1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2014-2018 The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ 9 10 #include <linux/debugfs.h> 11 #include <linux/dma-buf.h> 12 13 #include <drm/drm_atomic.h> 14 #include <drm/drm_atomic_uapi.h> 15 #include <drm/drm_damage_helper.h> 16 #include <drm/drm_file.h> 17 #include <drm/drm_gem_atomic_helper.h> 18 19 #include "msm_drv.h" 20 #include "dpu_kms.h" 21 #include "dpu_formats.h" 22 #include "dpu_hw_sspp.h" 23 #include "dpu_trace.h" 24 #include "dpu_crtc.h" 25 #include "dpu_vbif.h" 26 #include "dpu_plane.h" 27 28 #define DPU_DEBUG_PLANE(pl, fmt, ...) DPU_DEBUG("plane%d " fmt,\ 29 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__) 30 31 #define DPU_ERROR_PLANE(pl, fmt, ...) DPU_ERROR("plane%d " fmt,\ 32 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__) 33 34 #define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci)) 35 #define PHASE_STEP_SHIFT 21 36 #define PHASE_STEP_UNIT_SCALE ((int) (1 << PHASE_STEP_SHIFT)) 37 #define PHASE_RESIDUAL 15 38 39 #define SHARP_STRENGTH_DEFAULT 32 40 #define SHARP_EDGE_THR_DEFAULT 112 41 #define SHARP_SMOOTH_THR_DEFAULT 8 42 #define SHARP_NOISE_THR_DEFAULT 2 43 44 #define DPU_NAME_SIZE 12 45 46 #define DPU_PLANE_COLOR_FILL_FLAG BIT(31) 47 #define DPU_ZPOS_MAX 255 48 49 /* multirect rect index */ 50 enum { 51 R0, 52 R1, 53 R_MAX 54 }; 55 56 /* 57 * Default Preload Values 58 */ 59 #define DPU_QSEED3_DEFAULT_PRELOAD_H 0x4 60 #define DPU_QSEED3_DEFAULT_PRELOAD_V 0x3 61 #define DPU_QSEED4_DEFAULT_PRELOAD_V 0x2 62 #define DPU_QSEED4_DEFAULT_PRELOAD_H 0x4 63 64 #define DEFAULT_REFRESH_RATE 60 65 66 static const uint32_t qcom_compressed_supported_formats[] = { 67 DRM_FORMAT_ABGR8888, 68 DRM_FORMAT_ARGB8888, 69 DRM_FORMAT_XBGR8888, 70 DRM_FORMAT_XRGB8888, 71 DRM_FORMAT_BGR565, 72 73 DRM_FORMAT_NV12, 74 }; 75 76 /** 77 * enum dpu_plane_qos - Different qos configurations for each pipe 78 * 79 * @DPU_PLANE_QOS_VBLANK_CTRL: Setup VBLANK qos for the pipe. 80 * @DPU_PLANE_QOS_VBLANK_AMORTIZE: Enables Amortization within pipe. 81 * this configuration is mutually exclusive from VBLANK_CTRL. 82 * @DPU_PLANE_QOS_PANIC_CTRL: Setup panic for the pipe. 83 */ 84 enum dpu_plane_qos { 85 DPU_PLANE_QOS_VBLANK_CTRL = BIT(0), 86 DPU_PLANE_QOS_VBLANK_AMORTIZE = BIT(1), 87 DPU_PLANE_QOS_PANIC_CTRL = BIT(2), 88 }; 89 90 /* 91 * struct dpu_plane - local dpu plane structure 92 * @aspace: address space pointer 93 * @csc_ptr: Points to dpu_csc_cfg structure to use for current 94 * @mplane_list: List of multirect planes of the same pipe 95 * @catalog: Points to dpu catalog structure 96 * @revalidate: force revalidation of all the plane properties 97 */ 98 struct dpu_plane { 99 struct drm_plane base; 100 101 struct mutex lock; 102 103 enum dpu_sspp pipe; 104 uint32_t features; /* capabilities from catalog */ 105 106 struct dpu_hw_pipe *pipe_hw; 107 struct dpu_hw_pipe_cfg pipe_cfg; 108 struct dpu_hw_pipe_qos_cfg pipe_qos_cfg; 109 uint32_t color_fill; 110 bool is_error; 111 bool is_rt_pipe; 112 bool is_virtual; 113 struct list_head mplane_list; 114 struct dpu_mdss_cfg *catalog; 115 116 struct dpu_csc_cfg *csc_ptr; 117 118 const struct dpu_sspp_sub_blks *pipe_sblk; 119 char pipe_name[DPU_NAME_SIZE]; 120 121 /* debugfs related stuff */ 122 struct dentry *debugfs_root; 123 struct dpu_debugfs_regset32 debugfs_src; 124 struct dpu_debugfs_regset32 debugfs_scaler; 125 struct dpu_debugfs_regset32 debugfs_csc; 126 bool debugfs_default_scale; 127 }; 128 129 static const uint64_t supported_format_modifiers[] = { 130 DRM_FORMAT_MOD_QCOM_COMPRESSED, 131 DRM_FORMAT_MOD_LINEAR, 132 DRM_FORMAT_MOD_INVALID 133 }; 134 135 #define to_dpu_plane(x) container_of(x, struct dpu_plane, base) 136 137 static struct dpu_kms *_dpu_plane_get_kms(struct drm_plane *plane) 138 { 139 struct msm_drm_private *priv = plane->dev->dev_private; 140 141 return to_dpu_kms(priv->kms); 142 } 143 144 /** 145 * _dpu_plane_calc_bw - calculate bandwidth required for a plane 146 * @plane: Pointer to drm plane. 147 * @fb: Pointer to framebuffer associated with the given plane 148 * Result: Updates calculated bandwidth in the plane state. 149 * BW Equation: src_w * src_h * bpp * fps * (v_total / v_dest) 150 * Prefill BW Equation: line src bytes * line_time 151 */ 152 static void _dpu_plane_calc_bw(struct drm_plane *plane, 153 struct drm_framebuffer *fb) 154 { 155 struct dpu_plane *pdpu = to_dpu_plane(plane); 156 struct dpu_plane_state *pstate; 157 struct drm_display_mode *mode; 158 const struct dpu_format *fmt = NULL; 159 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 160 int src_width, src_height, dst_height, fps; 161 u64 plane_prefill_bw; 162 u64 plane_bw; 163 u32 hw_latency_lines; 164 u64 scale_factor; 165 int vbp, vpw, vfp; 166 167 pstate = to_dpu_plane_state(plane->state); 168 mode = &plane->state->crtc->mode; 169 170 fmt = dpu_get_dpu_format_ext(fb->format->format, fb->modifier); 171 172 src_width = drm_rect_width(&pdpu->pipe_cfg.src_rect); 173 src_height = drm_rect_height(&pdpu->pipe_cfg.src_rect); 174 dst_height = drm_rect_height(&pdpu->pipe_cfg.dst_rect); 175 fps = drm_mode_vrefresh(mode); 176 vbp = mode->vtotal - mode->vsync_end; 177 vpw = mode->vsync_end - mode->vsync_start; 178 vfp = mode->vsync_start - mode->vdisplay; 179 hw_latency_lines = dpu_kms->catalog->perf.min_prefill_lines; 180 scale_factor = src_height > dst_height ? 181 mult_frac(src_height, 1, dst_height) : 1; 182 183 plane_bw = 184 src_width * mode->vtotal * fps * fmt->bpp * 185 scale_factor; 186 187 plane_prefill_bw = 188 src_width * hw_latency_lines * fps * fmt->bpp * 189 scale_factor * mode->vtotal; 190 191 if ((vbp+vpw) > hw_latency_lines) 192 do_div(plane_prefill_bw, (vbp+vpw)); 193 else if ((vbp+vpw+vfp) < hw_latency_lines) 194 do_div(plane_prefill_bw, (vbp+vpw+vfp)); 195 else 196 do_div(plane_prefill_bw, hw_latency_lines); 197 198 199 pstate->plane_fetch_bw = max(plane_bw, plane_prefill_bw); 200 } 201 202 /** 203 * _dpu_plane_calc_clk - calculate clock required for a plane 204 * @plane: Pointer to drm plane. 205 * Result: Updates calculated clock in the plane state. 206 * Clock equation: dst_w * v_total * fps * (src_h / dst_h) 207 */ 208 static void _dpu_plane_calc_clk(struct drm_plane *plane) 209 { 210 struct dpu_plane *pdpu = to_dpu_plane(plane); 211 struct dpu_plane_state *pstate; 212 struct drm_display_mode *mode; 213 int dst_width, src_height, dst_height, fps; 214 215 pstate = to_dpu_plane_state(plane->state); 216 mode = &plane->state->crtc->mode; 217 218 src_height = drm_rect_height(&pdpu->pipe_cfg.src_rect); 219 dst_width = drm_rect_width(&pdpu->pipe_cfg.dst_rect); 220 dst_height = drm_rect_height(&pdpu->pipe_cfg.dst_rect); 221 fps = drm_mode_vrefresh(mode); 222 223 pstate->plane_clk = 224 dst_width * mode->vtotal * fps; 225 226 if (src_height > dst_height) { 227 pstate->plane_clk *= src_height; 228 do_div(pstate->plane_clk, dst_height); 229 } 230 } 231 232 /** 233 * _dpu_plane_calc_fill_level - calculate fill level of the given source format 234 * @plane: Pointer to drm plane 235 * @fmt: Pointer to source buffer format 236 * @src_width: width of source buffer 237 * Return: fill level corresponding to the source buffer/format or 0 if error 238 */ 239 static int _dpu_plane_calc_fill_level(struct drm_plane *plane, 240 const struct dpu_format *fmt, u32 src_width) 241 { 242 struct dpu_plane *pdpu, *tmp; 243 struct dpu_plane_state *pstate; 244 u32 fixed_buff_size; 245 u32 total_fl; 246 247 if (!fmt || !plane->state || !src_width || !fmt->bpp) { 248 DPU_ERROR("invalid arguments\n"); 249 return 0; 250 } 251 252 pdpu = to_dpu_plane(plane); 253 pstate = to_dpu_plane_state(plane->state); 254 fixed_buff_size = pdpu->catalog->caps->pixel_ram_size; 255 256 list_for_each_entry(tmp, &pdpu->mplane_list, mplane_list) { 257 if (!tmp->base.state->visible) 258 continue; 259 DPU_DEBUG("plane%d/%d src_width:%d/%d\n", 260 pdpu->base.base.id, tmp->base.base.id, 261 src_width, 262 drm_rect_width(&tmp->pipe_cfg.src_rect)); 263 src_width = max_t(u32, src_width, 264 drm_rect_width(&tmp->pipe_cfg.src_rect)); 265 } 266 267 if (fmt->fetch_planes == DPU_PLANE_PSEUDO_PLANAR) { 268 if (fmt->chroma_sample == DPU_CHROMA_420) { 269 /* NV12 */ 270 total_fl = (fixed_buff_size / 2) / 271 ((src_width + 32) * fmt->bpp); 272 } else { 273 /* non NV12 */ 274 total_fl = (fixed_buff_size / 2) * 2 / 275 ((src_width + 32) * fmt->bpp); 276 } 277 } else { 278 if (pstate->multirect_mode == DPU_SSPP_MULTIRECT_PARALLEL) { 279 total_fl = (fixed_buff_size / 2) * 2 / 280 ((src_width + 32) * fmt->bpp); 281 } else { 282 total_fl = (fixed_buff_size) * 2 / 283 ((src_width + 32) * fmt->bpp); 284 } 285 } 286 287 DPU_DEBUG("plane%u: pnum:%d fmt: %4.4s w:%u fl:%u\n", 288 plane->base.id, pdpu->pipe - SSPP_VIG0, 289 (char *)&fmt->base.pixel_format, 290 src_width, total_fl); 291 292 return total_fl; 293 } 294 295 /** 296 * _dpu_plane_get_qos_lut - get LUT mapping based on fill level 297 * @tbl: Pointer to LUT table 298 * @total_fl: fill level 299 * Return: LUT setting corresponding to the fill level 300 */ 301 static u64 _dpu_plane_get_qos_lut(const struct dpu_qos_lut_tbl *tbl, 302 u32 total_fl) 303 { 304 int i; 305 306 if (!tbl || !tbl->nentry || !tbl->entries) 307 return 0; 308 309 for (i = 0; i < tbl->nentry; i++) 310 if (total_fl <= tbl->entries[i].fl) 311 return tbl->entries[i].lut; 312 313 /* if last fl is zero, use as default */ 314 if (!tbl->entries[i-1].fl) 315 return tbl->entries[i-1].lut; 316 317 return 0; 318 } 319 320 /** 321 * _dpu_plane_set_qos_lut - set QoS LUT of the given plane 322 * @plane: Pointer to drm plane 323 * @fb: Pointer to framebuffer associated with the given plane 324 */ 325 static void _dpu_plane_set_qos_lut(struct drm_plane *plane, 326 struct drm_framebuffer *fb) 327 { 328 struct dpu_plane *pdpu = to_dpu_plane(plane); 329 const struct dpu_format *fmt = NULL; 330 u64 qos_lut; 331 u32 total_fl = 0, lut_usage; 332 333 if (!pdpu->is_rt_pipe) { 334 lut_usage = DPU_QOS_LUT_USAGE_NRT; 335 } else { 336 fmt = dpu_get_dpu_format_ext( 337 fb->format->format, 338 fb->modifier); 339 total_fl = _dpu_plane_calc_fill_level(plane, fmt, 340 drm_rect_width(&pdpu->pipe_cfg.src_rect)); 341 342 if (fmt && DPU_FORMAT_IS_LINEAR(fmt)) 343 lut_usage = DPU_QOS_LUT_USAGE_LINEAR; 344 else 345 lut_usage = DPU_QOS_LUT_USAGE_MACROTILE; 346 } 347 348 qos_lut = _dpu_plane_get_qos_lut( 349 &pdpu->catalog->perf.qos_lut_tbl[lut_usage], total_fl); 350 351 pdpu->pipe_qos_cfg.creq_lut = qos_lut; 352 353 trace_dpu_perf_set_qos_luts(pdpu->pipe - SSPP_VIG0, 354 (fmt) ? fmt->base.pixel_format : 0, 355 pdpu->is_rt_pipe, total_fl, qos_lut, lut_usage); 356 357 DPU_DEBUG("plane%u: pnum:%d fmt: %4.4s rt:%d fl:%u lut:0x%llx\n", 358 plane->base.id, 359 pdpu->pipe - SSPP_VIG0, 360 fmt ? (char *)&fmt->base.pixel_format : NULL, 361 pdpu->is_rt_pipe, total_fl, qos_lut); 362 363 pdpu->pipe_hw->ops.setup_creq_lut(pdpu->pipe_hw, &pdpu->pipe_qos_cfg); 364 } 365 366 /** 367 * _dpu_plane_set_panic_lut - set danger/safe LUT of the given plane 368 * @plane: Pointer to drm plane 369 * @fb: Pointer to framebuffer associated with the given plane 370 */ 371 static void _dpu_plane_set_danger_lut(struct drm_plane *plane, 372 struct drm_framebuffer *fb) 373 { 374 struct dpu_plane *pdpu = to_dpu_plane(plane); 375 const struct dpu_format *fmt = NULL; 376 u32 danger_lut, safe_lut; 377 378 if (!pdpu->is_rt_pipe) { 379 danger_lut = pdpu->catalog->perf.danger_lut_tbl 380 [DPU_QOS_LUT_USAGE_NRT]; 381 safe_lut = pdpu->catalog->perf.safe_lut_tbl 382 [DPU_QOS_LUT_USAGE_NRT]; 383 } else { 384 fmt = dpu_get_dpu_format_ext( 385 fb->format->format, 386 fb->modifier); 387 388 if (fmt && DPU_FORMAT_IS_LINEAR(fmt)) { 389 danger_lut = pdpu->catalog->perf.danger_lut_tbl 390 [DPU_QOS_LUT_USAGE_LINEAR]; 391 safe_lut = pdpu->catalog->perf.safe_lut_tbl 392 [DPU_QOS_LUT_USAGE_LINEAR]; 393 } else { 394 danger_lut = pdpu->catalog->perf.danger_lut_tbl 395 [DPU_QOS_LUT_USAGE_MACROTILE]; 396 safe_lut = pdpu->catalog->perf.safe_lut_tbl 397 [DPU_QOS_LUT_USAGE_MACROTILE]; 398 } 399 } 400 401 pdpu->pipe_qos_cfg.danger_lut = danger_lut; 402 pdpu->pipe_qos_cfg.safe_lut = safe_lut; 403 404 trace_dpu_perf_set_danger_luts(pdpu->pipe - SSPP_VIG0, 405 (fmt) ? fmt->base.pixel_format : 0, 406 (fmt) ? fmt->fetch_mode : 0, 407 pdpu->pipe_qos_cfg.danger_lut, 408 pdpu->pipe_qos_cfg.safe_lut); 409 410 DPU_DEBUG("plane%u: pnum:%d fmt: %4.4s mode:%d luts[0x%x, 0x%x]\n", 411 plane->base.id, 412 pdpu->pipe - SSPP_VIG0, 413 fmt ? (char *)&fmt->base.pixel_format : NULL, 414 fmt ? fmt->fetch_mode : -1, 415 pdpu->pipe_qos_cfg.danger_lut, 416 pdpu->pipe_qos_cfg.safe_lut); 417 418 pdpu->pipe_hw->ops.setup_danger_safe_lut(pdpu->pipe_hw, 419 &pdpu->pipe_qos_cfg); 420 } 421 422 /** 423 * _dpu_plane_set_qos_ctrl - set QoS control of the given plane 424 * @plane: Pointer to drm plane 425 * @enable: true to enable QoS control 426 * @flags: QoS control mode (enum dpu_plane_qos) 427 */ 428 static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane, 429 bool enable, u32 flags) 430 { 431 struct dpu_plane *pdpu = to_dpu_plane(plane); 432 433 if (flags & DPU_PLANE_QOS_VBLANK_CTRL) { 434 pdpu->pipe_qos_cfg.creq_vblank = pdpu->pipe_sblk->creq_vblank; 435 pdpu->pipe_qos_cfg.danger_vblank = 436 pdpu->pipe_sblk->danger_vblank; 437 pdpu->pipe_qos_cfg.vblank_en = enable; 438 } 439 440 if (flags & DPU_PLANE_QOS_VBLANK_AMORTIZE) { 441 /* this feature overrules previous VBLANK_CTRL */ 442 pdpu->pipe_qos_cfg.vblank_en = false; 443 pdpu->pipe_qos_cfg.creq_vblank = 0; /* clear vblank bits */ 444 } 445 446 if (flags & DPU_PLANE_QOS_PANIC_CTRL) 447 pdpu->pipe_qos_cfg.danger_safe_en = enable; 448 449 if (!pdpu->is_rt_pipe) { 450 pdpu->pipe_qos_cfg.vblank_en = false; 451 pdpu->pipe_qos_cfg.danger_safe_en = false; 452 } 453 454 DPU_DEBUG("plane%u: pnum:%d ds:%d vb:%d pri[0x%x, 0x%x] is_rt:%d\n", 455 plane->base.id, 456 pdpu->pipe - SSPP_VIG0, 457 pdpu->pipe_qos_cfg.danger_safe_en, 458 pdpu->pipe_qos_cfg.vblank_en, 459 pdpu->pipe_qos_cfg.creq_vblank, 460 pdpu->pipe_qos_cfg.danger_vblank, 461 pdpu->is_rt_pipe); 462 463 pdpu->pipe_hw->ops.setup_qos_ctrl(pdpu->pipe_hw, 464 &pdpu->pipe_qos_cfg); 465 } 466 467 /** 468 * _dpu_plane_set_ot_limit - set OT limit for the given plane 469 * @plane: Pointer to drm plane 470 * @crtc: Pointer to drm crtc 471 */ 472 static void _dpu_plane_set_ot_limit(struct drm_plane *plane, 473 struct drm_crtc *crtc) 474 { 475 struct dpu_plane *pdpu = to_dpu_plane(plane); 476 struct dpu_vbif_set_ot_params ot_params; 477 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 478 479 memset(&ot_params, 0, sizeof(ot_params)); 480 ot_params.xin_id = pdpu->pipe_hw->cap->xin_id; 481 ot_params.num = pdpu->pipe_hw->idx - SSPP_NONE; 482 ot_params.width = drm_rect_width(&pdpu->pipe_cfg.src_rect); 483 ot_params.height = drm_rect_height(&pdpu->pipe_cfg.src_rect); 484 ot_params.is_wfd = !pdpu->is_rt_pipe; 485 ot_params.frame_rate = drm_mode_vrefresh(&crtc->mode); 486 ot_params.vbif_idx = VBIF_RT; 487 ot_params.clk_ctrl = pdpu->pipe_hw->cap->clk_ctrl; 488 ot_params.rd = true; 489 490 dpu_vbif_set_ot_limit(dpu_kms, &ot_params); 491 } 492 493 /** 494 * _dpu_plane_set_vbif_qos - set vbif QoS for the given plane 495 * @plane: Pointer to drm plane 496 */ 497 static void _dpu_plane_set_qos_remap(struct drm_plane *plane) 498 { 499 struct dpu_plane *pdpu = to_dpu_plane(plane); 500 struct dpu_vbif_set_qos_params qos_params; 501 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 502 503 memset(&qos_params, 0, sizeof(qos_params)); 504 qos_params.vbif_idx = VBIF_RT; 505 qos_params.clk_ctrl = pdpu->pipe_hw->cap->clk_ctrl; 506 qos_params.xin_id = pdpu->pipe_hw->cap->xin_id; 507 qos_params.num = pdpu->pipe_hw->idx - SSPP_VIG0; 508 qos_params.is_rt = pdpu->is_rt_pipe; 509 510 DPU_DEBUG("plane%d pipe:%d vbif:%d xin:%d rt:%d, clk_ctrl:%d\n", 511 plane->base.id, qos_params.num, 512 qos_params.vbif_idx, 513 qos_params.xin_id, qos_params.is_rt, 514 qos_params.clk_ctrl); 515 516 dpu_vbif_set_qos_remap(dpu_kms, &qos_params); 517 } 518 519 static void _dpu_plane_set_scanout(struct drm_plane *plane, 520 struct dpu_plane_state *pstate, 521 struct dpu_hw_pipe_cfg *pipe_cfg, 522 struct drm_framebuffer *fb) 523 { 524 struct dpu_plane *pdpu = to_dpu_plane(plane); 525 struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); 526 struct msm_gem_address_space *aspace = kms->base.aspace; 527 int ret; 528 529 ret = dpu_format_populate_layout(aspace, fb, &pipe_cfg->layout); 530 if (ret == -EAGAIN) 531 DPU_DEBUG_PLANE(pdpu, "not updating same src addrs\n"); 532 else if (ret) 533 DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret); 534 else if (pdpu->pipe_hw->ops.setup_sourceaddress) { 535 trace_dpu_plane_set_scanout(pdpu->pipe_hw->idx, 536 &pipe_cfg->layout, 537 pstate->multirect_index); 538 pdpu->pipe_hw->ops.setup_sourceaddress(pdpu->pipe_hw, pipe_cfg, 539 pstate->multirect_index); 540 } 541 } 542 543 static void _dpu_plane_setup_scaler3(struct dpu_plane *pdpu, 544 struct dpu_plane_state *pstate, 545 uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h, 546 struct dpu_hw_scaler3_cfg *scale_cfg, 547 const struct dpu_format *fmt, 548 uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v) 549 { 550 uint32_t i; 551 552 memset(scale_cfg, 0, sizeof(*scale_cfg)); 553 memset(&pstate->pixel_ext, 0, sizeof(struct dpu_hw_pixel_ext)); 554 555 scale_cfg->phase_step_x[DPU_SSPP_COMP_0] = 556 mult_frac((1 << PHASE_STEP_SHIFT), src_w, dst_w); 557 scale_cfg->phase_step_y[DPU_SSPP_COMP_0] = 558 mult_frac((1 << PHASE_STEP_SHIFT), src_h, dst_h); 559 560 561 scale_cfg->phase_step_y[DPU_SSPP_COMP_1_2] = 562 scale_cfg->phase_step_y[DPU_SSPP_COMP_0] / chroma_subsmpl_v; 563 scale_cfg->phase_step_x[DPU_SSPP_COMP_1_2] = 564 scale_cfg->phase_step_x[DPU_SSPP_COMP_0] / chroma_subsmpl_h; 565 566 scale_cfg->phase_step_x[DPU_SSPP_COMP_2] = 567 scale_cfg->phase_step_x[DPU_SSPP_COMP_1_2]; 568 scale_cfg->phase_step_y[DPU_SSPP_COMP_2] = 569 scale_cfg->phase_step_y[DPU_SSPP_COMP_1_2]; 570 571 scale_cfg->phase_step_x[DPU_SSPP_COMP_3] = 572 scale_cfg->phase_step_x[DPU_SSPP_COMP_0]; 573 scale_cfg->phase_step_y[DPU_SSPP_COMP_3] = 574 scale_cfg->phase_step_y[DPU_SSPP_COMP_0]; 575 576 for (i = 0; i < DPU_MAX_PLANES; i++) { 577 scale_cfg->src_width[i] = src_w; 578 scale_cfg->src_height[i] = src_h; 579 if (i == DPU_SSPP_COMP_1_2 || i == DPU_SSPP_COMP_2) { 580 scale_cfg->src_width[i] /= chroma_subsmpl_h; 581 scale_cfg->src_height[i] /= chroma_subsmpl_v; 582 } 583 584 if (pdpu->pipe_hw->cap->features & 585 BIT(DPU_SSPP_SCALER_QSEED4)) { 586 scale_cfg->preload_x[i] = DPU_QSEED4_DEFAULT_PRELOAD_H; 587 scale_cfg->preload_y[i] = DPU_QSEED4_DEFAULT_PRELOAD_V; 588 } else { 589 scale_cfg->preload_x[i] = DPU_QSEED3_DEFAULT_PRELOAD_H; 590 scale_cfg->preload_y[i] = DPU_QSEED3_DEFAULT_PRELOAD_V; 591 } 592 593 pstate->pixel_ext.num_ext_pxls_top[i] = 594 scale_cfg->src_height[i]; 595 pstate->pixel_ext.num_ext_pxls_left[i] = 596 scale_cfg->src_width[i]; 597 } 598 if (!(DPU_FORMAT_IS_YUV(fmt)) && (src_h == dst_h) 599 && (src_w == dst_w)) 600 return; 601 602 scale_cfg->dst_width = dst_w; 603 scale_cfg->dst_height = dst_h; 604 scale_cfg->y_rgb_filter_cfg = DPU_SCALE_BIL; 605 scale_cfg->uv_filter_cfg = DPU_SCALE_BIL; 606 scale_cfg->alpha_filter_cfg = DPU_SCALE_ALPHA_BIL; 607 scale_cfg->lut_flag = 0; 608 scale_cfg->blend_cfg = 1; 609 scale_cfg->enable = 1; 610 } 611 612 static void _dpu_plane_setup_csc(struct dpu_plane *pdpu) 613 { 614 static const struct dpu_csc_cfg dpu_csc_YUV2RGB_601L = { 615 { 616 /* S15.16 format */ 617 0x00012A00, 0x00000000, 0x00019880, 618 0x00012A00, 0xFFFF9B80, 0xFFFF3000, 619 0x00012A00, 0x00020480, 0x00000000, 620 }, 621 /* signed bias */ 622 { 0xfff0, 0xff80, 0xff80,}, 623 { 0x0, 0x0, 0x0,}, 624 /* unsigned clamp */ 625 { 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0,}, 626 { 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,}, 627 }; 628 static const struct dpu_csc_cfg dpu_csc10_YUV2RGB_601L = { 629 { 630 /* S15.16 format */ 631 0x00012A00, 0x00000000, 0x00019880, 632 0x00012A00, 0xFFFF9B80, 0xFFFF3000, 633 0x00012A00, 0x00020480, 0x00000000, 634 }, 635 /* signed bias */ 636 { 0xffc0, 0xfe00, 0xfe00,}, 637 { 0x0, 0x0, 0x0,}, 638 /* unsigned clamp */ 639 { 0x40, 0x3ac, 0x40, 0x3c0, 0x40, 0x3c0,}, 640 { 0x00, 0x3ff, 0x00, 0x3ff, 0x00, 0x3ff,}, 641 }; 642 643 if (!pdpu) { 644 DPU_ERROR("invalid plane\n"); 645 return; 646 } 647 648 if (BIT(DPU_SSPP_CSC_10BIT) & pdpu->features) 649 pdpu->csc_ptr = (struct dpu_csc_cfg *)&dpu_csc10_YUV2RGB_601L; 650 else 651 pdpu->csc_ptr = (struct dpu_csc_cfg *)&dpu_csc_YUV2RGB_601L; 652 653 DPU_DEBUG_PLANE(pdpu, "using 0x%X 0x%X 0x%X...\n", 654 pdpu->csc_ptr->csc_mv[0], 655 pdpu->csc_ptr->csc_mv[1], 656 pdpu->csc_ptr->csc_mv[2]); 657 } 658 659 static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu, 660 struct dpu_plane_state *pstate, 661 const struct dpu_format *fmt, bool color_fill) 662 { 663 const struct drm_format_info *info = drm_format_info(fmt->base.pixel_format); 664 665 /* don't chroma subsample if decimating */ 666 /* update scaler. calculate default config for QSEED3 */ 667 _dpu_plane_setup_scaler3(pdpu, pstate, 668 drm_rect_width(&pdpu->pipe_cfg.src_rect), 669 drm_rect_height(&pdpu->pipe_cfg.src_rect), 670 drm_rect_width(&pdpu->pipe_cfg.dst_rect), 671 drm_rect_height(&pdpu->pipe_cfg.dst_rect), 672 &pstate->scaler3_cfg, fmt, 673 info->hsub, info->vsub); 674 } 675 676 /** 677 * _dpu_plane_color_fill - enables color fill on plane 678 * @pdpu: Pointer to DPU plane object 679 * @color: RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red 680 * @alpha: 8-bit fill alpha value, 255 selects 100% alpha 681 * Returns: 0 on success 682 */ 683 static int _dpu_plane_color_fill(struct dpu_plane *pdpu, 684 uint32_t color, uint32_t alpha) 685 { 686 const struct dpu_format *fmt; 687 const struct drm_plane *plane = &pdpu->base; 688 struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state); 689 690 DPU_DEBUG_PLANE(pdpu, "\n"); 691 692 /* 693 * select fill format to match user property expectation, 694 * h/w only supports RGB variants 695 */ 696 fmt = dpu_get_dpu_format(DRM_FORMAT_ABGR8888); 697 698 /* update sspp */ 699 if (fmt && pdpu->pipe_hw->ops.setup_solidfill) { 700 pdpu->pipe_hw->ops.setup_solidfill(pdpu->pipe_hw, 701 (color & 0xFFFFFF) | ((alpha & 0xFF) << 24), 702 pstate->multirect_index); 703 704 /* override scaler/decimation if solid fill */ 705 pdpu->pipe_cfg.src_rect.x1 = 0; 706 pdpu->pipe_cfg.src_rect.y1 = 0; 707 pdpu->pipe_cfg.src_rect.x2 = 708 drm_rect_width(&pdpu->pipe_cfg.dst_rect); 709 pdpu->pipe_cfg.src_rect.y2 = 710 drm_rect_height(&pdpu->pipe_cfg.dst_rect); 711 _dpu_plane_setup_scaler(pdpu, pstate, fmt, true); 712 713 if (pdpu->pipe_hw->ops.setup_format) 714 pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw, 715 fmt, DPU_SSPP_SOLID_FILL, 716 pstate->multirect_index); 717 718 if (pdpu->pipe_hw->ops.setup_rects) 719 pdpu->pipe_hw->ops.setup_rects(pdpu->pipe_hw, 720 &pdpu->pipe_cfg, 721 pstate->multirect_index); 722 723 if (pdpu->pipe_hw->ops.setup_pe) 724 pdpu->pipe_hw->ops.setup_pe(pdpu->pipe_hw, 725 &pstate->pixel_ext); 726 727 if (pdpu->pipe_hw->ops.setup_scaler && 728 pstate->multirect_index != DPU_SSPP_RECT_1) 729 pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw, 730 &pdpu->pipe_cfg, &pstate->pixel_ext, 731 &pstate->scaler3_cfg); 732 } 733 734 return 0; 735 } 736 737 void dpu_plane_clear_multirect(const struct drm_plane_state *drm_state) 738 { 739 struct dpu_plane_state *pstate = to_dpu_plane_state(drm_state); 740 741 pstate->multirect_index = DPU_SSPP_RECT_SOLO; 742 pstate->multirect_mode = DPU_SSPP_MULTIRECT_NONE; 743 } 744 745 int dpu_plane_validate_multirect_v2(struct dpu_multirect_plane_states *plane) 746 { 747 struct dpu_plane_state *pstate[R_MAX]; 748 const struct drm_plane_state *drm_state[R_MAX]; 749 struct drm_rect src[R_MAX], dst[R_MAX]; 750 struct dpu_plane *dpu_plane[R_MAX]; 751 const struct dpu_format *fmt[R_MAX]; 752 int i, buffer_lines; 753 unsigned int max_tile_height = 1; 754 bool parallel_fetch_qualified = true; 755 bool has_tiled_rect = false; 756 757 for (i = 0; i < R_MAX; i++) { 758 const struct msm_format *msm_fmt; 759 760 drm_state[i] = i ? plane->r1 : plane->r0; 761 msm_fmt = msm_framebuffer_format(drm_state[i]->fb); 762 fmt[i] = to_dpu_format(msm_fmt); 763 764 if (DPU_FORMAT_IS_UBWC(fmt[i])) { 765 has_tiled_rect = true; 766 if (fmt[i]->tile_height > max_tile_height) 767 max_tile_height = fmt[i]->tile_height; 768 } 769 } 770 771 for (i = 0; i < R_MAX; i++) { 772 int width_threshold; 773 774 pstate[i] = to_dpu_plane_state(drm_state[i]); 775 dpu_plane[i] = to_dpu_plane(drm_state[i]->plane); 776 777 if (pstate[i] == NULL) { 778 DPU_ERROR("DPU plane state of plane id %d is NULL\n", 779 drm_state[i]->plane->base.id); 780 return -EINVAL; 781 } 782 783 src[i].x1 = drm_state[i]->src_x >> 16; 784 src[i].y1 = drm_state[i]->src_y >> 16; 785 src[i].x2 = src[i].x1 + (drm_state[i]->src_w >> 16); 786 src[i].y2 = src[i].y1 + (drm_state[i]->src_h >> 16); 787 788 dst[i] = drm_plane_state_dest(drm_state[i]); 789 790 if (drm_rect_calc_hscale(&src[i], &dst[i], 1, 1) != 1 || 791 drm_rect_calc_vscale(&src[i], &dst[i], 1, 1) != 1) { 792 DPU_ERROR_PLANE(dpu_plane[i], 793 "scaling is not supported in multirect mode\n"); 794 return -EINVAL; 795 } 796 797 if (DPU_FORMAT_IS_YUV(fmt[i])) { 798 DPU_ERROR_PLANE(dpu_plane[i], 799 "Unsupported format for multirect mode\n"); 800 return -EINVAL; 801 } 802 803 /** 804 * SSPP PD_MEM is split half - one for each RECT. 805 * Tiled formats need 5 lines of buffering while fetching 806 * whereas linear formats need only 2 lines. 807 * So we cannot support more than half of the supported SSPP 808 * width for tiled formats. 809 */ 810 width_threshold = dpu_plane[i]->catalog->caps->max_linewidth; 811 if (has_tiled_rect) 812 width_threshold /= 2; 813 814 if (parallel_fetch_qualified && 815 drm_rect_width(&src[i]) > width_threshold) 816 parallel_fetch_qualified = false; 817 818 } 819 820 /* Validate RECT's and set the mode */ 821 822 /* Prefer PARALLEL FETCH Mode over TIME_MX Mode */ 823 if (parallel_fetch_qualified) { 824 pstate[R0]->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; 825 pstate[R1]->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; 826 827 goto done; 828 } 829 830 /* TIME_MX Mode */ 831 buffer_lines = 2 * max_tile_height; 832 833 if (dst[R1].y1 >= dst[R0].y2 + buffer_lines || 834 dst[R0].y1 >= dst[R1].y2 + buffer_lines) { 835 pstate[R0]->multirect_mode = DPU_SSPP_MULTIRECT_TIME_MX; 836 pstate[R1]->multirect_mode = DPU_SSPP_MULTIRECT_TIME_MX; 837 } else { 838 DPU_ERROR( 839 "No multirect mode possible for the planes (%d - %d)\n", 840 drm_state[R0]->plane->base.id, 841 drm_state[R1]->plane->base.id); 842 return -EINVAL; 843 } 844 845 done: 846 if (dpu_plane[R0]->is_virtual) { 847 pstate[R0]->multirect_index = DPU_SSPP_RECT_1; 848 pstate[R1]->multirect_index = DPU_SSPP_RECT_0; 849 } else { 850 pstate[R0]->multirect_index = DPU_SSPP_RECT_0; 851 pstate[R1]->multirect_index = DPU_SSPP_RECT_1; 852 } 853 854 DPU_DEBUG_PLANE(dpu_plane[R0], "R0: %d - %d\n", 855 pstate[R0]->multirect_mode, pstate[R0]->multirect_index); 856 DPU_DEBUG_PLANE(dpu_plane[R1], "R1: %d - %d\n", 857 pstate[R1]->multirect_mode, pstate[R1]->multirect_index); 858 return 0; 859 } 860 861 /** 862 * dpu_plane_get_ctl_flush - get control flush for the given plane 863 * @plane: Pointer to drm plane structure 864 * @ctl: Pointer to hardware control driver 865 * @flush_sspp: Pointer to sspp flush control word 866 */ 867 void dpu_plane_get_ctl_flush(struct drm_plane *plane, struct dpu_hw_ctl *ctl, 868 u32 *flush_sspp) 869 { 870 *flush_sspp = ctl->ops.get_bitmask_sspp(ctl, dpu_plane_pipe(plane)); 871 } 872 873 static int dpu_plane_prepare_fb(struct drm_plane *plane, 874 struct drm_plane_state *new_state) 875 { 876 struct drm_framebuffer *fb = new_state->fb; 877 struct dpu_plane *pdpu = to_dpu_plane(plane); 878 struct dpu_plane_state *pstate = to_dpu_plane_state(new_state); 879 struct dpu_hw_fmt_layout layout; 880 struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); 881 int ret; 882 883 if (!new_state->fb) 884 return 0; 885 886 DPU_DEBUG_PLANE(pdpu, "FB[%u]\n", fb->base.id); 887 888 /* cache aspace */ 889 pstate->aspace = kms->base.aspace; 890 891 /* 892 * TODO: Need to sort out the msm_framebuffer_prepare() call below so 893 * we can use msm_atomic_prepare_fb() instead of doing the 894 * implicit fence and fb prepare by hand here. 895 */ 896 drm_gem_plane_helper_prepare_fb(plane, new_state); 897 898 if (pstate->aspace) { 899 ret = msm_framebuffer_prepare(new_state->fb, 900 pstate->aspace); 901 if (ret) { 902 DPU_ERROR("failed to prepare framebuffer\n"); 903 return ret; 904 } 905 } 906 907 /* validate framebuffer layout before commit */ 908 ret = dpu_format_populate_layout(pstate->aspace, 909 new_state->fb, &layout); 910 if (ret) { 911 DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret); 912 return ret; 913 } 914 915 return 0; 916 } 917 918 static void dpu_plane_cleanup_fb(struct drm_plane *plane, 919 struct drm_plane_state *old_state) 920 { 921 struct dpu_plane *pdpu = to_dpu_plane(plane); 922 struct dpu_plane_state *old_pstate; 923 924 if (!old_state || !old_state->fb) 925 return; 926 927 old_pstate = to_dpu_plane_state(old_state); 928 929 DPU_DEBUG_PLANE(pdpu, "FB[%u]\n", old_state->fb->base.id); 930 931 msm_framebuffer_cleanup(old_state->fb, old_pstate->aspace); 932 } 933 934 static bool dpu_plane_validate_src(struct drm_rect *src, 935 struct drm_rect *fb_rect, 936 uint32_t min_src_size) 937 { 938 /* Ensure fb size is supported */ 939 if (drm_rect_width(fb_rect) > MAX_IMG_WIDTH || 940 drm_rect_height(fb_rect) > MAX_IMG_HEIGHT) 941 return false; 942 943 /* Ensure src rect is above the minimum size */ 944 if (drm_rect_width(src) < min_src_size || 945 drm_rect_height(src) < min_src_size) 946 return false; 947 948 /* Ensure src is fully encapsulated in fb */ 949 return drm_rect_intersect(fb_rect, src) && 950 drm_rect_equals(fb_rect, src); 951 } 952 953 static int dpu_plane_atomic_check(struct drm_plane *plane, 954 struct drm_atomic_state *state) 955 { 956 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 957 plane); 958 int ret = 0, min_scale; 959 struct dpu_plane *pdpu = to_dpu_plane(plane); 960 struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state); 961 const struct drm_crtc_state *crtc_state = NULL; 962 const struct dpu_format *fmt; 963 struct drm_rect src, dst, fb_rect = { 0 }; 964 uint32_t min_src_size, max_linewidth; 965 966 if (new_plane_state->crtc) 967 crtc_state = drm_atomic_get_new_crtc_state(state, 968 new_plane_state->crtc); 969 970 min_scale = FRAC_16_16(1, pdpu->pipe_sblk->maxupscale); 971 ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state, 972 min_scale, 973 pdpu->pipe_sblk->maxdwnscale << 16, 974 true, true); 975 if (ret) { 976 DPU_DEBUG_PLANE(pdpu, "Check plane state failed (%d)\n", ret); 977 return ret; 978 } 979 if (!new_plane_state->visible) 980 return 0; 981 982 src.x1 = new_plane_state->src_x >> 16; 983 src.y1 = new_plane_state->src_y >> 16; 984 src.x2 = src.x1 + (new_plane_state->src_w >> 16); 985 src.y2 = src.y1 + (new_plane_state->src_h >> 16); 986 987 dst = drm_plane_state_dest(new_plane_state); 988 989 fb_rect.x2 = new_plane_state->fb->width; 990 fb_rect.y2 = new_plane_state->fb->height; 991 992 max_linewidth = pdpu->catalog->caps->max_linewidth; 993 994 fmt = to_dpu_format(msm_framebuffer_format(new_plane_state->fb)); 995 996 min_src_size = DPU_FORMAT_IS_YUV(fmt) ? 2 : 1; 997 998 if (DPU_FORMAT_IS_YUV(fmt) && 999 (!(pdpu->features & DPU_SSPP_SCALER) || 1000 !(pdpu->features & (BIT(DPU_SSPP_CSC) 1001 | BIT(DPU_SSPP_CSC_10BIT))))) { 1002 DPU_DEBUG_PLANE(pdpu, 1003 "plane doesn't have scaler/csc for yuv\n"); 1004 return -EINVAL; 1005 1006 /* check src bounds */ 1007 } else if (!dpu_plane_validate_src(&src, &fb_rect, min_src_size)) { 1008 DPU_DEBUG_PLANE(pdpu, "invalid source " DRM_RECT_FMT "\n", 1009 DRM_RECT_ARG(&src)); 1010 return -E2BIG; 1011 1012 /* valid yuv image */ 1013 } else if (DPU_FORMAT_IS_YUV(fmt) && 1014 (src.x1 & 0x1 || src.y1 & 0x1 || 1015 drm_rect_width(&src) & 0x1 || 1016 drm_rect_height(&src) & 0x1)) { 1017 DPU_DEBUG_PLANE(pdpu, "invalid yuv source " DRM_RECT_FMT "\n", 1018 DRM_RECT_ARG(&src)); 1019 return -EINVAL; 1020 1021 /* min dst support */ 1022 } else if (drm_rect_width(&dst) < 0x1 || drm_rect_height(&dst) < 0x1) { 1023 DPU_DEBUG_PLANE(pdpu, "invalid dest rect " DRM_RECT_FMT "\n", 1024 DRM_RECT_ARG(&dst)); 1025 return -EINVAL; 1026 1027 /* check decimated source width */ 1028 } else if (drm_rect_width(&src) > max_linewidth) { 1029 DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n", 1030 DRM_RECT_ARG(&src), max_linewidth); 1031 return -E2BIG; 1032 } 1033 1034 pstate->needs_qos_remap = drm_atomic_crtc_needs_modeset(crtc_state); 1035 1036 return 0; 1037 } 1038 1039 void dpu_plane_flush(struct drm_plane *plane) 1040 { 1041 struct dpu_plane *pdpu; 1042 struct dpu_plane_state *pstate; 1043 1044 if (!plane || !plane->state) { 1045 DPU_ERROR("invalid plane\n"); 1046 return; 1047 } 1048 1049 pdpu = to_dpu_plane(plane); 1050 pstate = to_dpu_plane_state(plane->state); 1051 1052 /* 1053 * These updates have to be done immediately before the plane flush 1054 * timing, and may not be moved to the atomic_update/mode_set functions. 1055 */ 1056 if (pdpu->is_error) 1057 /* force white frame with 100% alpha pipe output on error */ 1058 _dpu_plane_color_fill(pdpu, 0xFFFFFF, 0xFF); 1059 else if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) 1060 /* force 100% alpha */ 1061 _dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF); 1062 else if (pdpu->pipe_hw && pdpu->csc_ptr && pdpu->pipe_hw->ops.setup_csc) 1063 pdpu->pipe_hw->ops.setup_csc(pdpu->pipe_hw, pdpu->csc_ptr); 1064 1065 /* flag h/w flush complete */ 1066 if (plane->state) 1067 pstate->pending = false; 1068 } 1069 1070 /** 1071 * dpu_plane_set_error: enable/disable error condition 1072 * @plane: pointer to drm_plane structure 1073 * @error: error value to set 1074 */ 1075 void dpu_plane_set_error(struct drm_plane *plane, bool error) 1076 { 1077 struct dpu_plane *pdpu; 1078 1079 if (!plane) 1080 return; 1081 1082 pdpu = to_dpu_plane(plane); 1083 pdpu->is_error = error; 1084 } 1085 1086 static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) 1087 { 1088 uint32_t src_flags; 1089 struct dpu_plane *pdpu = to_dpu_plane(plane); 1090 struct drm_plane_state *state = plane->state; 1091 struct dpu_plane_state *pstate = to_dpu_plane_state(state); 1092 struct drm_crtc *crtc = state->crtc; 1093 struct drm_framebuffer *fb = state->fb; 1094 bool is_rt_pipe, update_qos_remap; 1095 const struct dpu_format *fmt = 1096 to_dpu_format(msm_framebuffer_format(fb)); 1097 1098 memset(&(pdpu->pipe_cfg), 0, sizeof(struct dpu_hw_pipe_cfg)); 1099 1100 _dpu_plane_set_scanout(plane, pstate, &pdpu->pipe_cfg, fb); 1101 1102 pstate->pending = true; 1103 1104 is_rt_pipe = (dpu_crtc_get_client_type(crtc) != NRT_CLIENT); 1105 _dpu_plane_set_qos_ctrl(plane, false, DPU_PLANE_QOS_PANIC_CTRL); 1106 1107 DPU_DEBUG_PLANE(pdpu, "FB[%u] " DRM_RECT_FP_FMT "->crtc%u " DRM_RECT_FMT 1108 ", %4.4s ubwc %d\n", fb->base.id, DRM_RECT_FP_ARG(&state->src), 1109 crtc->base.id, DRM_RECT_ARG(&state->dst), 1110 (char *)&fmt->base.pixel_format, DPU_FORMAT_IS_UBWC(fmt)); 1111 1112 pdpu->pipe_cfg.src_rect = state->src; 1113 1114 /* state->src is 16.16, src_rect is not */ 1115 pdpu->pipe_cfg.src_rect.x1 >>= 16; 1116 pdpu->pipe_cfg.src_rect.x2 >>= 16; 1117 pdpu->pipe_cfg.src_rect.y1 >>= 16; 1118 pdpu->pipe_cfg.src_rect.y2 >>= 16; 1119 1120 pdpu->pipe_cfg.dst_rect = state->dst; 1121 1122 _dpu_plane_setup_scaler(pdpu, pstate, fmt, false); 1123 1124 /* override for color fill */ 1125 if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) { 1126 /* skip remaining processing on color fill */ 1127 return; 1128 } 1129 1130 if (pdpu->pipe_hw->ops.setup_rects) { 1131 pdpu->pipe_hw->ops.setup_rects(pdpu->pipe_hw, 1132 &pdpu->pipe_cfg, 1133 pstate->multirect_index); 1134 } 1135 1136 if (pdpu->pipe_hw->ops.setup_pe && 1137 (pstate->multirect_index != DPU_SSPP_RECT_1)) 1138 pdpu->pipe_hw->ops.setup_pe(pdpu->pipe_hw, 1139 &pstate->pixel_ext); 1140 1141 /** 1142 * when programmed in multirect mode, scalar block will be 1143 * bypassed. Still we need to update alpha and bitwidth 1144 * ONLY for RECT0 1145 */ 1146 if (pdpu->pipe_hw->ops.setup_scaler && 1147 pstate->multirect_index != DPU_SSPP_RECT_1) 1148 pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw, 1149 &pdpu->pipe_cfg, &pstate->pixel_ext, 1150 &pstate->scaler3_cfg); 1151 1152 if (pdpu->pipe_hw->ops.setup_multirect) 1153 pdpu->pipe_hw->ops.setup_multirect( 1154 pdpu->pipe_hw, 1155 pstate->multirect_index, 1156 pstate->multirect_mode); 1157 1158 if (pdpu->pipe_hw->ops.setup_format) { 1159 unsigned int rotation; 1160 1161 src_flags = 0x0; 1162 1163 rotation = drm_rotation_simplify(state->rotation, 1164 DRM_MODE_ROTATE_0 | 1165 DRM_MODE_REFLECT_X | 1166 DRM_MODE_REFLECT_Y); 1167 1168 if (rotation & DRM_MODE_REFLECT_X) 1169 src_flags |= DPU_SSPP_FLIP_LR; 1170 1171 if (rotation & DRM_MODE_REFLECT_Y) 1172 src_flags |= DPU_SSPP_FLIP_UD; 1173 1174 /* update format */ 1175 pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw, fmt, src_flags, 1176 pstate->multirect_index); 1177 1178 if (pdpu->pipe_hw->ops.setup_cdp) { 1179 struct dpu_hw_pipe_cdp_cfg *cdp_cfg = &pstate->cdp_cfg; 1180 1181 memset(cdp_cfg, 0, sizeof(struct dpu_hw_pipe_cdp_cfg)); 1182 1183 cdp_cfg->enable = pdpu->catalog->perf.cdp_cfg 1184 [DPU_PERF_CDP_USAGE_RT].rd_enable; 1185 cdp_cfg->ubwc_meta_enable = 1186 DPU_FORMAT_IS_UBWC(fmt); 1187 cdp_cfg->tile_amortize_enable = 1188 DPU_FORMAT_IS_UBWC(fmt) || 1189 DPU_FORMAT_IS_TILE(fmt); 1190 cdp_cfg->preload_ahead = DPU_SSPP_CDP_PRELOAD_AHEAD_64; 1191 1192 pdpu->pipe_hw->ops.setup_cdp(pdpu->pipe_hw, cdp_cfg); 1193 } 1194 1195 /* update csc */ 1196 if (DPU_FORMAT_IS_YUV(fmt)) 1197 _dpu_plane_setup_csc(pdpu); 1198 else 1199 pdpu->csc_ptr = 0; 1200 } 1201 1202 _dpu_plane_set_qos_lut(plane, fb); 1203 _dpu_plane_set_danger_lut(plane, fb); 1204 1205 if (plane->type != DRM_PLANE_TYPE_CURSOR) { 1206 _dpu_plane_set_qos_ctrl(plane, true, DPU_PLANE_QOS_PANIC_CTRL); 1207 _dpu_plane_set_ot_limit(plane, crtc); 1208 } 1209 1210 update_qos_remap = (is_rt_pipe != pdpu->is_rt_pipe) || 1211 pstate->needs_qos_remap; 1212 1213 if (update_qos_remap) { 1214 if (is_rt_pipe != pdpu->is_rt_pipe) 1215 pdpu->is_rt_pipe = is_rt_pipe; 1216 else if (pstate->needs_qos_remap) 1217 pstate->needs_qos_remap = false; 1218 _dpu_plane_set_qos_remap(plane); 1219 } 1220 1221 _dpu_plane_calc_bw(plane, fb); 1222 1223 _dpu_plane_calc_clk(plane); 1224 } 1225 1226 static void _dpu_plane_atomic_disable(struct drm_plane *plane) 1227 { 1228 struct dpu_plane *pdpu = to_dpu_plane(plane); 1229 struct drm_plane_state *state = plane->state; 1230 struct dpu_plane_state *pstate = to_dpu_plane_state(state); 1231 1232 trace_dpu_plane_disable(DRMID(plane), is_dpu_plane_virtual(plane), 1233 pstate->multirect_mode); 1234 1235 pstate->pending = true; 1236 1237 if (is_dpu_plane_virtual(plane) && 1238 pdpu->pipe_hw && pdpu->pipe_hw->ops.setup_multirect) 1239 pdpu->pipe_hw->ops.setup_multirect(pdpu->pipe_hw, 1240 DPU_SSPP_RECT_SOLO, DPU_SSPP_MULTIRECT_NONE); 1241 } 1242 1243 static void dpu_plane_atomic_update(struct drm_plane *plane, 1244 struct drm_atomic_state *state) 1245 { 1246 struct dpu_plane *pdpu = to_dpu_plane(plane); 1247 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, 1248 plane); 1249 1250 pdpu->is_error = false; 1251 1252 DPU_DEBUG_PLANE(pdpu, "\n"); 1253 1254 if (!new_state->visible) { 1255 _dpu_plane_atomic_disable(plane); 1256 } else { 1257 dpu_plane_sspp_atomic_update(plane); 1258 } 1259 } 1260 1261 static void dpu_plane_destroy(struct drm_plane *plane) 1262 { 1263 struct dpu_plane *pdpu = plane ? to_dpu_plane(plane) : NULL; 1264 1265 DPU_DEBUG_PLANE(pdpu, "\n"); 1266 1267 if (pdpu) { 1268 _dpu_plane_set_qos_ctrl(plane, false, DPU_PLANE_QOS_PANIC_CTRL); 1269 1270 mutex_destroy(&pdpu->lock); 1271 1272 /* this will destroy the states as well */ 1273 drm_plane_cleanup(plane); 1274 1275 dpu_hw_sspp_destroy(pdpu->pipe_hw); 1276 1277 kfree(pdpu); 1278 } 1279 } 1280 1281 static void dpu_plane_destroy_state(struct drm_plane *plane, 1282 struct drm_plane_state *state) 1283 { 1284 __drm_atomic_helper_plane_destroy_state(state); 1285 kfree(to_dpu_plane_state(state)); 1286 } 1287 1288 static struct drm_plane_state * 1289 dpu_plane_duplicate_state(struct drm_plane *plane) 1290 { 1291 struct dpu_plane *pdpu; 1292 struct dpu_plane_state *pstate; 1293 struct dpu_plane_state *old_state; 1294 1295 if (!plane) { 1296 DPU_ERROR("invalid plane\n"); 1297 return NULL; 1298 } else if (!plane->state) { 1299 DPU_ERROR("invalid plane state\n"); 1300 return NULL; 1301 } 1302 1303 old_state = to_dpu_plane_state(plane->state); 1304 pdpu = to_dpu_plane(plane); 1305 pstate = kmemdup(old_state, sizeof(*old_state), GFP_KERNEL); 1306 if (!pstate) { 1307 DPU_ERROR_PLANE(pdpu, "failed to allocate state\n"); 1308 return NULL; 1309 } 1310 1311 DPU_DEBUG_PLANE(pdpu, "\n"); 1312 1313 pstate->pending = false; 1314 1315 __drm_atomic_helper_plane_duplicate_state(plane, &pstate->base); 1316 1317 return &pstate->base; 1318 } 1319 1320 static void dpu_plane_reset(struct drm_plane *plane) 1321 { 1322 struct dpu_plane *pdpu; 1323 struct dpu_plane_state *pstate; 1324 1325 if (!plane) { 1326 DPU_ERROR("invalid plane\n"); 1327 return; 1328 } 1329 1330 pdpu = to_dpu_plane(plane); 1331 DPU_DEBUG_PLANE(pdpu, "\n"); 1332 1333 /* remove previous state, if present */ 1334 if (plane->state) { 1335 dpu_plane_destroy_state(plane, plane->state); 1336 plane->state = 0; 1337 } 1338 1339 pstate = kzalloc(sizeof(*pstate), GFP_KERNEL); 1340 if (!pstate) { 1341 DPU_ERROR_PLANE(pdpu, "failed to allocate state\n"); 1342 return; 1343 } 1344 1345 pstate->base.plane = plane; 1346 1347 plane->state = &pstate->base; 1348 } 1349 1350 #ifdef CONFIG_DEBUG_FS 1351 static void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable) 1352 { 1353 struct dpu_plane *pdpu = to_dpu_plane(plane); 1354 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 1355 1356 if (!pdpu->is_rt_pipe) 1357 return; 1358 1359 pm_runtime_get_sync(&dpu_kms->pdev->dev); 1360 _dpu_plane_set_qos_ctrl(plane, enable, DPU_PLANE_QOS_PANIC_CTRL); 1361 pm_runtime_put_sync(&dpu_kms->pdev->dev); 1362 } 1363 1364 static ssize_t _dpu_plane_danger_read(struct file *file, 1365 char __user *buff, size_t count, loff_t *ppos) 1366 { 1367 struct dpu_kms *kms = file->private_data; 1368 int len; 1369 char buf[40]; 1370 1371 len = scnprintf(buf, sizeof(buf), "%d\n", !kms->has_danger_ctrl); 1372 1373 return simple_read_from_buffer(buff, count, ppos, buf, len); 1374 } 1375 1376 static void _dpu_plane_set_danger_state(struct dpu_kms *kms, bool enable) 1377 { 1378 struct drm_plane *plane; 1379 1380 drm_for_each_plane(plane, kms->dev) { 1381 if (plane->fb && plane->state) { 1382 dpu_plane_danger_signal_ctrl(plane, enable); 1383 DPU_DEBUG("plane:%d img:%dx%d ", 1384 plane->base.id, plane->fb->width, 1385 plane->fb->height); 1386 DPU_DEBUG("src[%d,%d,%d,%d] dst[%d,%d,%d,%d]\n", 1387 plane->state->src_x >> 16, 1388 plane->state->src_y >> 16, 1389 plane->state->src_w >> 16, 1390 plane->state->src_h >> 16, 1391 plane->state->crtc_x, plane->state->crtc_y, 1392 plane->state->crtc_w, plane->state->crtc_h); 1393 } else { 1394 DPU_DEBUG("Inactive plane:%d\n", plane->base.id); 1395 } 1396 } 1397 } 1398 1399 static ssize_t _dpu_plane_danger_write(struct file *file, 1400 const char __user *user_buf, size_t count, loff_t *ppos) 1401 { 1402 struct dpu_kms *kms = file->private_data; 1403 int disable_panic; 1404 int ret; 1405 1406 ret = kstrtouint_from_user(user_buf, count, 0, &disable_panic); 1407 if (ret) 1408 return ret; 1409 1410 if (disable_panic) { 1411 /* Disable panic signal for all active pipes */ 1412 DPU_DEBUG("Disabling danger:\n"); 1413 _dpu_plane_set_danger_state(kms, false); 1414 kms->has_danger_ctrl = false; 1415 } else { 1416 /* Enable panic signal for all active pipes */ 1417 DPU_DEBUG("Enabling danger:\n"); 1418 kms->has_danger_ctrl = true; 1419 _dpu_plane_set_danger_state(kms, true); 1420 } 1421 1422 return count; 1423 } 1424 1425 static const struct file_operations dpu_plane_danger_enable = { 1426 .open = simple_open, 1427 .read = _dpu_plane_danger_read, 1428 .write = _dpu_plane_danger_write, 1429 }; 1430 1431 static int _dpu_plane_init_debugfs(struct drm_plane *plane) 1432 { 1433 struct dpu_plane *pdpu = to_dpu_plane(plane); 1434 struct dpu_kms *kms = _dpu_plane_get_kms(plane); 1435 const struct dpu_sspp_cfg *cfg = pdpu->pipe_hw->cap; 1436 const struct dpu_sspp_sub_blks *sblk = cfg->sblk; 1437 1438 /* create overall sub-directory for the pipe */ 1439 pdpu->debugfs_root = 1440 debugfs_create_dir(pdpu->pipe_name, 1441 plane->dev->primary->debugfs_root); 1442 1443 /* don't error check these */ 1444 debugfs_create_x32("features", 0600, 1445 pdpu->debugfs_root, &pdpu->features); 1446 1447 /* add register dump support */ 1448 dpu_debugfs_setup_regset32(&pdpu->debugfs_src, 1449 sblk->src_blk.base + cfg->base, 1450 sblk->src_blk.len, 1451 kms); 1452 dpu_debugfs_create_regset32("src_blk", 0400, 1453 pdpu->debugfs_root, &pdpu->debugfs_src); 1454 1455 if (cfg->features & BIT(DPU_SSPP_SCALER_QSEED3) || 1456 cfg->features & BIT(DPU_SSPP_SCALER_QSEED3LITE) || 1457 cfg->features & BIT(DPU_SSPP_SCALER_QSEED2) || 1458 cfg->features & BIT(DPU_SSPP_SCALER_QSEED4)) { 1459 dpu_debugfs_setup_regset32(&pdpu->debugfs_scaler, 1460 sblk->scaler_blk.base + cfg->base, 1461 sblk->scaler_blk.len, 1462 kms); 1463 dpu_debugfs_create_regset32("scaler_blk", 0400, 1464 pdpu->debugfs_root, 1465 &pdpu->debugfs_scaler); 1466 debugfs_create_bool("default_scaling", 1467 0600, 1468 pdpu->debugfs_root, 1469 &pdpu->debugfs_default_scale); 1470 } 1471 1472 if (cfg->features & BIT(DPU_SSPP_CSC) || 1473 cfg->features & BIT(DPU_SSPP_CSC_10BIT)) { 1474 dpu_debugfs_setup_regset32(&pdpu->debugfs_csc, 1475 sblk->csc_blk.base + cfg->base, 1476 sblk->csc_blk.len, 1477 kms); 1478 dpu_debugfs_create_regset32("csc_blk", 0400, 1479 pdpu->debugfs_root, &pdpu->debugfs_csc); 1480 } 1481 1482 debugfs_create_u32("xin_id", 1483 0400, 1484 pdpu->debugfs_root, 1485 (u32 *) &cfg->xin_id); 1486 debugfs_create_u32("clk_ctrl", 1487 0400, 1488 pdpu->debugfs_root, 1489 (u32 *) &cfg->clk_ctrl); 1490 debugfs_create_x32("creq_vblank", 1491 0600, 1492 pdpu->debugfs_root, 1493 (u32 *) &sblk->creq_vblank); 1494 debugfs_create_x32("danger_vblank", 1495 0600, 1496 pdpu->debugfs_root, 1497 (u32 *) &sblk->danger_vblank); 1498 1499 debugfs_create_file("disable_danger", 1500 0600, 1501 pdpu->debugfs_root, 1502 kms, &dpu_plane_danger_enable); 1503 1504 return 0; 1505 } 1506 #else 1507 static int _dpu_plane_init_debugfs(struct drm_plane *plane) 1508 { 1509 return 0; 1510 } 1511 #endif 1512 1513 static int dpu_plane_late_register(struct drm_plane *plane) 1514 { 1515 return _dpu_plane_init_debugfs(plane); 1516 } 1517 1518 static void dpu_plane_early_unregister(struct drm_plane *plane) 1519 { 1520 struct dpu_plane *pdpu = to_dpu_plane(plane); 1521 1522 debugfs_remove_recursive(pdpu->debugfs_root); 1523 } 1524 1525 static bool dpu_plane_format_mod_supported(struct drm_plane *plane, 1526 uint32_t format, uint64_t modifier) 1527 { 1528 if (modifier == DRM_FORMAT_MOD_LINEAR) 1529 return true; 1530 1531 if (modifier == DRM_FORMAT_MOD_QCOM_COMPRESSED) { 1532 int i; 1533 for (i = 0; i < ARRAY_SIZE(qcom_compressed_supported_formats); i++) { 1534 if (format == qcom_compressed_supported_formats[i]) 1535 return true; 1536 } 1537 } 1538 1539 return false; 1540 } 1541 1542 static const struct drm_plane_funcs dpu_plane_funcs = { 1543 .update_plane = drm_atomic_helper_update_plane, 1544 .disable_plane = drm_atomic_helper_disable_plane, 1545 .destroy = dpu_plane_destroy, 1546 .reset = dpu_plane_reset, 1547 .atomic_duplicate_state = dpu_plane_duplicate_state, 1548 .atomic_destroy_state = dpu_plane_destroy_state, 1549 .late_register = dpu_plane_late_register, 1550 .early_unregister = dpu_plane_early_unregister, 1551 .format_mod_supported = dpu_plane_format_mod_supported, 1552 }; 1553 1554 static const struct drm_plane_helper_funcs dpu_plane_helper_funcs = { 1555 .prepare_fb = dpu_plane_prepare_fb, 1556 .cleanup_fb = dpu_plane_cleanup_fb, 1557 .atomic_check = dpu_plane_atomic_check, 1558 .atomic_update = dpu_plane_atomic_update, 1559 }; 1560 1561 enum dpu_sspp dpu_plane_pipe(struct drm_plane *plane) 1562 { 1563 return plane ? to_dpu_plane(plane)->pipe : SSPP_NONE; 1564 } 1565 1566 bool is_dpu_plane_virtual(struct drm_plane *plane) 1567 { 1568 return plane ? to_dpu_plane(plane)->is_virtual : false; 1569 } 1570 1571 /* initialize plane */ 1572 struct drm_plane *dpu_plane_init(struct drm_device *dev, 1573 uint32_t pipe, enum drm_plane_type type, 1574 unsigned long possible_crtcs, u32 master_plane_id) 1575 { 1576 struct drm_plane *plane = NULL, *master_plane = NULL; 1577 const uint32_t *format_list; 1578 struct dpu_plane *pdpu; 1579 struct msm_drm_private *priv = dev->dev_private; 1580 struct dpu_kms *kms = to_dpu_kms(priv->kms); 1581 int zpos_max = DPU_ZPOS_MAX; 1582 uint32_t num_formats; 1583 int ret = -EINVAL; 1584 1585 /* create and zero local structure */ 1586 pdpu = kzalloc(sizeof(*pdpu), GFP_KERNEL); 1587 if (!pdpu) { 1588 DPU_ERROR("[%u]failed to allocate local plane struct\n", pipe); 1589 ret = -ENOMEM; 1590 return ERR_PTR(ret); 1591 } 1592 1593 /* cache local stuff for later */ 1594 plane = &pdpu->base; 1595 pdpu->pipe = pipe; 1596 pdpu->is_virtual = (master_plane_id != 0); 1597 INIT_LIST_HEAD(&pdpu->mplane_list); 1598 master_plane = drm_plane_find(dev, NULL, master_plane_id); 1599 if (master_plane) { 1600 struct dpu_plane *mpdpu = to_dpu_plane(master_plane); 1601 1602 list_add_tail(&pdpu->mplane_list, &mpdpu->mplane_list); 1603 } 1604 1605 /* initialize underlying h/w driver */ 1606 pdpu->pipe_hw = dpu_hw_sspp_init(pipe, kms->mmio, kms->catalog, 1607 master_plane_id != 0); 1608 if (IS_ERR(pdpu->pipe_hw)) { 1609 DPU_ERROR("[%u]SSPP init failed\n", pipe); 1610 ret = PTR_ERR(pdpu->pipe_hw); 1611 goto clean_plane; 1612 } else if (!pdpu->pipe_hw->cap || !pdpu->pipe_hw->cap->sblk) { 1613 DPU_ERROR("[%u]SSPP init returned invalid cfg\n", pipe); 1614 goto clean_sspp; 1615 } 1616 1617 /* cache features mask for later */ 1618 pdpu->features = pdpu->pipe_hw->cap->features; 1619 pdpu->pipe_sblk = pdpu->pipe_hw->cap->sblk; 1620 if (!pdpu->pipe_sblk) { 1621 DPU_ERROR("[%u]invalid sblk\n", pipe); 1622 goto clean_sspp; 1623 } 1624 1625 if (pdpu->is_virtual) { 1626 format_list = pdpu->pipe_sblk->virt_format_list; 1627 num_formats = pdpu->pipe_sblk->virt_num_formats; 1628 } 1629 else { 1630 format_list = pdpu->pipe_sblk->format_list; 1631 num_formats = pdpu->pipe_sblk->num_formats; 1632 } 1633 1634 ret = drm_universal_plane_init(dev, plane, 0xff, &dpu_plane_funcs, 1635 format_list, num_formats, 1636 supported_format_modifiers, type, NULL); 1637 if (ret) 1638 goto clean_sspp; 1639 1640 pdpu->catalog = kms->catalog; 1641 1642 if (kms->catalog->mixer_count && 1643 kms->catalog->mixer[0].sblk->maxblendstages) { 1644 zpos_max = kms->catalog->mixer[0].sblk->maxblendstages - 1; 1645 if (zpos_max > DPU_STAGE_MAX - DPU_STAGE_0 - 1) 1646 zpos_max = DPU_STAGE_MAX - DPU_STAGE_0 - 1; 1647 } 1648 1649 ret = drm_plane_create_zpos_property(plane, 0, 0, zpos_max); 1650 if (ret) 1651 DPU_ERROR("failed to install zpos property, rc = %d\n", ret); 1652 1653 drm_plane_create_rotation_property(plane, 1654 DRM_MODE_ROTATE_0, 1655 DRM_MODE_ROTATE_0 | 1656 DRM_MODE_ROTATE_180 | 1657 DRM_MODE_REFLECT_X | 1658 DRM_MODE_REFLECT_Y); 1659 1660 drm_plane_enable_fb_damage_clips(plane); 1661 1662 /* success! finalize initialization */ 1663 drm_plane_helper_add(plane, &dpu_plane_helper_funcs); 1664 1665 /* save user friendly pipe name for later */ 1666 snprintf(pdpu->pipe_name, DPU_NAME_SIZE, "plane%u", plane->base.id); 1667 1668 mutex_init(&pdpu->lock); 1669 1670 DPU_DEBUG("%s created for pipe:%u id:%u virtual:%u\n", pdpu->pipe_name, 1671 pipe, plane->base.id, master_plane_id); 1672 return plane; 1673 1674 clean_sspp: 1675 if (pdpu && pdpu->pipe_hw) 1676 dpu_hw_sspp_destroy(pdpu->pipe_hw); 1677 clean_plane: 1678 kfree(pdpu); 1679 return ERR_PTR(ret); 1680 } 1681