xref: /openbmc/linux/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c (revision f5ad1c74)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
4  * Copyright (C) 2013 Red Hat
5  * Author: Rob Clark <robdclark@gmail.com>
6  */
7 
8 #define pr_fmt(fmt)	"[drm:%s:%d] " fmt, __func__, __LINE__
9 
10 #include <linux/debugfs.h>
11 #include <linux/dma-buf.h>
12 #include <linux/of_irq.h>
13 #include <linux/pm_opp.h>
14 
15 #include <drm/drm_crtc.h>
16 #include <drm/drm_file.h>
17 
18 #include "msm_drv.h"
19 #include "msm_mmu.h"
20 #include "msm_gem.h"
21 
22 #include "dpu_kms.h"
23 #include "dpu_core_irq.h"
24 #include "dpu_formats.h"
25 #include "dpu_hw_vbif.h"
26 #include "dpu_vbif.h"
27 #include "dpu_encoder.h"
28 #include "dpu_plane.h"
29 #include "dpu_crtc.h"
30 
31 #define CREATE_TRACE_POINTS
32 #include "dpu_trace.h"
33 
34 /*
35  * To enable overall DRM driver logging
36  * # echo 0x2 > /sys/module/drm/parameters/debug
37  *
38  * To enable DRM driver h/w logging
39  * # echo <mask> > /sys/kernel/debug/dri/0/debug/hw_log_mask
40  *
41  * See dpu_hw_mdss.h for h/w logging mask definitions (search for DPU_DBG_MASK_)
42  */
43 #define DPU_DEBUGFS_DIR "msm_dpu"
44 #define DPU_DEBUGFS_HWMASKNAME "hw_log_mask"
45 
46 static int dpu_kms_hw_init(struct msm_kms *kms);
47 static void _dpu_kms_mmu_destroy(struct dpu_kms *dpu_kms);
48 
49 #ifdef CONFIG_DEBUG_FS
50 static int _dpu_danger_signal_status(struct seq_file *s,
51 		bool danger_status)
52 {
53 	struct dpu_kms *kms = (struct dpu_kms *)s->private;
54 	struct dpu_danger_safe_status status;
55 	int i;
56 
57 	if (!kms->hw_mdp) {
58 		DPU_ERROR("invalid arg(s)\n");
59 		return 0;
60 	}
61 
62 	memset(&status, 0, sizeof(struct dpu_danger_safe_status));
63 
64 	pm_runtime_get_sync(&kms->pdev->dev);
65 	if (danger_status) {
66 		seq_puts(s, "\nDanger signal status:\n");
67 		if (kms->hw_mdp->ops.get_danger_status)
68 			kms->hw_mdp->ops.get_danger_status(kms->hw_mdp,
69 					&status);
70 	} else {
71 		seq_puts(s, "\nSafe signal status:\n");
72 		if (kms->hw_mdp->ops.get_danger_status)
73 			kms->hw_mdp->ops.get_danger_status(kms->hw_mdp,
74 					&status);
75 	}
76 	pm_runtime_put_sync(&kms->pdev->dev);
77 
78 	seq_printf(s, "MDP     :  0x%x\n", status.mdp);
79 
80 	for (i = SSPP_VIG0; i < SSPP_MAX; i++)
81 		seq_printf(s, "SSPP%d   :  0x%x  \t", i - SSPP_VIG0,
82 				status.sspp[i]);
83 	seq_puts(s, "\n");
84 
85 	return 0;
86 }
87 
88 static int dpu_debugfs_danger_stats_show(struct seq_file *s, void *v)
89 {
90 	return _dpu_danger_signal_status(s, true);
91 }
92 DEFINE_SHOW_ATTRIBUTE(dpu_debugfs_danger_stats);
93 
94 static int dpu_debugfs_safe_stats_show(struct seq_file *s, void *v)
95 {
96 	return _dpu_danger_signal_status(s, false);
97 }
98 DEFINE_SHOW_ATTRIBUTE(dpu_debugfs_safe_stats);
99 
100 static void dpu_debugfs_danger_init(struct dpu_kms *dpu_kms,
101 		struct dentry *parent)
102 {
103 	struct dentry *entry = debugfs_create_dir("danger", parent);
104 
105 	debugfs_create_file("danger_status", 0600, entry,
106 			dpu_kms, &dpu_debugfs_danger_stats_fops);
107 	debugfs_create_file("safe_status", 0600, entry,
108 			dpu_kms, &dpu_debugfs_safe_stats_fops);
109 }
110 
111 static int _dpu_debugfs_show_regset32(struct seq_file *s, void *data)
112 {
113 	struct dpu_debugfs_regset32 *regset = s->private;
114 	struct dpu_kms *dpu_kms = regset->dpu_kms;
115 	void __iomem *base;
116 	uint32_t i, addr;
117 
118 	if (!dpu_kms->mmio)
119 		return 0;
120 
121 	base = dpu_kms->mmio + regset->offset;
122 
123 	/* insert padding spaces, if needed */
124 	if (regset->offset & 0xF) {
125 		seq_printf(s, "[%x]", regset->offset & ~0xF);
126 		for (i = 0; i < (regset->offset & 0xF); i += 4)
127 			seq_puts(s, "         ");
128 	}
129 
130 	pm_runtime_get_sync(&dpu_kms->pdev->dev);
131 
132 	/* main register output */
133 	for (i = 0; i < regset->blk_len; i += 4) {
134 		addr = regset->offset + i;
135 		if ((addr & 0xF) == 0x0)
136 			seq_printf(s, i ? "\n[%x]" : "[%x]", addr);
137 		seq_printf(s, " %08x", readl_relaxed(base + i));
138 	}
139 	seq_puts(s, "\n");
140 	pm_runtime_put_sync(&dpu_kms->pdev->dev);
141 
142 	return 0;
143 }
144 
145 static int dpu_debugfs_open_regset32(struct inode *inode,
146 		struct file *file)
147 {
148 	return single_open(file, _dpu_debugfs_show_regset32, inode->i_private);
149 }
150 
151 static const struct file_operations dpu_fops_regset32 = {
152 	.open =		dpu_debugfs_open_regset32,
153 	.read =		seq_read,
154 	.llseek =	seq_lseek,
155 	.release =	single_release,
156 };
157 
158 void dpu_debugfs_setup_regset32(struct dpu_debugfs_regset32 *regset,
159 		uint32_t offset, uint32_t length, struct dpu_kms *dpu_kms)
160 {
161 	if (regset) {
162 		regset->offset = offset;
163 		regset->blk_len = length;
164 		regset->dpu_kms = dpu_kms;
165 	}
166 }
167 
168 void dpu_debugfs_create_regset32(const char *name, umode_t mode,
169 		void *parent, struct dpu_debugfs_regset32 *regset)
170 {
171 	if (!name || !regset || !regset->dpu_kms || !regset->blk_len)
172 		return;
173 
174 	/* make sure offset is a multiple of 4 */
175 	regset->offset = round_down(regset->offset, 4);
176 
177 	debugfs_create_file(name, mode, parent, regset, &dpu_fops_regset32);
178 }
179 
180 static int dpu_kms_debugfs_init(struct msm_kms *kms, struct drm_minor *minor)
181 {
182 	struct dpu_kms *dpu_kms = to_dpu_kms(kms);
183 	void *p = dpu_hw_util_get_log_mask_ptr();
184 	struct dentry *entry;
185 	struct drm_device *dev;
186 	struct msm_drm_private *priv;
187 
188 	if (!p)
189 		return -EINVAL;
190 
191 	dev = dpu_kms->dev;
192 	priv = dev->dev_private;
193 
194 	entry = debugfs_create_dir("debug", minor->debugfs_root);
195 
196 	debugfs_create_x32(DPU_DEBUGFS_HWMASKNAME, 0600, entry, p);
197 
198 	dpu_debugfs_danger_init(dpu_kms, entry);
199 	dpu_debugfs_vbif_init(dpu_kms, entry);
200 	dpu_debugfs_core_irq_init(dpu_kms, entry);
201 
202 	if (priv->dp)
203 		msm_dp_debugfs_init(priv->dp, minor);
204 
205 	return dpu_core_perf_debugfs_init(dpu_kms, entry);
206 }
207 #endif
208 
209 /* Global/shared object state funcs */
210 
211 /*
212  * This is a helper that returns the private state currently in operation.
213  * Note that this would return the "old_state" if called in the atomic check
214  * path, and the "new_state" after the atomic swap has been done.
215  */
216 struct dpu_global_state *
217 dpu_kms_get_existing_global_state(struct dpu_kms *dpu_kms)
218 {
219 	return to_dpu_global_state(dpu_kms->global_state.state);
220 }
221 
222 /*
223  * This acquires the modeset lock set aside for global state, creates
224  * a new duplicated private object state.
225  */
226 struct dpu_global_state *dpu_kms_get_global_state(struct drm_atomic_state *s)
227 {
228 	struct msm_drm_private *priv = s->dev->dev_private;
229 	struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
230 	struct drm_private_state *priv_state;
231 	int ret;
232 
233 	ret = drm_modeset_lock(&dpu_kms->global_state_lock, s->acquire_ctx);
234 	if (ret)
235 		return ERR_PTR(ret);
236 
237 	priv_state = drm_atomic_get_private_obj_state(s,
238 						&dpu_kms->global_state);
239 	if (IS_ERR(priv_state))
240 		return ERR_CAST(priv_state);
241 
242 	return to_dpu_global_state(priv_state);
243 }
244 
245 static struct drm_private_state *
246 dpu_kms_global_duplicate_state(struct drm_private_obj *obj)
247 {
248 	struct dpu_global_state *state;
249 
250 	state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL);
251 	if (!state)
252 		return NULL;
253 
254 	__drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);
255 
256 	return &state->base;
257 }
258 
259 static void dpu_kms_global_destroy_state(struct drm_private_obj *obj,
260 				      struct drm_private_state *state)
261 {
262 	struct dpu_global_state *dpu_state = to_dpu_global_state(state);
263 
264 	kfree(dpu_state);
265 }
266 
267 static const struct drm_private_state_funcs dpu_kms_global_state_funcs = {
268 	.atomic_duplicate_state = dpu_kms_global_duplicate_state,
269 	.atomic_destroy_state = dpu_kms_global_destroy_state,
270 };
271 
272 static int dpu_kms_global_obj_init(struct dpu_kms *dpu_kms)
273 {
274 	struct dpu_global_state *state;
275 
276 	drm_modeset_lock_init(&dpu_kms->global_state_lock);
277 
278 	state = kzalloc(sizeof(*state), GFP_KERNEL);
279 	if (!state)
280 		return -ENOMEM;
281 
282 	drm_atomic_private_obj_init(dpu_kms->dev, &dpu_kms->global_state,
283 				    &state->base,
284 				    &dpu_kms_global_state_funcs);
285 	return 0;
286 }
287 
288 static int dpu_kms_parse_data_bus_icc_path(struct dpu_kms *dpu_kms)
289 {
290 	struct icc_path *path0;
291 	struct icc_path *path1;
292 	struct drm_device *dev = dpu_kms->dev;
293 
294 	path0 = of_icc_get(dev->dev, "mdp0-mem");
295 	path1 = of_icc_get(dev->dev, "mdp1-mem");
296 
297 	if (IS_ERR_OR_NULL(path0))
298 		return PTR_ERR_OR_ZERO(path0);
299 
300 	dpu_kms->path[0] = path0;
301 	dpu_kms->num_paths = 1;
302 
303 	if (!IS_ERR_OR_NULL(path1)) {
304 		dpu_kms->path[1] = path1;
305 		dpu_kms->num_paths++;
306 	}
307 	return 0;
308 }
309 
310 static int dpu_kms_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
311 {
312 	return dpu_crtc_vblank(crtc, true);
313 }
314 
315 static void dpu_kms_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
316 {
317 	dpu_crtc_vblank(crtc, false);
318 }
319 
320 static void dpu_kms_enable_commit(struct msm_kms *kms)
321 {
322 	struct dpu_kms *dpu_kms = to_dpu_kms(kms);
323 	pm_runtime_get_sync(&dpu_kms->pdev->dev);
324 }
325 
326 static void dpu_kms_disable_commit(struct msm_kms *kms)
327 {
328 	struct dpu_kms *dpu_kms = to_dpu_kms(kms);
329 	pm_runtime_put_sync(&dpu_kms->pdev->dev);
330 }
331 
332 static ktime_t dpu_kms_vsync_time(struct msm_kms *kms, struct drm_crtc *crtc)
333 {
334 	struct drm_encoder *encoder;
335 
336 	drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) {
337 		ktime_t vsync_time;
338 
339 		if (dpu_encoder_vsync_time(encoder, &vsync_time) == 0)
340 			return vsync_time;
341 	}
342 
343 	return ktime_get();
344 }
345 
346 static void dpu_kms_prepare_commit(struct msm_kms *kms,
347 		struct drm_atomic_state *state)
348 {
349 	struct drm_crtc *crtc;
350 	struct drm_crtc_state *crtc_state;
351 	struct drm_encoder *encoder;
352 	int i;
353 
354 	if (!kms)
355 		return;
356 
357 	/* Call prepare_commit for all affected encoders */
358 	for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
359 		drm_for_each_encoder_mask(encoder, crtc->dev,
360 					  crtc_state->encoder_mask) {
361 			dpu_encoder_prepare_commit(encoder);
362 		}
363 	}
364 }
365 
366 static void dpu_kms_flush_commit(struct msm_kms *kms, unsigned crtc_mask)
367 {
368 	struct dpu_kms *dpu_kms = to_dpu_kms(kms);
369 	struct drm_crtc *crtc;
370 
371 	for_each_crtc_mask(dpu_kms->dev, crtc, crtc_mask) {
372 		if (!crtc->state->active)
373 			continue;
374 
375 		trace_dpu_kms_commit(DRMID(crtc));
376 		dpu_crtc_commit_kickoff(crtc);
377 	}
378 }
379 
380 /*
381  * Override the encoder enable since we need to setup the inline rotator and do
382  * some crtc magic before enabling any bridge that might be present.
383  */
384 void dpu_kms_encoder_enable(struct drm_encoder *encoder)
385 {
386 	const struct drm_encoder_helper_funcs *funcs = encoder->helper_private;
387 	struct drm_device *dev = encoder->dev;
388 	struct drm_crtc *crtc;
389 
390 	/* Forward this enable call to the commit hook */
391 	if (funcs && funcs->commit)
392 		funcs->commit(encoder);
393 
394 	drm_for_each_crtc(crtc, dev) {
395 		if (!(crtc->state->encoder_mask & drm_encoder_mask(encoder)))
396 			continue;
397 
398 		trace_dpu_kms_enc_enable(DRMID(crtc));
399 	}
400 }
401 
402 static void dpu_kms_complete_commit(struct msm_kms *kms, unsigned crtc_mask)
403 {
404 	struct dpu_kms *dpu_kms = to_dpu_kms(kms);
405 	struct drm_crtc *crtc;
406 
407 	DPU_ATRACE_BEGIN("kms_complete_commit");
408 
409 	for_each_crtc_mask(dpu_kms->dev, crtc, crtc_mask)
410 		dpu_crtc_complete_commit(crtc);
411 
412 	DPU_ATRACE_END("kms_complete_commit");
413 }
414 
415 static void dpu_kms_wait_for_commit_done(struct msm_kms *kms,
416 		struct drm_crtc *crtc)
417 {
418 	struct drm_encoder *encoder;
419 	struct drm_device *dev;
420 	int ret;
421 
422 	if (!kms || !crtc || !crtc->state) {
423 		DPU_ERROR("invalid params\n");
424 		return;
425 	}
426 
427 	dev = crtc->dev;
428 
429 	if (!crtc->state->enable) {
430 		DPU_DEBUG("[crtc:%d] not enable\n", crtc->base.id);
431 		return;
432 	}
433 
434 	if (!crtc->state->active) {
435 		DPU_DEBUG("[crtc:%d] not active\n", crtc->base.id);
436 		return;
437 	}
438 
439 	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
440 		if (encoder->crtc != crtc)
441 			continue;
442 		/*
443 		 * Wait for post-flush if necessary to delay before
444 		 * plane_cleanup. For example, wait for vsync in case of video
445 		 * mode panels. This may be a no-op for command mode panels.
446 		 */
447 		trace_dpu_kms_wait_for_commit_done(DRMID(crtc));
448 		ret = dpu_encoder_wait_for_event(encoder, MSM_ENC_COMMIT_DONE);
449 		if (ret && ret != -EWOULDBLOCK) {
450 			DPU_ERROR("wait for commit done returned %d\n", ret);
451 			break;
452 		}
453 	}
454 }
455 
456 static void dpu_kms_wait_flush(struct msm_kms *kms, unsigned crtc_mask)
457 {
458 	struct dpu_kms *dpu_kms = to_dpu_kms(kms);
459 	struct drm_crtc *crtc;
460 
461 	for_each_crtc_mask(dpu_kms->dev, crtc, crtc_mask)
462 		dpu_kms_wait_for_commit_done(kms, crtc);
463 }
464 
465 static int _dpu_kms_initialize_dsi(struct drm_device *dev,
466 				    struct msm_drm_private *priv,
467 				    struct dpu_kms *dpu_kms)
468 {
469 	struct drm_encoder *encoder = NULL;
470 	int i, rc = 0;
471 
472 	if (!(priv->dsi[0] || priv->dsi[1]))
473 		return rc;
474 
475 	/*TODO: Support two independent DSI connectors */
476 	encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_DSI);
477 	if (IS_ERR(encoder)) {
478 		DPU_ERROR("encoder init failed for dsi display\n");
479 		return PTR_ERR(encoder);
480 	}
481 
482 	priv->encoders[priv->num_encoders++] = encoder;
483 
484 	for (i = 0; i < ARRAY_SIZE(priv->dsi); i++) {
485 		if (!priv->dsi[i])
486 			continue;
487 
488 		rc = msm_dsi_modeset_init(priv->dsi[i], dev, encoder);
489 		if (rc) {
490 			DPU_ERROR("modeset_init failed for dsi[%d], rc = %d\n",
491 				i, rc);
492 			break;
493 		}
494 	}
495 
496 	return rc;
497 }
498 
499 static int _dpu_kms_initialize_displayport(struct drm_device *dev,
500 					    struct msm_drm_private *priv,
501 					    struct dpu_kms *dpu_kms)
502 {
503 	struct drm_encoder *encoder = NULL;
504 	int rc = 0;
505 
506 	if (!priv->dp)
507 		return rc;
508 
509 	encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_TMDS);
510 	if (IS_ERR(encoder)) {
511 		DPU_ERROR("encoder init failed for dsi display\n");
512 		return PTR_ERR(encoder);
513 	}
514 
515 	rc = msm_dp_modeset_init(priv->dp, dev, encoder);
516 	if (rc) {
517 		DPU_ERROR("modeset_init failed for DP, rc = %d\n", rc);
518 		drm_encoder_cleanup(encoder);
519 		return rc;
520 	}
521 
522 	priv->encoders[priv->num_encoders++] = encoder;
523 	return rc;
524 }
525 
526 /**
527  * _dpu_kms_setup_displays - create encoders, bridges and connectors
528  *                           for underlying displays
529  * @dev:        Pointer to drm device structure
530  * @priv:       Pointer to private drm device data
531  * @dpu_kms:    Pointer to dpu kms structure
532  * Returns:     Zero on success
533  */
534 static int _dpu_kms_setup_displays(struct drm_device *dev,
535 				    struct msm_drm_private *priv,
536 				    struct dpu_kms *dpu_kms)
537 {
538 	int rc = 0;
539 
540 	rc = _dpu_kms_initialize_dsi(dev, priv, dpu_kms);
541 	if (rc) {
542 		DPU_ERROR("initialize_dsi failed, rc = %d\n", rc);
543 		return rc;
544 	}
545 
546 	rc = _dpu_kms_initialize_displayport(dev, priv, dpu_kms);
547 	if (rc) {
548 		DPU_ERROR("initialize_DP failed, rc = %d\n", rc);
549 		return rc;
550 	}
551 
552 	return rc;
553 }
554 
555 static void _dpu_kms_drm_obj_destroy(struct dpu_kms *dpu_kms)
556 {
557 	struct msm_drm_private *priv;
558 	int i;
559 
560 	priv = dpu_kms->dev->dev_private;
561 
562 	for (i = 0; i < priv->num_crtcs; i++)
563 		priv->crtcs[i]->funcs->destroy(priv->crtcs[i]);
564 	priv->num_crtcs = 0;
565 
566 	for (i = 0; i < priv->num_planes; i++)
567 		priv->planes[i]->funcs->destroy(priv->planes[i]);
568 	priv->num_planes = 0;
569 
570 	for (i = 0; i < priv->num_connectors; i++)
571 		priv->connectors[i]->funcs->destroy(priv->connectors[i]);
572 	priv->num_connectors = 0;
573 
574 	for (i = 0; i < priv->num_encoders; i++)
575 		priv->encoders[i]->funcs->destroy(priv->encoders[i]);
576 	priv->num_encoders = 0;
577 }
578 
579 static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms)
580 {
581 	struct drm_device *dev;
582 	struct drm_plane *primary_planes[MAX_PLANES], *plane;
583 	struct drm_plane *cursor_planes[MAX_PLANES] = { NULL };
584 	struct drm_crtc *crtc;
585 
586 	struct msm_drm_private *priv;
587 	struct dpu_mdss_cfg *catalog;
588 
589 	int primary_planes_idx = 0, cursor_planes_idx = 0, i, ret;
590 	int max_crtc_count;
591 	dev = dpu_kms->dev;
592 	priv = dev->dev_private;
593 	catalog = dpu_kms->catalog;
594 
595 	/*
596 	 * Create encoder and query display drivers to create
597 	 * bridges and connectors
598 	 */
599 	ret = _dpu_kms_setup_displays(dev, priv, dpu_kms);
600 	if (ret)
601 		goto fail;
602 
603 	max_crtc_count = min(catalog->mixer_count, priv->num_encoders);
604 
605 	/* Create the planes, keeping track of one primary/cursor per crtc */
606 	for (i = 0; i < catalog->sspp_count; i++) {
607 		enum drm_plane_type type;
608 
609 		if ((catalog->sspp[i].features & BIT(DPU_SSPP_CURSOR))
610 			&& cursor_planes_idx < max_crtc_count)
611 			type = DRM_PLANE_TYPE_CURSOR;
612 		else if (primary_planes_idx < max_crtc_count)
613 			type = DRM_PLANE_TYPE_PRIMARY;
614 		else
615 			type = DRM_PLANE_TYPE_OVERLAY;
616 
617 		DPU_DEBUG("Create plane type %d with features %lx (cur %lx)\n",
618 			  type, catalog->sspp[i].features,
619 			  catalog->sspp[i].features & BIT(DPU_SSPP_CURSOR));
620 
621 		plane = dpu_plane_init(dev, catalog->sspp[i].id, type,
622 				       (1UL << max_crtc_count) - 1, 0);
623 		if (IS_ERR(plane)) {
624 			DPU_ERROR("dpu_plane_init failed\n");
625 			ret = PTR_ERR(plane);
626 			goto fail;
627 		}
628 		priv->planes[priv->num_planes++] = plane;
629 
630 		if (type == DRM_PLANE_TYPE_CURSOR)
631 			cursor_planes[cursor_planes_idx++] = plane;
632 		else if (type == DRM_PLANE_TYPE_PRIMARY)
633 			primary_planes[primary_planes_idx++] = plane;
634 	}
635 
636 	max_crtc_count = min(max_crtc_count, primary_planes_idx);
637 
638 	/* Create one CRTC per encoder */
639 	for (i = 0; i < max_crtc_count; i++) {
640 		crtc = dpu_crtc_init(dev, primary_planes[i], cursor_planes[i]);
641 		if (IS_ERR(crtc)) {
642 			ret = PTR_ERR(crtc);
643 			goto fail;
644 		}
645 		priv->crtcs[priv->num_crtcs++] = crtc;
646 	}
647 
648 	/* All CRTCs are compatible with all encoders */
649 	for (i = 0; i < priv->num_encoders; i++)
650 		priv->encoders[i]->possible_crtcs = (1 << priv->num_crtcs) - 1;
651 
652 	return 0;
653 fail:
654 	_dpu_kms_drm_obj_destroy(dpu_kms);
655 	return ret;
656 }
657 
658 static long dpu_kms_round_pixclk(struct msm_kms *kms, unsigned long rate,
659 		struct drm_encoder *encoder)
660 {
661 	return rate;
662 }
663 
664 static void _dpu_kms_hw_destroy(struct dpu_kms *dpu_kms)
665 {
666 	int i;
667 
668 	if (dpu_kms->hw_intr)
669 		dpu_hw_intr_destroy(dpu_kms->hw_intr);
670 	dpu_kms->hw_intr = NULL;
671 
672 	/* safe to call these more than once during shutdown */
673 	_dpu_kms_mmu_destroy(dpu_kms);
674 
675 	if (dpu_kms->catalog) {
676 		for (i = 0; i < dpu_kms->catalog->vbif_count; i++) {
677 			u32 vbif_idx = dpu_kms->catalog->vbif[i].id;
678 
679 			if ((vbif_idx < VBIF_MAX) && dpu_kms->hw_vbif[vbif_idx])
680 				dpu_hw_vbif_destroy(dpu_kms->hw_vbif[vbif_idx]);
681 		}
682 	}
683 
684 	if (dpu_kms->rm_init)
685 		dpu_rm_destroy(&dpu_kms->rm);
686 	dpu_kms->rm_init = false;
687 
688 	if (dpu_kms->catalog)
689 		dpu_hw_catalog_deinit(dpu_kms->catalog);
690 	dpu_kms->catalog = NULL;
691 
692 	if (dpu_kms->vbif[VBIF_NRT])
693 		devm_iounmap(&dpu_kms->pdev->dev, dpu_kms->vbif[VBIF_NRT]);
694 	dpu_kms->vbif[VBIF_NRT] = NULL;
695 
696 	if (dpu_kms->vbif[VBIF_RT])
697 		devm_iounmap(&dpu_kms->pdev->dev, dpu_kms->vbif[VBIF_RT]);
698 	dpu_kms->vbif[VBIF_RT] = NULL;
699 
700 	if (dpu_kms->hw_mdp)
701 		dpu_hw_mdp_destroy(dpu_kms->hw_mdp);
702 	dpu_kms->hw_mdp = NULL;
703 
704 	if (dpu_kms->mmio)
705 		devm_iounmap(&dpu_kms->pdev->dev, dpu_kms->mmio);
706 	dpu_kms->mmio = NULL;
707 }
708 
709 static void dpu_kms_destroy(struct msm_kms *kms)
710 {
711 	struct dpu_kms *dpu_kms;
712 
713 	if (!kms) {
714 		DPU_ERROR("invalid kms\n");
715 		return;
716 	}
717 
718 	dpu_kms = to_dpu_kms(kms);
719 
720 	_dpu_kms_hw_destroy(dpu_kms);
721 
722 	msm_kms_destroy(&dpu_kms->base);
723 }
724 
725 static void _dpu_kms_set_encoder_mode(struct msm_kms *kms,
726 				 struct drm_encoder *encoder,
727 				 bool cmd_mode)
728 {
729 	struct msm_display_info info;
730 	struct msm_drm_private *priv = encoder->dev->dev_private;
731 	int i, rc = 0;
732 
733 	memset(&info, 0, sizeof(info));
734 
735 	info.intf_type = encoder->encoder_type;
736 	info.capabilities = cmd_mode ? MSM_DISPLAY_CAP_CMD_MODE :
737 			MSM_DISPLAY_CAP_VID_MODE;
738 
739 	switch (info.intf_type) {
740 	case DRM_MODE_ENCODER_DSI:
741 		/* TODO: No support for DSI swap */
742 		for (i = 0; i < ARRAY_SIZE(priv->dsi); i++) {
743 			if (priv->dsi[i]) {
744 				info.h_tile_instance[info.num_of_h_tiles] = i;
745 				info.num_of_h_tiles++;
746 			}
747 		}
748 		break;
749 	case DRM_MODE_ENCODER_TMDS:
750 		info.num_of_h_tiles = 1;
751 		break;
752 	};
753 
754 	rc = dpu_encoder_setup(encoder->dev, encoder, &info);
755 	if (rc)
756 		DPU_ERROR("failed to setup DPU encoder %d: rc:%d\n",
757 			encoder->base.id, rc);
758 }
759 
760 static irqreturn_t dpu_irq(struct msm_kms *kms)
761 {
762 	struct dpu_kms *dpu_kms = to_dpu_kms(kms);
763 
764 	return dpu_core_irq(dpu_kms);
765 }
766 
767 static void dpu_irq_preinstall(struct msm_kms *kms)
768 {
769 	struct dpu_kms *dpu_kms = to_dpu_kms(kms);
770 
771 	dpu_core_irq_preinstall(dpu_kms);
772 }
773 
774 static int dpu_irq_postinstall(struct msm_kms *kms)
775 {
776 	struct msm_drm_private *priv;
777 	struct dpu_kms *dpu_kms = to_dpu_kms(kms);
778 
779 	if (!dpu_kms || !dpu_kms->dev)
780 		return -EINVAL;
781 
782 	priv = dpu_kms->dev->dev_private;
783 	if (!priv)
784 		return -EINVAL;
785 
786 	msm_dp_irq_postinstall(priv->dp);
787 
788 	return 0;
789 }
790 
791 static void dpu_irq_uninstall(struct msm_kms *kms)
792 {
793 	struct dpu_kms *dpu_kms = to_dpu_kms(kms);
794 
795 	dpu_core_irq_uninstall(dpu_kms);
796 }
797 
798 static const struct msm_kms_funcs kms_funcs = {
799 	.hw_init         = dpu_kms_hw_init,
800 	.irq_preinstall  = dpu_irq_preinstall,
801 	.irq_postinstall = dpu_irq_postinstall,
802 	.irq_uninstall   = dpu_irq_uninstall,
803 	.irq             = dpu_irq,
804 	.enable_commit   = dpu_kms_enable_commit,
805 	.disable_commit  = dpu_kms_disable_commit,
806 	.vsync_time      = dpu_kms_vsync_time,
807 	.prepare_commit  = dpu_kms_prepare_commit,
808 	.flush_commit    = dpu_kms_flush_commit,
809 	.wait_flush      = dpu_kms_wait_flush,
810 	.complete_commit = dpu_kms_complete_commit,
811 	.enable_vblank   = dpu_kms_enable_vblank,
812 	.disable_vblank  = dpu_kms_disable_vblank,
813 	.check_modified_format = dpu_format_check_modified_format,
814 	.get_format      = dpu_get_msm_format,
815 	.round_pixclk    = dpu_kms_round_pixclk,
816 	.destroy         = dpu_kms_destroy,
817 	.set_encoder_mode = _dpu_kms_set_encoder_mode,
818 #ifdef CONFIG_DEBUG_FS
819 	.debugfs_init    = dpu_kms_debugfs_init,
820 #endif
821 };
822 
823 static void _dpu_kms_mmu_destroy(struct dpu_kms *dpu_kms)
824 {
825 	struct msm_mmu *mmu;
826 
827 	if (!dpu_kms->base.aspace)
828 		return;
829 
830 	mmu = dpu_kms->base.aspace->mmu;
831 
832 	mmu->funcs->detach(mmu);
833 	msm_gem_address_space_put(dpu_kms->base.aspace);
834 
835 	dpu_kms->base.aspace = NULL;
836 }
837 
838 static int _dpu_kms_mmu_init(struct dpu_kms *dpu_kms)
839 {
840 	struct iommu_domain *domain;
841 	struct msm_gem_address_space *aspace;
842 	struct msm_mmu *mmu;
843 
844 	domain = iommu_domain_alloc(&platform_bus_type);
845 	if (!domain)
846 		return 0;
847 
848 	mmu = msm_iommu_new(dpu_kms->dev->dev, domain);
849 	aspace = msm_gem_address_space_create(mmu, "dpu1",
850 		0x1000, 0x100000000 - 0x1000);
851 
852 	if (IS_ERR(aspace)) {
853 		mmu->funcs->destroy(mmu);
854 		return PTR_ERR(aspace);
855 	}
856 
857 	dpu_kms->base.aspace = aspace;
858 	return 0;
859 }
860 
861 static struct dss_clk *_dpu_kms_get_clk(struct dpu_kms *dpu_kms,
862 		char *clock_name)
863 {
864 	struct dss_module_power *mp = &dpu_kms->mp;
865 	int i;
866 
867 	for (i = 0; i < mp->num_clk; i++) {
868 		if (!strcmp(mp->clk_config[i].clk_name, clock_name))
869 			return &mp->clk_config[i];
870 	}
871 
872 	return NULL;
873 }
874 
875 u64 dpu_kms_get_clk_rate(struct dpu_kms *dpu_kms, char *clock_name)
876 {
877 	struct dss_clk *clk;
878 
879 	clk = _dpu_kms_get_clk(dpu_kms, clock_name);
880 	if (!clk)
881 		return -EINVAL;
882 
883 	return clk_get_rate(clk->clk);
884 }
885 
886 static int dpu_kms_hw_init(struct msm_kms *kms)
887 {
888 	struct dpu_kms *dpu_kms;
889 	struct drm_device *dev;
890 	int i, rc = -EINVAL;
891 
892 	if (!kms) {
893 		DPU_ERROR("invalid kms\n");
894 		return rc;
895 	}
896 
897 	dpu_kms = to_dpu_kms(kms);
898 	dev = dpu_kms->dev;
899 
900 	rc = dpu_kms_global_obj_init(dpu_kms);
901 	if (rc)
902 		return rc;
903 
904 	atomic_set(&dpu_kms->bandwidth_ref, 0);
905 
906 	dpu_kms->mmio = msm_ioremap(dpu_kms->pdev, "mdp", "mdp");
907 	if (IS_ERR(dpu_kms->mmio)) {
908 		rc = PTR_ERR(dpu_kms->mmio);
909 		DPU_ERROR("mdp register memory map failed: %d\n", rc);
910 		dpu_kms->mmio = NULL;
911 		goto error;
912 	}
913 	DRM_DEBUG("mapped dpu address space @%pK\n", dpu_kms->mmio);
914 
915 	dpu_kms->vbif[VBIF_RT] = msm_ioremap(dpu_kms->pdev, "vbif", "vbif");
916 	if (IS_ERR(dpu_kms->vbif[VBIF_RT])) {
917 		rc = PTR_ERR(dpu_kms->vbif[VBIF_RT]);
918 		DPU_ERROR("vbif register memory map failed: %d\n", rc);
919 		dpu_kms->vbif[VBIF_RT] = NULL;
920 		goto error;
921 	}
922 	dpu_kms->vbif[VBIF_NRT] = msm_ioremap_quiet(dpu_kms->pdev, "vbif_nrt", "vbif_nrt");
923 	if (IS_ERR(dpu_kms->vbif[VBIF_NRT])) {
924 		dpu_kms->vbif[VBIF_NRT] = NULL;
925 		DPU_DEBUG("VBIF NRT is not defined");
926 	}
927 
928 	dpu_kms->reg_dma = msm_ioremap_quiet(dpu_kms->pdev, "regdma", "regdma");
929 	if (IS_ERR(dpu_kms->reg_dma)) {
930 		dpu_kms->reg_dma = NULL;
931 		DPU_DEBUG("REG_DMA is not defined");
932 	}
933 
934 	pm_runtime_get_sync(&dpu_kms->pdev->dev);
935 
936 	dpu_kms->core_rev = readl_relaxed(dpu_kms->mmio + 0x0);
937 
938 	pr_info("dpu hardware revision:0x%x\n", dpu_kms->core_rev);
939 
940 	dpu_kms->catalog = dpu_hw_catalog_init(dpu_kms->core_rev);
941 	if (IS_ERR_OR_NULL(dpu_kms->catalog)) {
942 		rc = PTR_ERR(dpu_kms->catalog);
943 		if (!dpu_kms->catalog)
944 			rc = -EINVAL;
945 		DPU_ERROR("catalog init failed: %d\n", rc);
946 		dpu_kms->catalog = NULL;
947 		goto power_error;
948 	}
949 
950 	/*
951 	 * Now we need to read the HW catalog and initialize resources such as
952 	 * clocks, regulators, GDSC/MMAGIC, ioremap the register ranges etc
953 	 */
954 	rc = _dpu_kms_mmu_init(dpu_kms);
955 	if (rc) {
956 		DPU_ERROR("dpu_kms_mmu_init failed: %d\n", rc);
957 		goto power_error;
958 	}
959 
960 	rc = dpu_rm_init(&dpu_kms->rm, dpu_kms->catalog, dpu_kms->mmio);
961 	if (rc) {
962 		DPU_ERROR("rm init failed: %d\n", rc);
963 		goto power_error;
964 	}
965 
966 	dpu_kms->rm_init = true;
967 
968 	dpu_kms->hw_mdp = dpu_hw_mdptop_init(MDP_TOP, dpu_kms->mmio,
969 					     dpu_kms->catalog);
970 	if (IS_ERR(dpu_kms->hw_mdp)) {
971 		rc = PTR_ERR(dpu_kms->hw_mdp);
972 		DPU_ERROR("failed to get hw_mdp: %d\n", rc);
973 		dpu_kms->hw_mdp = NULL;
974 		goto power_error;
975 	}
976 
977 	for (i = 0; i < dpu_kms->catalog->vbif_count; i++) {
978 		u32 vbif_idx = dpu_kms->catalog->vbif[i].id;
979 
980 		dpu_kms->hw_vbif[i] = dpu_hw_vbif_init(vbif_idx,
981 				dpu_kms->vbif[vbif_idx], dpu_kms->catalog);
982 		if (IS_ERR_OR_NULL(dpu_kms->hw_vbif[vbif_idx])) {
983 			rc = PTR_ERR(dpu_kms->hw_vbif[vbif_idx]);
984 			if (!dpu_kms->hw_vbif[vbif_idx])
985 				rc = -EINVAL;
986 			DPU_ERROR("failed to init vbif %d: %d\n", vbif_idx, rc);
987 			dpu_kms->hw_vbif[vbif_idx] = NULL;
988 			goto power_error;
989 		}
990 	}
991 
992 	rc = dpu_core_perf_init(&dpu_kms->perf, dev, dpu_kms->catalog,
993 			_dpu_kms_get_clk(dpu_kms, "core"));
994 	if (rc) {
995 		DPU_ERROR("failed to init perf %d\n", rc);
996 		goto perf_err;
997 	}
998 
999 	dpu_kms->hw_intr = dpu_hw_intr_init(dpu_kms->mmio, dpu_kms->catalog);
1000 	if (IS_ERR_OR_NULL(dpu_kms->hw_intr)) {
1001 		rc = PTR_ERR(dpu_kms->hw_intr);
1002 		DPU_ERROR("hw_intr init failed: %d\n", rc);
1003 		dpu_kms->hw_intr = NULL;
1004 		goto hw_intr_init_err;
1005 	}
1006 
1007 	dev->mode_config.min_width = 0;
1008 	dev->mode_config.min_height = 0;
1009 
1010 	/*
1011 	 * max crtc width is equal to the max mixer width * 2 and max height is
1012 	 * is 4K
1013 	 */
1014 	dev->mode_config.max_width =
1015 			dpu_kms->catalog->caps->max_mixer_width * 2;
1016 	dev->mode_config.max_height = 4096;
1017 
1018 	/*
1019 	 * Support format modifiers for compression etc.
1020 	 */
1021 	dev->mode_config.allow_fb_modifiers = true;
1022 
1023 	/*
1024 	 * _dpu_kms_drm_obj_init should create the DRM related objects
1025 	 * i.e. CRTCs, planes, encoders, connectors and so forth
1026 	 */
1027 	rc = _dpu_kms_drm_obj_init(dpu_kms);
1028 	if (rc) {
1029 		DPU_ERROR("modeset init failed: %d\n", rc);
1030 		goto drm_obj_init_err;
1031 	}
1032 
1033 	dpu_vbif_init_memtypes(dpu_kms);
1034 
1035 	if (of_device_is_compatible(dev->dev->of_node, "qcom,sc7180-mdss"))
1036 		dpu_kms_parse_data_bus_icc_path(dpu_kms);
1037 
1038 	pm_runtime_put_sync(&dpu_kms->pdev->dev);
1039 
1040 	return 0;
1041 
1042 drm_obj_init_err:
1043 	dpu_core_perf_destroy(&dpu_kms->perf);
1044 hw_intr_init_err:
1045 perf_err:
1046 power_error:
1047 	pm_runtime_put_sync(&dpu_kms->pdev->dev);
1048 error:
1049 	_dpu_kms_hw_destroy(dpu_kms);
1050 
1051 	return rc;
1052 }
1053 
1054 struct msm_kms *dpu_kms_init(struct drm_device *dev)
1055 {
1056 	struct msm_drm_private *priv;
1057 	struct dpu_kms *dpu_kms;
1058 	int irq;
1059 
1060 	if (!dev) {
1061 		DPU_ERROR("drm device node invalid\n");
1062 		return ERR_PTR(-EINVAL);
1063 	}
1064 
1065 	priv = dev->dev_private;
1066 	dpu_kms = to_dpu_kms(priv->kms);
1067 
1068 	irq = irq_of_parse_and_map(dpu_kms->pdev->dev.of_node, 0);
1069 	if (irq < 0) {
1070 		DPU_ERROR("failed to get irq: %d\n", irq);
1071 		return ERR_PTR(irq);
1072 	}
1073 	dpu_kms->base.irq = irq;
1074 
1075 	return &dpu_kms->base;
1076 }
1077 
1078 static int dpu_bind(struct device *dev, struct device *master, void *data)
1079 {
1080 	struct drm_device *ddev = dev_get_drvdata(master);
1081 	struct platform_device *pdev = to_platform_device(dev);
1082 	struct msm_drm_private *priv = ddev->dev_private;
1083 	struct dpu_kms *dpu_kms;
1084 	struct dss_module_power *mp;
1085 	int ret = 0;
1086 
1087 	dpu_kms = devm_kzalloc(&pdev->dev, sizeof(*dpu_kms), GFP_KERNEL);
1088 	if (!dpu_kms)
1089 		return -ENOMEM;
1090 
1091 	dpu_kms->opp_table = dev_pm_opp_set_clkname(dev, "core");
1092 	if (IS_ERR(dpu_kms->opp_table))
1093 		return PTR_ERR(dpu_kms->opp_table);
1094 	/* OPP table is optional */
1095 	ret = dev_pm_opp_of_add_table(dev);
1096 	if (ret && ret != -ENODEV) {
1097 		dev_err(dev, "invalid OPP table in device tree\n");
1098 		goto put_clkname;
1099 	}
1100 
1101 	mp = &dpu_kms->mp;
1102 	ret = msm_dss_parse_clock(pdev, mp);
1103 	if (ret) {
1104 		DPU_ERROR("failed to parse clocks, ret=%d\n", ret);
1105 		goto err;
1106 	}
1107 
1108 	platform_set_drvdata(pdev, dpu_kms);
1109 
1110 	ret = msm_kms_init(&dpu_kms->base, &kms_funcs);
1111 	if (ret) {
1112 		DPU_ERROR("failed to init kms, ret=%d\n", ret);
1113 		goto err;
1114 	}
1115 	dpu_kms->dev = ddev;
1116 	dpu_kms->pdev = pdev;
1117 
1118 	pm_runtime_enable(&pdev->dev);
1119 	dpu_kms->rpm_enabled = true;
1120 
1121 	priv->kms = &dpu_kms->base;
1122 	return ret;
1123 err:
1124 	dev_pm_opp_of_remove_table(dev);
1125 put_clkname:
1126 	dev_pm_opp_put_clkname(dpu_kms->opp_table);
1127 	return ret;
1128 }
1129 
1130 static void dpu_unbind(struct device *dev, struct device *master, void *data)
1131 {
1132 	struct platform_device *pdev = to_platform_device(dev);
1133 	struct dpu_kms *dpu_kms = platform_get_drvdata(pdev);
1134 	struct dss_module_power *mp = &dpu_kms->mp;
1135 
1136 	msm_dss_put_clk(mp->clk_config, mp->num_clk);
1137 	devm_kfree(&pdev->dev, mp->clk_config);
1138 	mp->num_clk = 0;
1139 
1140 	if (dpu_kms->rpm_enabled)
1141 		pm_runtime_disable(&pdev->dev);
1142 
1143 	dev_pm_opp_of_remove_table(dev);
1144 	dev_pm_opp_put_clkname(dpu_kms->opp_table);
1145 }
1146 
1147 static const struct component_ops dpu_ops = {
1148 	.bind   = dpu_bind,
1149 	.unbind = dpu_unbind,
1150 };
1151 
1152 static int dpu_dev_probe(struct platform_device *pdev)
1153 {
1154 	return component_add(&pdev->dev, &dpu_ops);
1155 }
1156 
1157 static int dpu_dev_remove(struct platform_device *pdev)
1158 {
1159 	component_del(&pdev->dev, &dpu_ops);
1160 	return 0;
1161 }
1162 
1163 static int __maybe_unused dpu_runtime_suspend(struct device *dev)
1164 {
1165 	int i, rc = -1;
1166 	struct platform_device *pdev = to_platform_device(dev);
1167 	struct dpu_kms *dpu_kms = platform_get_drvdata(pdev);
1168 	struct dss_module_power *mp = &dpu_kms->mp;
1169 
1170 	/* Drop the performance state vote */
1171 	dev_pm_opp_set_rate(dev, 0);
1172 	rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, false);
1173 	if (rc)
1174 		DPU_ERROR("clock disable failed rc:%d\n", rc);
1175 
1176 	for (i = 0; i < dpu_kms->num_paths; i++)
1177 		icc_set_bw(dpu_kms->path[i], 0, 0);
1178 
1179 	return rc;
1180 }
1181 
1182 static int __maybe_unused dpu_runtime_resume(struct device *dev)
1183 {
1184 	int rc = -1;
1185 	struct platform_device *pdev = to_platform_device(dev);
1186 	struct dpu_kms *dpu_kms = platform_get_drvdata(pdev);
1187 	struct drm_encoder *encoder;
1188 	struct drm_device *ddev;
1189 	struct dss_module_power *mp = &dpu_kms->mp;
1190 	int i;
1191 
1192 	ddev = dpu_kms->dev;
1193 
1194 	/* Min vote of BW is required before turning on AXI clk */
1195 	for (i = 0; i < dpu_kms->num_paths; i++)
1196 		icc_set_bw(dpu_kms->path[i], 0,
1197 			dpu_kms->catalog->perf.min_dram_ib);
1198 
1199 	rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, true);
1200 	if (rc) {
1201 		DPU_ERROR("clock enable failed rc:%d\n", rc);
1202 		return rc;
1203 	}
1204 
1205 	dpu_vbif_init_memtypes(dpu_kms);
1206 
1207 	drm_for_each_encoder(encoder, ddev)
1208 		dpu_encoder_virt_runtime_resume(encoder);
1209 
1210 	return rc;
1211 }
1212 
1213 static const struct dev_pm_ops dpu_pm_ops = {
1214 	SET_RUNTIME_PM_OPS(dpu_runtime_suspend, dpu_runtime_resume, NULL)
1215 	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1216 				pm_runtime_force_resume)
1217 };
1218 
1219 static const struct of_device_id dpu_dt_match[] = {
1220 	{ .compatible = "qcom,sdm845-dpu", },
1221 	{ .compatible = "qcom,sc7180-dpu", },
1222 	{}
1223 };
1224 MODULE_DEVICE_TABLE(of, dpu_dt_match);
1225 
1226 static struct platform_driver dpu_driver = {
1227 	.probe = dpu_dev_probe,
1228 	.remove = dpu_dev_remove,
1229 	.driver = {
1230 		.name = "msm_dpu",
1231 		.of_match_table = dpu_dt_match,
1232 		.pm = &dpu_pm_ops,
1233 	},
1234 };
1235 
1236 void __init msm_dpu_register(void)
1237 {
1238 	platform_driver_register(&dpu_driver);
1239 }
1240 
1241 void __exit msm_dpu_unregister(void)
1242 {
1243 	platform_driver_unregister(&dpu_driver);
1244 }
1245