1 /* 2 * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved. 3 * Copyright (C) 2013 Red Hat 4 * Author: Rob Clark <robdclark@gmail.com> 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published by 8 * the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ 20 21 #include <drm/drm_crtc.h> 22 #include <linux/debugfs.h> 23 #include <linux/of_irq.h> 24 #include <linux/dma-buf.h> 25 26 #include "msm_drv.h" 27 #include "msm_mmu.h" 28 #include "msm_gem.h" 29 30 #include "dpu_kms.h" 31 #include "dpu_core_irq.h" 32 #include "dpu_formats.h" 33 #include "dpu_hw_vbif.h" 34 #include "dpu_vbif.h" 35 #include "dpu_encoder.h" 36 #include "dpu_plane.h" 37 #include "dpu_crtc.h" 38 39 #define CREATE_TRACE_POINTS 40 #include "dpu_trace.h" 41 42 static const char * const iommu_ports[] = { 43 "mdp_0", 44 }; 45 46 /* 47 * To enable overall DRM driver logging 48 * # echo 0x2 > /sys/module/drm/parameters/debug 49 * 50 * To enable DRM driver h/w logging 51 * # echo <mask> > /sys/kernel/debug/dri/0/debug/hw_log_mask 52 * 53 * See dpu_hw_mdss.h for h/w logging mask definitions (search for DPU_DBG_MASK_) 54 */ 55 #define DPU_DEBUGFS_DIR "msm_dpu" 56 #define DPU_DEBUGFS_HWMASKNAME "hw_log_mask" 57 58 static int dpu_kms_hw_init(struct msm_kms *kms); 59 static int _dpu_kms_mmu_destroy(struct dpu_kms *dpu_kms); 60 61 static unsigned long dpu_iomap_size(struct platform_device *pdev, 62 const char *name) 63 { 64 struct resource *res; 65 66 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name); 67 if (!res) { 68 DRM_ERROR("failed to get memory resource: %s\n", name); 69 return 0; 70 } 71 72 return resource_size(res); 73 } 74 75 #ifdef CONFIG_DEBUG_FS 76 static int _dpu_danger_signal_status(struct seq_file *s, 77 bool danger_status) 78 { 79 struct dpu_kms *kms = (struct dpu_kms *)s->private; 80 struct msm_drm_private *priv; 81 struct dpu_danger_safe_status status; 82 int i; 83 84 if (!kms || !kms->dev || !kms->dev->dev_private || !kms->hw_mdp) { 85 DPU_ERROR("invalid arg(s)\n"); 86 return 0; 87 } 88 89 priv = kms->dev->dev_private; 90 memset(&status, 0, sizeof(struct dpu_danger_safe_status)); 91 92 pm_runtime_get_sync(&kms->pdev->dev); 93 if (danger_status) { 94 seq_puts(s, "\nDanger signal status:\n"); 95 if (kms->hw_mdp->ops.get_danger_status) 96 kms->hw_mdp->ops.get_danger_status(kms->hw_mdp, 97 &status); 98 } else { 99 seq_puts(s, "\nSafe signal status:\n"); 100 if (kms->hw_mdp->ops.get_danger_status) 101 kms->hw_mdp->ops.get_danger_status(kms->hw_mdp, 102 &status); 103 } 104 pm_runtime_put_sync(&kms->pdev->dev); 105 106 seq_printf(s, "MDP : 0x%x\n", status.mdp); 107 108 for (i = SSPP_VIG0; i < SSPP_MAX; i++) 109 seq_printf(s, "SSPP%d : 0x%x \t", i - SSPP_VIG0, 110 status.sspp[i]); 111 seq_puts(s, "\n"); 112 113 return 0; 114 } 115 116 #define DEFINE_DPU_DEBUGFS_SEQ_FOPS(__prefix) \ 117 static int __prefix ## _open(struct inode *inode, struct file *file) \ 118 { \ 119 return single_open(file, __prefix ## _show, inode->i_private); \ 120 } \ 121 static const struct file_operations __prefix ## _fops = { \ 122 .owner = THIS_MODULE, \ 123 .open = __prefix ## _open, \ 124 .release = single_release, \ 125 .read = seq_read, \ 126 .llseek = seq_lseek, \ 127 } 128 129 static int dpu_debugfs_danger_stats_show(struct seq_file *s, void *v) 130 { 131 return _dpu_danger_signal_status(s, true); 132 } 133 DEFINE_DPU_DEBUGFS_SEQ_FOPS(dpu_debugfs_danger_stats); 134 135 static int dpu_debugfs_safe_stats_show(struct seq_file *s, void *v) 136 { 137 return _dpu_danger_signal_status(s, false); 138 } 139 DEFINE_DPU_DEBUGFS_SEQ_FOPS(dpu_debugfs_safe_stats); 140 141 static void dpu_debugfs_danger_destroy(struct dpu_kms *dpu_kms) 142 { 143 debugfs_remove_recursive(dpu_kms->debugfs_danger); 144 dpu_kms->debugfs_danger = NULL; 145 } 146 147 static int dpu_debugfs_danger_init(struct dpu_kms *dpu_kms, 148 struct dentry *parent) 149 { 150 dpu_kms->debugfs_danger = debugfs_create_dir("danger", 151 parent); 152 if (!dpu_kms->debugfs_danger) { 153 DPU_ERROR("failed to create danger debugfs\n"); 154 return -EINVAL; 155 } 156 157 debugfs_create_file("danger_status", 0600, dpu_kms->debugfs_danger, 158 dpu_kms, &dpu_debugfs_danger_stats_fops); 159 debugfs_create_file("safe_status", 0600, dpu_kms->debugfs_danger, 160 dpu_kms, &dpu_debugfs_safe_stats_fops); 161 162 return 0; 163 } 164 165 static int _dpu_debugfs_show_regset32(struct seq_file *s, void *data) 166 { 167 struct dpu_debugfs_regset32 *regset; 168 struct dpu_kms *dpu_kms; 169 struct drm_device *dev; 170 struct msm_drm_private *priv; 171 void __iomem *base; 172 uint32_t i, addr; 173 174 if (!s || !s->private) 175 return 0; 176 177 regset = s->private; 178 179 dpu_kms = regset->dpu_kms; 180 if (!dpu_kms || !dpu_kms->mmio) 181 return 0; 182 183 dev = dpu_kms->dev; 184 if (!dev) 185 return 0; 186 187 priv = dev->dev_private; 188 if (!priv) 189 return 0; 190 191 base = dpu_kms->mmio + regset->offset; 192 193 /* insert padding spaces, if needed */ 194 if (regset->offset & 0xF) { 195 seq_printf(s, "[%x]", regset->offset & ~0xF); 196 for (i = 0; i < (regset->offset & 0xF); i += 4) 197 seq_puts(s, " "); 198 } 199 200 pm_runtime_get_sync(&dpu_kms->pdev->dev); 201 202 /* main register output */ 203 for (i = 0; i < regset->blk_len; i += 4) { 204 addr = regset->offset + i; 205 if ((addr & 0xF) == 0x0) 206 seq_printf(s, i ? "\n[%x]" : "[%x]", addr); 207 seq_printf(s, " %08x", readl_relaxed(base + i)); 208 } 209 seq_puts(s, "\n"); 210 pm_runtime_put_sync(&dpu_kms->pdev->dev); 211 212 return 0; 213 } 214 215 static int dpu_debugfs_open_regset32(struct inode *inode, 216 struct file *file) 217 { 218 return single_open(file, _dpu_debugfs_show_regset32, inode->i_private); 219 } 220 221 static const struct file_operations dpu_fops_regset32 = { 222 .open = dpu_debugfs_open_regset32, 223 .read = seq_read, 224 .llseek = seq_lseek, 225 .release = single_release, 226 }; 227 228 void dpu_debugfs_setup_regset32(struct dpu_debugfs_regset32 *regset, 229 uint32_t offset, uint32_t length, struct dpu_kms *dpu_kms) 230 { 231 if (regset) { 232 regset->offset = offset; 233 regset->blk_len = length; 234 regset->dpu_kms = dpu_kms; 235 } 236 } 237 238 void *dpu_debugfs_create_regset32(const char *name, umode_t mode, 239 void *parent, struct dpu_debugfs_regset32 *regset) 240 { 241 if (!name || !regset || !regset->dpu_kms || !regset->blk_len) 242 return NULL; 243 244 /* make sure offset is a multiple of 4 */ 245 regset->offset = round_down(regset->offset, 4); 246 247 return debugfs_create_file(name, mode, parent, 248 regset, &dpu_fops_regset32); 249 } 250 251 static int _dpu_debugfs_init(struct dpu_kms *dpu_kms) 252 { 253 void *p; 254 int rc; 255 256 p = dpu_hw_util_get_log_mask_ptr(); 257 258 if (!dpu_kms || !p) 259 return -EINVAL; 260 261 dpu_kms->debugfs_root = debugfs_create_dir("debug", 262 dpu_kms->dev->primary->debugfs_root); 263 if (IS_ERR_OR_NULL(dpu_kms->debugfs_root)) { 264 DRM_ERROR("debugfs create_dir failed %ld\n", 265 PTR_ERR(dpu_kms->debugfs_root)); 266 return PTR_ERR(dpu_kms->debugfs_root); 267 } 268 269 rc = dpu_dbg_debugfs_register(dpu_kms->debugfs_root); 270 if (rc) { 271 DRM_ERROR("failed to reg dpu dbg debugfs: %d\n", rc); 272 return rc; 273 } 274 275 /* allow root to be NULL */ 276 debugfs_create_x32(DPU_DEBUGFS_HWMASKNAME, 0600, dpu_kms->debugfs_root, p); 277 278 (void) dpu_debugfs_danger_init(dpu_kms, dpu_kms->debugfs_root); 279 (void) dpu_debugfs_vbif_init(dpu_kms, dpu_kms->debugfs_root); 280 (void) dpu_debugfs_core_irq_init(dpu_kms, dpu_kms->debugfs_root); 281 282 rc = dpu_core_perf_debugfs_init(&dpu_kms->perf, dpu_kms->debugfs_root); 283 if (rc) { 284 DPU_ERROR("failed to init perf %d\n", rc); 285 return rc; 286 } 287 288 return 0; 289 } 290 291 static void _dpu_debugfs_destroy(struct dpu_kms *dpu_kms) 292 { 293 /* don't need to NULL check debugfs_root */ 294 if (dpu_kms) { 295 dpu_debugfs_vbif_destroy(dpu_kms); 296 dpu_debugfs_danger_destroy(dpu_kms); 297 dpu_debugfs_core_irq_destroy(dpu_kms); 298 debugfs_remove_recursive(dpu_kms->debugfs_root); 299 } 300 } 301 #else 302 static void _dpu_debugfs_destroy(struct dpu_kms *dpu_kms) 303 { 304 } 305 #endif 306 307 static int dpu_kms_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc) 308 { 309 return dpu_crtc_vblank(crtc, true); 310 } 311 312 static void dpu_kms_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc) 313 { 314 dpu_crtc_vblank(crtc, false); 315 } 316 317 static void dpu_kms_prepare_commit(struct msm_kms *kms, 318 struct drm_atomic_state *state) 319 { 320 struct dpu_kms *dpu_kms; 321 struct msm_drm_private *priv; 322 struct drm_device *dev; 323 struct drm_encoder *encoder; 324 325 if (!kms) 326 return; 327 dpu_kms = to_dpu_kms(kms); 328 dev = dpu_kms->dev; 329 330 if (!dev || !dev->dev_private) 331 return; 332 priv = dev->dev_private; 333 pm_runtime_get_sync(&dpu_kms->pdev->dev); 334 335 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) 336 if (encoder->crtc != NULL) 337 dpu_encoder_prepare_commit(encoder); 338 } 339 340 /* 341 * Override the encoder enable since we need to setup the inline rotator and do 342 * some crtc magic before enabling any bridge that might be present. 343 */ 344 void dpu_kms_encoder_enable(struct drm_encoder *encoder) 345 { 346 const struct drm_encoder_helper_funcs *funcs = encoder->helper_private; 347 struct drm_crtc *crtc = encoder->crtc; 348 349 /* Forward this enable call to the commit hook */ 350 if (funcs && funcs->commit) 351 funcs->commit(encoder); 352 353 if (crtc && crtc->state->active) { 354 trace_dpu_kms_enc_enable(DRMID(crtc)); 355 dpu_crtc_commit_kickoff(crtc); 356 } 357 } 358 359 static void dpu_kms_commit(struct msm_kms *kms, struct drm_atomic_state *state) 360 { 361 struct drm_crtc *crtc; 362 struct drm_crtc_state *crtc_state; 363 int i; 364 365 for_each_new_crtc_in_state(state, crtc, crtc_state, i) { 366 /* If modeset is required, kickoff is run in encoder_enable */ 367 if (drm_atomic_crtc_needs_modeset(crtc_state)) 368 continue; 369 370 if (crtc->state->active) { 371 trace_dpu_kms_commit(DRMID(crtc)); 372 dpu_crtc_commit_kickoff(crtc); 373 } 374 } 375 } 376 377 static void dpu_kms_complete_commit(struct msm_kms *kms, 378 struct drm_atomic_state *old_state) 379 { 380 struct dpu_kms *dpu_kms; 381 struct msm_drm_private *priv; 382 struct drm_crtc *crtc; 383 struct drm_crtc_state *old_crtc_state; 384 int i; 385 386 if (!kms || !old_state) 387 return; 388 dpu_kms = to_dpu_kms(kms); 389 390 if (!dpu_kms->dev || !dpu_kms->dev->dev_private) 391 return; 392 priv = dpu_kms->dev->dev_private; 393 394 DPU_ATRACE_BEGIN("kms_complete_commit"); 395 396 for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) 397 dpu_crtc_complete_commit(crtc, old_crtc_state); 398 399 pm_runtime_put_sync(&dpu_kms->pdev->dev); 400 401 DPU_ATRACE_END("kms_complete_commit"); 402 } 403 404 static void dpu_kms_wait_for_commit_done(struct msm_kms *kms, 405 struct drm_crtc *crtc) 406 { 407 struct drm_encoder *encoder; 408 struct drm_device *dev; 409 int ret; 410 411 if (!kms || !crtc || !crtc->state) { 412 DPU_ERROR("invalid params\n"); 413 return; 414 } 415 416 dev = crtc->dev; 417 418 if (!crtc->state->enable) { 419 DPU_DEBUG("[crtc:%d] not enable\n", crtc->base.id); 420 return; 421 } 422 423 if (!crtc->state->active) { 424 DPU_DEBUG("[crtc:%d] not active\n", crtc->base.id); 425 return; 426 } 427 428 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 429 if (encoder->crtc != crtc) 430 continue; 431 /* 432 * Wait for post-flush if necessary to delay before 433 * plane_cleanup. For example, wait for vsync in case of video 434 * mode panels. This may be a no-op for command mode panels. 435 */ 436 trace_dpu_kms_wait_for_commit_done(DRMID(crtc)); 437 ret = dpu_encoder_wait_for_event(encoder, MSM_ENC_COMMIT_DONE); 438 if (ret && ret != -EWOULDBLOCK) { 439 DPU_ERROR("wait for commit done returned %d\n", ret); 440 break; 441 } 442 } 443 } 444 445 static void _dpu_kms_initialize_dsi(struct drm_device *dev, 446 struct msm_drm_private *priv, 447 struct dpu_kms *dpu_kms) 448 { 449 struct drm_encoder *encoder = NULL; 450 int i, rc; 451 452 /*TODO: Support two independent DSI connectors */ 453 encoder = dpu_encoder_init(dev, DRM_MODE_CONNECTOR_DSI); 454 if (IS_ERR_OR_NULL(encoder)) { 455 DPU_ERROR("encoder init failed for dsi display\n"); 456 return; 457 } 458 459 priv->encoders[priv->num_encoders++] = encoder; 460 461 for (i = 0; i < ARRAY_SIZE(priv->dsi); i++) { 462 if (!priv->dsi[i]) { 463 DPU_DEBUG("invalid msm_dsi for ctrl %d\n", i); 464 return; 465 } 466 467 rc = msm_dsi_modeset_init(priv->dsi[i], dev, encoder); 468 if (rc) { 469 DPU_ERROR("modeset_init failed for dsi[%d], rc = %d\n", 470 i, rc); 471 continue; 472 } 473 } 474 } 475 476 /** 477 * _dpu_kms_setup_displays - create encoders, bridges and connectors 478 * for underlying displays 479 * @dev: Pointer to drm device structure 480 * @priv: Pointer to private drm device data 481 * @dpu_kms: Pointer to dpu kms structure 482 * Returns: Zero on success 483 */ 484 static void _dpu_kms_setup_displays(struct drm_device *dev, 485 struct msm_drm_private *priv, 486 struct dpu_kms *dpu_kms) 487 { 488 _dpu_kms_initialize_dsi(dev, priv, dpu_kms); 489 490 /** 491 * Extend this function to initialize other 492 * types of displays 493 */ 494 } 495 496 static void _dpu_kms_drm_obj_destroy(struct dpu_kms *dpu_kms) 497 { 498 struct msm_drm_private *priv; 499 int i; 500 501 if (!dpu_kms) { 502 DPU_ERROR("invalid dpu_kms\n"); 503 return; 504 } else if (!dpu_kms->dev) { 505 DPU_ERROR("invalid dev\n"); 506 return; 507 } else if (!dpu_kms->dev->dev_private) { 508 DPU_ERROR("invalid dev_private\n"); 509 return; 510 } 511 priv = dpu_kms->dev->dev_private; 512 513 for (i = 0; i < priv->num_crtcs; i++) 514 priv->crtcs[i]->funcs->destroy(priv->crtcs[i]); 515 priv->num_crtcs = 0; 516 517 for (i = 0; i < priv->num_planes; i++) 518 priv->planes[i]->funcs->destroy(priv->planes[i]); 519 priv->num_planes = 0; 520 521 for (i = 0; i < priv->num_connectors; i++) 522 priv->connectors[i]->funcs->destroy(priv->connectors[i]); 523 priv->num_connectors = 0; 524 525 for (i = 0; i < priv->num_encoders; i++) 526 priv->encoders[i]->funcs->destroy(priv->encoders[i]); 527 priv->num_encoders = 0; 528 } 529 530 static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms) 531 { 532 struct drm_device *dev; 533 struct drm_plane *primary_planes[MAX_PLANES], *plane; 534 struct drm_crtc *crtc; 535 536 struct msm_drm_private *priv; 537 struct dpu_mdss_cfg *catalog; 538 539 int primary_planes_idx = 0, i, ret; 540 int max_crtc_count; 541 542 if (!dpu_kms || !dpu_kms->dev || !dpu_kms->dev->dev) { 543 DPU_ERROR("invalid dpu_kms\n"); 544 return -EINVAL; 545 } 546 547 dev = dpu_kms->dev; 548 priv = dev->dev_private; 549 catalog = dpu_kms->catalog; 550 551 /* 552 * Create encoder and query display drivers to create 553 * bridges and connectors 554 */ 555 _dpu_kms_setup_displays(dev, priv, dpu_kms); 556 557 max_crtc_count = min(catalog->mixer_count, priv->num_encoders); 558 559 /* Create the planes */ 560 for (i = 0; i < catalog->sspp_count; i++) { 561 bool primary = true; 562 563 if (catalog->sspp[i].features & BIT(DPU_SSPP_CURSOR) 564 || primary_planes_idx >= max_crtc_count) 565 primary = false; 566 567 plane = dpu_plane_init(dev, catalog->sspp[i].id, primary, 568 (1UL << max_crtc_count) - 1, 0); 569 if (IS_ERR(plane)) { 570 DPU_ERROR("dpu_plane_init failed\n"); 571 ret = PTR_ERR(plane); 572 goto fail; 573 } 574 priv->planes[priv->num_planes++] = plane; 575 576 if (primary) 577 primary_planes[primary_planes_idx++] = plane; 578 } 579 580 max_crtc_count = min(max_crtc_count, primary_planes_idx); 581 582 /* Create one CRTC per encoder */ 583 for (i = 0; i < max_crtc_count; i++) { 584 crtc = dpu_crtc_init(dev, primary_planes[i]); 585 if (IS_ERR(crtc)) { 586 ret = PTR_ERR(crtc); 587 goto fail; 588 } 589 priv->crtcs[priv->num_crtcs++] = crtc; 590 } 591 592 /* All CRTCs are compatible with all encoders */ 593 for (i = 0; i < priv->num_encoders; i++) 594 priv->encoders[i]->possible_crtcs = (1 << priv->num_crtcs) - 1; 595 596 return 0; 597 fail: 598 _dpu_kms_drm_obj_destroy(dpu_kms); 599 return ret; 600 } 601 602 #ifdef CONFIG_DEBUG_FS 603 static int dpu_kms_debugfs_init(struct msm_kms *kms, struct drm_minor *minor) 604 { 605 struct dpu_kms *dpu_kms = to_dpu_kms(kms); 606 struct drm_device *dev; 607 int rc; 608 609 if (!dpu_kms || !dpu_kms->dev || !dpu_kms->dev->dev) { 610 DPU_ERROR("invalid dpu_kms\n"); 611 return -EINVAL; 612 } 613 614 dev = dpu_kms->dev; 615 616 rc = _dpu_debugfs_init(dpu_kms); 617 if (rc) 618 DPU_ERROR("dpu_debugfs init failed: %d\n", rc); 619 620 return rc; 621 } 622 #endif 623 624 static long dpu_kms_round_pixclk(struct msm_kms *kms, unsigned long rate, 625 struct drm_encoder *encoder) 626 { 627 return rate; 628 } 629 630 static void _dpu_kms_hw_destroy(struct dpu_kms *dpu_kms) 631 { 632 struct drm_device *dev; 633 int i; 634 635 dev = dpu_kms->dev; 636 if (!dev) 637 return; 638 639 if (dpu_kms->hw_intr) 640 dpu_hw_intr_destroy(dpu_kms->hw_intr); 641 dpu_kms->hw_intr = NULL; 642 643 if (dpu_kms->power_event) 644 dpu_power_handle_unregister_event( 645 &dpu_kms->phandle, dpu_kms->power_event); 646 647 /* safe to call these more than once during shutdown */ 648 _dpu_debugfs_destroy(dpu_kms); 649 _dpu_kms_mmu_destroy(dpu_kms); 650 651 if (dpu_kms->catalog) { 652 for (i = 0; i < dpu_kms->catalog->vbif_count; i++) { 653 u32 vbif_idx = dpu_kms->catalog->vbif[i].id; 654 655 if ((vbif_idx < VBIF_MAX) && dpu_kms->hw_vbif[vbif_idx]) 656 dpu_hw_vbif_destroy(dpu_kms->hw_vbif[vbif_idx]); 657 } 658 } 659 660 if (dpu_kms->rm_init) 661 dpu_rm_destroy(&dpu_kms->rm); 662 dpu_kms->rm_init = false; 663 664 if (dpu_kms->catalog) 665 dpu_hw_catalog_deinit(dpu_kms->catalog); 666 dpu_kms->catalog = NULL; 667 668 if (dpu_kms->core_client) 669 dpu_power_client_destroy(&dpu_kms->phandle, 670 dpu_kms->core_client); 671 dpu_kms->core_client = NULL; 672 673 if (dpu_kms->vbif[VBIF_NRT]) 674 devm_iounmap(&dpu_kms->pdev->dev, dpu_kms->vbif[VBIF_NRT]); 675 dpu_kms->vbif[VBIF_NRT] = NULL; 676 677 if (dpu_kms->vbif[VBIF_RT]) 678 devm_iounmap(&dpu_kms->pdev->dev, dpu_kms->vbif[VBIF_RT]); 679 dpu_kms->vbif[VBIF_RT] = NULL; 680 681 if (dpu_kms->mmio) 682 devm_iounmap(&dpu_kms->pdev->dev, dpu_kms->mmio); 683 dpu_kms->mmio = NULL; 684 } 685 686 static void dpu_kms_destroy(struct msm_kms *kms) 687 { 688 struct dpu_kms *dpu_kms; 689 690 if (!kms) { 691 DPU_ERROR("invalid kms\n"); 692 return; 693 } 694 695 dpu_kms = to_dpu_kms(kms); 696 697 dpu_dbg_destroy(); 698 _dpu_kms_hw_destroy(dpu_kms); 699 } 700 701 static int dpu_kms_pm_suspend(struct device *dev) 702 { 703 struct drm_device *ddev; 704 struct drm_modeset_acquire_ctx ctx; 705 struct drm_atomic_state *state; 706 struct dpu_kms *dpu_kms; 707 int ret = 0, num_crtcs = 0; 708 709 if (!dev) 710 return -EINVAL; 711 712 ddev = dev_get_drvdata(dev); 713 if (!ddev || !ddev_to_msm_kms(ddev)) 714 return -EINVAL; 715 716 dpu_kms = to_dpu_kms(ddev_to_msm_kms(ddev)); 717 718 /* disable hot-plug polling */ 719 drm_kms_helper_poll_disable(ddev); 720 721 /* acquire modeset lock(s) */ 722 drm_modeset_acquire_init(&ctx, 0); 723 724 retry: 725 DPU_ATRACE_BEGIN("kms_pm_suspend"); 726 727 ret = drm_modeset_lock_all_ctx(ddev, &ctx); 728 if (ret) 729 goto unlock; 730 731 /* save current state for resume */ 732 if (dpu_kms->suspend_state) 733 drm_atomic_state_put(dpu_kms->suspend_state); 734 dpu_kms->suspend_state = drm_atomic_helper_duplicate_state(ddev, &ctx); 735 if (IS_ERR_OR_NULL(dpu_kms->suspend_state)) { 736 DRM_ERROR("failed to back up suspend state\n"); 737 dpu_kms->suspend_state = NULL; 738 goto unlock; 739 } 740 741 /* create atomic state to disable all CRTCs */ 742 state = drm_atomic_state_alloc(ddev); 743 if (IS_ERR_OR_NULL(state)) { 744 DRM_ERROR("failed to allocate crtc disable state\n"); 745 goto unlock; 746 } 747 748 state->acquire_ctx = &ctx; 749 750 /* check for nothing to do */ 751 if (num_crtcs == 0) { 752 DRM_DEBUG("all crtcs are already in the off state\n"); 753 drm_atomic_state_put(state); 754 goto suspended; 755 } 756 757 /* commit the "disable all" state */ 758 ret = drm_atomic_commit(state); 759 if (ret < 0) { 760 DRM_ERROR("failed to disable crtcs, %d\n", ret); 761 drm_atomic_state_put(state); 762 goto unlock; 763 } 764 765 suspended: 766 dpu_kms->suspend_block = true; 767 768 unlock: 769 if (ret == -EDEADLK) { 770 drm_modeset_backoff(&ctx); 771 goto retry; 772 } 773 drm_modeset_drop_locks(&ctx); 774 drm_modeset_acquire_fini(&ctx); 775 776 DPU_ATRACE_END("kms_pm_suspend"); 777 return 0; 778 } 779 780 static int dpu_kms_pm_resume(struct device *dev) 781 { 782 struct drm_device *ddev; 783 struct dpu_kms *dpu_kms; 784 int ret; 785 786 if (!dev) 787 return -EINVAL; 788 789 ddev = dev_get_drvdata(dev); 790 if (!ddev || !ddev_to_msm_kms(ddev)) 791 return -EINVAL; 792 793 dpu_kms = to_dpu_kms(ddev_to_msm_kms(ddev)); 794 795 DPU_ATRACE_BEGIN("kms_pm_resume"); 796 797 drm_mode_config_reset(ddev); 798 799 drm_modeset_lock_all(ddev); 800 801 dpu_kms->suspend_block = false; 802 803 if (dpu_kms->suspend_state) { 804 dpu_kms->suspend_state->acquire_ctx = 805 ddev->mode_config.acquire_ctx; 806 ret = drm_atomic_commit(dpu_kms->suspend_state); 807 if (ret < 0) { 808 DRM_ERROR("failed to restore state, %d\n", ret); 809 drm_atomic_state_put(dpu_kms->suspend_state); 810 } 811 dpu_kms->suspend_state = NULL; 812 } 813 drm_modeset_unlock_all(ddev); 814 815 /* enable hot-plug polling */ 816 drm_kms_helper_poll_enable(ddev); 817 818 DPU_ATRACE_END("kms_pm_resume"); 819 return 0; 820 } 821 822 static void _dpu_kms_set_encoder_mode(struct msm_kms *kms, 823 struct drm_encoder *encoder, 824 bool cmd_mode) 825 { 826 struct msm_display_info info; 827 struct msm_drm_private *priv = encoder->dev->dev_private; 828 int i, rc = 0; 829 830 memset(&info, 0, sizeof(info)); 831 832 info.intf_type = encoder->encoder_type; 833 info.capabilities = cmd_mode ? MSM_DISPLAY_CAP_CMD_MODE : 834 MSM_DISPLAY_CAP_VID_MODE; 835 836 /* TODO: No support for DSI swap */ 837 for (i = 0; i < ARRAY_SIZE(priv->dsi); i++) { 838 if (priv->dsi[i]) { 839 info.h_tile_instance[info.num_of_h_tiles] = i; 840 info.num_of_h_tiles++; 841 } 842 } 843 844 rc = dpu_encoder_setup(encoder->dev, encoder, &info); 845 if (rc) 846 DPU_ERROR("failed to setup DPU encoder %d: rc:%d\n", 847 encoder->base.id, rc); 848 } 849 850 static const struct msm_kms_funcs kms_funcs = { 851 .hw_init = dpu_kms_hw_init, 852 .irq_preinstall = dpu_irq_preinstall, 853 .irq_postinstall = dpu_irq_postinstall, 854 .irq_uninstall = dpu_irq_uninstall, 855 .irq = dpu_irq, 856 .prepare_commit = dpu_kms_prepare_commit, 857 .commit = dpu_kms_commit, 858 .complete_commit = dpu_kms_complete_commit, 859 .wait_for_crtc_commit_done = dpu_kms_wait_for_commit_done, 860 .enable_vblank = dpu_kms_enable_vblank, 861 .disable_vblank = dpu_kms_disable_vblank, 862 .check_modified_format = dpu_format_check_modified_format, 863 .get_format = dpu_get_msm_format, 864 .round_pixclk = dpu_kms_round_pixclk, 865 .pm_suspend = dpu_kms_pm_suspend, 866 .pm_resume = dpu_kms_pm_resume, 867 .destroy = dpu_kms_destroy, 868 .set_encoder_mode = _dpu_kms_set_encoder_mode, 869 #ifdef CONFIG_DEBUG_FS 870 .debugfs_init = dpu_kms_debugfs_init, 871 #endif 872 }; 873 874 /* the caller api needs to turn on clock before calling it */ 875 static inline void _dpu_kms_core_hw_rev_init(struct dpu_kms *dpu_kms) 876 { 877 dpu_kms->core_rev = readl_relaxed(dpu_kms->mmio + 0x0); 878 } 879 880 static int _dpu_kms_mmu_destroy(struct dpu_kms *dpu_kms) 881 { 882 struct msm_mmu *mmu; 883 884 mmu = dpu_kms->base.aspace->mmu; 885 886 mmu->funcs->detach(mmu, (const char **)iommu_ports, 887 ARRAY_SIZE(iommu_ports)); 888 msm_gem_address_space_put(dpu_kms->base.aspace); 889 890 return 0; 891 } 892 893 static int _dpu_kms_mmu_init(struct dpu_kms *dpu_kms) 894 { 895 struct iommu_domain *domain; 896 struct msm_gem_address_space *aspace; 897 int ret; 898 899 domain = iommu_domain_alloc(&platform_bus_type); 900 if (!domain) 901 return 0; 902 903 aspace = msm_gem_address_space_create(dpu_kms->dev->dev, 904 domain, "dpu1"); 905 if (IS_ERR(aspace)) { 906 ret = PTR_ERR(aspace); 907 goto fail; 908 } 909 910 dpu_kms->base.aspace = aspace; 911 912 ret = aspace->mmu->funcs->attach(aspace->mmu, iommu_ports, 913 ARRAY_SIZE(iommu_ports)); 914 if (ret) { 915 DPU_ERROR("failed to attach iommu %d\n", ret); 916 msm_gem_address_space_put(aspace); 917 goto fail; 918 } 919 920 return 0; 921 fail: 922 _dpu_kms_mmu_destroy(dpu_kms); 923 924 return ret; 925 } 926 927 static struct dss_clk *_dpu_kms_get_clk(struct dpu_kms *dpu_kms, 928 char *clock_name) 929 { 930 struct dss_module_power *mp = &dpu_kms->mp; 931 int i; 932 933 for (i = 0; i < mp->num_clk; i++) { 934 if (!strcmp(mp->clk_config[i].clk_name, clock_name)) 935 return &mp->clk_config[i]; 936 } 937 938 return NULL; 939 } 940 941 u64 dpu_kms_get_clk_rate(struct dpu_kms *dpu_kms, char *clock_name) 942 { 943 struct dss_clk *clk; 944 945 clk = _dpu_kms_get_clk(dpu_kms, clock_name); 946 if (!clk) 947 return -EINVAL; 948 949 return clk_get_rate(clk->clk); 950 } 951 952 static void dpu_kms_handle_power_event(u32 event_type, void *usr) 953 { 954 struct dpu_kms *dpu_kms = usr; 955 956 if (!dpu_kms) 957 return; 958 959 if (event_type == DPU_POWER_EVENT_POST_ENABLE) 960 dpu_vbif_init_memtypes(dpu_kms); 961 } 962 963 static int dpu_kms_hw_init(struct msm_kms *kms) 964 { 965 struct dpu_kms *dpu_kms; 966 struct drm_device *dev; 967 struct msm_drm_private *priv; 968 int i, rc = -EINVAL; 969 970 if (!kms) { 971 DPU_ERROR("invalid kms\n"); 972 goto end; 973 } 974 975 dpu_kms = to_dpu_kms(kms); 976 dev = dpu_kms->dev; 977 if (!dev) { 978 DPU_ERROR("invalid device\n"); 979 goto end; 980 } 981 982 rc = dpu_dbg_init(&dpu_kms->pdev->dev); 983 if (rc) { 984 DRM_ERROR("failed to init dpu dbg: %d\n", rc); 985 goto end; 986 } 987 988 priv = dev->dev_private; 989 if (!priv) { 990 DPU_ERROR("invalid private data\n"); 991 goto dbg_destroy; 992 } 993 994 dpu_kms->mmio = msm_ioremap(dpu_kms->pdev, "mdp", "mdp"); 995 if (IS_ERR(dpu_kms->mmio)) { 996 rc = PTR_ERR(dpu_kms->mmio); 997 DPU_ERROR("mdp register memory map failed: %d\n", rc); 998 dpu_kms->mmio = NULL; 999 goto error; 1000 } 1001 DRM_DEBUG("mapped dpu address space @%pK\n", dpu_kms->mmio); 1002 dpu_kms->mmio_len = dpu_iomap_size(dpu_kms->pdev, "mdp"); 1003 1004 dpu_kms->vbif[VBIF_RT] = msm_ioremap(dpu_kms->pdev, "vbif", "vbif"); 1005 if (IS_ERR(dpu_kms->vbif[VBIF_RT])) { 1006 rc = PTR_ERR(dpu_kms->vbif[VBIF_RT]); 1007 DPU_ERROR("vbif register memory map failed: %d\n", rc); 1008 dpu_kms->vbif[VBIF_RT] = NULL; 1009 goto error; 1010 } 1011 dpu_kms->vbif_len[VBIF_RT] = dpu_iomap_size(dpu_kms->pdev, "vbif"); 1012 dpu_kms->vbif[VBIF_NRT] = msm_ioremap(dpu_kms->pdev, "vbif_nrt", "vbif_nrt"); 1013 if (IS_ERR(dpu_kms->vbif[VBIF_NRT])) { 1014 dpu_kms->vbif[VBIF_NRT] = NULL; 1015 DPU_DEBUG("VBIF NRT is not defined"); 1016 } else { 1017 dpu_kms->vbif_len[VBIF_NRT] = dpu_iomap_size(dpu_kms->pdev, 1018 "vbif_nrt"); 1019 } 1020 1021 dpu_kms->reg_dma = msm_ioremap(dpu_kms->pdev, "regdma", "regdma"); 1022 if (IS_ERR(dpu_kms->reg_dma)) { 1023 dpu_kms->reg_dma = NULL; 1024 DPU_DEBUG("REG_DMA is not defined"); 1025 } else { 1026 dpu_kms->reg_dma_len = dpu_iomap_size(dpu_kms->pdev, "regdma"); 1027 } 1028 1029 dpu_kms->core_client = dpu_power_client_create(&dpu_kms->phandle, 1030 "core"); 1031 if (IS_ERR_OR_NULL(dpu_kms->core_client)) { 1032 rc = PTR_ERR(dpu_kms->core_client); 1033 if (!dpu_kms->core_client) 1034 rc = -EINVAL; 1035 DPU_ERROR("dpu power client create failed: %d\n", rc); 1036 dpu_kms->core_client = NULL; 1037 goto error; 1038 } 1039 1040 pm_runtime_get_sync(&dpu_kms->pdev->dev); 1041 1042 _dpu_kms_core_hw_rev_init(dpu_kms); 1043 1044 pr_info("dpu hardware revision:0x%x\n", dpu_kms->core_rev); 1045 1046 dpu_kms->catalog = dpu_hw_catalog_init(dpu_kms->core_rev); 1047 if (IS_ERR_OR_NULL(dpu_kms->catalog)) { 1048 rc = PTR_ERR(dpu_kms->catalog); 1049 if (!dpu_kms->catalog) 1050 rc = -EINVAL; 1051 DPU_ERROR("catalog init failed: %d\n", rc); 1052 dpu_kms->catalog = NULL; 1053 goto power_error; 1054 } 1055 1056 dpu_dbg_init_dbg_buses(dpu_kms->core_rev); 1057 1058 /* 1059 * Now we need to read the HW catalog and initialize resources such as 1060 * clocks, regulators, GDSC/MMAGIC, ioremap the register ranges etc 1061 */ 1062 rc = _dpu_kms_mmu_init(dpu_kms); 1063 if (rc) { 1064 DPU_ERROR("dpu_kms_mmu_init failed: %d\n", rc); 1065 goto power_error; 1066 } 1067 1068 rc = dpu_rm_init(&dpu_kms->rm, dpu_kms->catalog, dpu_kms->mmio, 1069 dpu_kms->dev); 1070 if (rc) { 1071 DPU_ERROR("rm init failed: %d\n", rc); 1072 goto power_error; 1073 } 1074 1075 dpu_kms->rm_init = true; 1076 1077 dpu_kms->hw_mdp = dpu_rm_get_mdp(&dpu_kms->rm); 1078 if (IS_ERR_OR_NULL(dpu_kms->hw_mdp)) { 1079 rc = PTR_ERR(dpu_kms->hw_mdp); 1080 if (!dpu_kms->hw_mdp) 1081 rc = -EINVAL; 1082 DPU_ERROR("failed to get hw_mdp: %d\n", rc); 1083 dpu_kms->hw_mdp = NULL; 1084 goto power_error; 1085 } 1086 1087 for (i = 0; i < dpu_kms->catalog->vbif_count; i++) { 1088 u32 vbif_idx = dpu_kms->catalog->vbif[i].id; 1089 1090 dpu_kms->hw_vbif[i] = dpu_hw_vbif_init(vbif_idx, 1091 dpu_kms->vbif[vbif_idx], dpu_kms->catalog); 1092 if (IS_ERR_OR_NULL(dpu_kms->hw_vbif[vbif_idx])) { 1093 rc = PTR_ERR(dpu_kms->hw_vbif[vbif_idx]); 1094 if (!dpu_kms->hw_vbif[vbif_idx]) 1095 rc = -EINVAL; 1096 DPU_ERROR("failed to init vbif %d: %d\n", vbif_idx, rc); 1097 dpu_kms->hw_vbif[vbif_idx] = NULL; 1098 goto power_error; 1099 } 1100 } 1101 1102 rc = dpu_core_perf_init(&dpu_kms->perf, dev, dpu_kms->catalog, 1103 &dpu_kms->phandle, 1104 _dpu_kms_get_clk(dpu_kms, "core")); 1105 if (rc) { 1106 DPU_ERROR("failed to init perf %d\n", rc); 1107 goto perf_err; 1108 } 1109 1110 dpu_kms->hw_intr = dpu_hw_intr_init(dpu_kms->mmio, dpu_kms->catalog); 1111 if (IS_ERR_OR_NULL(dpu_kms->hw_intr)) { 1112 rc = PTR_ERR(dpu_kms->hw_intr); 1113 DPU_ERROR("hw_intr init failed: %d\n", rc); 1114 dpu_kms->hw_intr = NULL; 1115 goto hw_intr_init_err; 1116 } 1117 1118 /* 1119 * _dpu_kms_drm_obj_init should create the DRM related objects 1120 * i.e. CRTCs, planes, encoders, connectors and so forth 1121 */ 1122 rc = _dpu_kms_drm_obj_init(dpu_kms); 1123 if (rc) { 1124 DPU_ERROR("modeset init failed: %d\n", rc); 1125 goto drm_obj_init_err; 1126 } 1127 1128 dev->mode_config.min_width = 0; 1129 dev->mode_config.min_height = 0; 1130 1131 /* 1132 * max crtc width is equal to the max mixer width * 2 and max height is 1133 * is 4K 1134 */ 1135 dev->mode_config.max_width = 1136 dpu_kms->catalog->caps->max_mixer_width * 2; 1137 dev->mode_config.max_height = 4096; 1138 1139 /* 1140 * Support format modifiers for compression etc. 1141 */ 1142 dev->mode_config.allow_fb_modifiers = true; 1143 1144 /* 1145 * Handle (re)initializations during power enable 1146 */ 1147 dpu_kms_handle_power_event(DPU_POWER_EVENT_POST_ENABLE, dpu_kms); 1148 dpu_kms->power_event = dpu_power_handle_register_event( 1149 &dpu_kms->phandle, 1150 DPU_POWER_EVENT_POST_ENABLE, 1151 dpu_kms_handle_power_event, dpu_kms, "kms"); 1152 1153 pm_runtime_put_sync(&dpu_kms->pdev->dev); 1154 1155 return 0; 1156 1157 drm_obj_init_err: 1158 dpu_core_perf_destroy(&dpu_kms->perf); 1159 hw_intr_init_err: 1160 perf_err: 1161 power_error: 1162 pm_runtime_put_sync(&dpu_kms->pdev->dev); 1163 error: 1164 _dpu_kms_hw_destroy(dpu_kms); 1165 dbg_destroy: 1166 dpu_dbg_destroy(); 1167 end: 1168 return rc; 1169 } 1170 1171 struct msm_kms *dpu_kms_init(struct drm_device *dev) 1172 { 1173 struct msm_drm_private *priv; 1174 struct dpu_kms *dpu_kms; 1175 int irq; 1176 1177 if (!dev || !dev->dev_private) { 1178 DPU_ERROR("drm device node invalid\n"); 1179 return ERR_PTR(-EINVAL); 1180 } 1181 1182 priv = dev->dev_private; 1183 dpu_kms = to_dpu_kms(priv->kms); 1184 1185 irq = irq_of_parse_and_map(dpu_kms->pdev->dev.of_node, 0); 1186 if (irq < 0) { 1187 DPU_ERROR("failed to get irq: %d\n", irq); 1188 return ERR_PTR(irq); 1189 } 1190 dpu_kms->base.irq = irq; 1191 1192 return &dpu_kms->base; 1193 } 1194 1195 static int dpu_bind(struct device *dev, struct device *master, void *data) 1196 { 1197 struct drm_device *ddev = dev_get_drvdata(master); 1198 struct platform_device *pdev = to_platform_device(dev); 1199 struct msm_drm_private *priv = ddev->dev_private; 1200 struct dpu_kms *dpu_kms; 1201 struct dss_module_power *mp; 1202 int ret = 0; 1203 1204 dpu_kms = devm_kzalloc(&pdev->dev, sizeof(*dpu_kms), GFP_KERNEL); 1205 if (!dpu_kms) 1206 return -ENOMEM; 1207 1208 mp = &dpu_kms->mp; 1209 ret = msm_dss_parse_clock(pdev, mp); 1210 if (ret) { 1211 DPU_ERROR("failed to parse clocks, ret=%d\n", ret); 1212 return ret; 1213 } 1214 1215 dpu_power_resource_init(pdev, &dpu_kms->phandle); 1216 1217 platform_set_drvdata(pdev, dpu_kms); 1218 1219 msm_kms_init(&dpu_kms->base, &kms_funcs); 1220 dpu_kms->dev = ddev; 1221 dpu_kms->pdev = pdev; 1222 1223 pm_runtime_enable(&pdev->dev); 1224 dpu_kms->rpm_enabled = true; 1225 1226 priv->kms = &dpu_kms->base; 1227 return ret; 1228 } 1229 1230 static void dpu_unbind(struct device *dev, struct device *master, void *data) 1231 { 1232 struct platform_device *pdev = to_platform_device(dev); 1233 struct dpu_kms *dpu_kms = platform_get_drvdata(pdev); 1234 struct dss_module_power *mp = &dpu_kms->mp; 1235 1236 dpu_power_resource_deinit(pdev, &dpu_kms->phandle); 1237 msm_dss_put_clk(mp->clk_config, mp->num_clk); 1238 devm_kfree(&pdev->dev, mp->clk_config); 1239 mp->num_clk = 0; 1240 1241 if (dpu_kms->rpm_enabled) 1242 pm_runtime_disable(&pdev->dev); 1243 } 1244 1245 static const struct component_ops dpu_ops = { 1246 .bind = dpu_bind, 1247 .unbind = dpu_unbind, 1248 }; 1249 1250 static int dpu_dev_probe(struct platform_device *pdev) 1251 { 1252 return component_add(&pdev->dev, &dpu_ops); 1253 } 1254 1255 static int dpu_dev_remove(struct platform_device *pdev) 1256 { 1257 component_del(&pdev->dev, &dpu_ops); 1258 return 0; 1259 } 1260 1261 static int __maybe_unused dpu_runtime_suspend(struct device *dev) 1262 { 1263 int rc = -1; 1264 struct platform_device *pdev = to_platform_device(dev); 1265 struct dpu_kms *dpu_kms = platform_get_drvdata(pdev); 1266 struct drm_device *ddev; 1267 struct dss_module_power *mp = &dpu_kms->mp; 1268 1269 ddev = dpu_kms->dev; 1270 if (!ddev) { 1271 DPU_ERROR("invalid drm_device\n"); 1272 goto exit; 1273 } 1274 1275 rc = dpu_power_resource_enable(&dpu_kms->phandle, 1276 dpu_kms->core_client, false); 1277 if (rc) 1278 DPU_ERROR("resource disable failed: %d\n", rc); 1279 1280 rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, false); 1281 if (rc) 1282 DPU_ERROR("clock disable failed rc:%d\n", rc); 1283 1284 exit: 1285 return rc; 1286 } 1287 1288 static int __maybe_unused dpu_runtime_resume(struct device *dev) 1289 { 1290 int rc = -1; 1291 struct platform_device *pdev = to_platform_device(dev); 1292 struct dpu_kms *dpu_kms = platform_get_drvdata(pdev); 1293 struct drm_device *ddev; 1294 struct dss_module_power *mp = &dpu_kms->mp; 1295 1296 ddev = dpu_kms->dev; 1297 if (!ddev) { 1298 DPU_ERROR("invalid drm_device\n"); 1299 goto exit; 1300 } 1301 1302 rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, true); 1303 if (rc) { 1304 DPU_ERROR("clock enable failed rc:%d\n", rc); 1305 goto exit; 1306 } 1307 1308 rc = dpu_power_resource_enable(&dpu_kms->phandle, 1309 dpu_kms->core_client, true); 1310 if (rc) 1311 DPU_ERROR("resource enable failed: %d\n", rc); 1312 1313 exit: 1314 return rc; 1315 } 1316 1317 static const struct dev_pm_ops dpu_pm_ops = { 1318 SET_RUNTIME_PM_OPS(dpu_runtime_suspend, dpu_runtime_resume, NULL) 1319 }; 1320 1321 static const struct of_device_id dpu_dt_match[] = { 1322 { .compatible = "qcom,sdm845-dpu", }, 1323 {} 1324 }; 1325 MODULE_DEVICE_TABLE(of, dpu_dt_match); 1326 1327 static struct platform_driver dpu_driver = { 1328 .probe = dpu_dev_probe, 1329 .remove = dpu_dev_remove, 1330 .driver = { 1331 .name = "msm_dpu", 1332 .of_match_table = dpu_dt_match, 1333 .pm = &dpu_pm_ops, 1334 }, 1335 }; 1336 1337 void __init msm_dpu_register(void) 1338 { 1339 platform_driver_register(&dpu_driver); 1340 } 1341 1342 void __exit msm_dpu_unregister(void) 1343 { 1344 platform_driver_unregister(&dpu_driver); 1345 } 1346