1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ 9 10 #include <linux/debugfs.h> 11 #include <linux/dma-buf.h> 12 #include <linux/of_irq.h> 13 #include <linux/pm_opp.h> 14 15 #include <drm/drm_crtc.h> 16 #include <drm/drm_file.h> 17 #include <drm/drm_vblank.h> 18 19 #include "msm_drv.h" 20 #include "msm_mmu.h" 21 #include "msm_gem.h" 22 #include "disp/msm_disp_snapshot.h" 23 24 #include "dpu_core_irq.h" 25 #include "dpu_crtc.h" 26 #include "dpu_encoder.h" 27 #include "dpu_formats.h" 28 #include "dpu_hw_vbif.h" 29 #include "dpu_kms.h" 30 #include "dpu_plane.h" 31 #include "dpu_vbif.h" 32 33 #define CREATE_TRACE_POINTS 34 #include "dpu_trace.h" 35 36 /* 37 * To enable overall DRM driver logging 38 * # echo 0x2 > /sys/module/drm/parameters/debug 39 * 40 * To enable DRM driver h/w logging 41 * # echo <mask> > /sys/kernel/debug/dri/0/debug/hw_log_mask 42 * 43 * See dpu_hw_mdss.h for h/w logging mask definitions (search for DPU_DBG_MASK_) 44 */ 45 #define DPU_DEBUGFS_DIR "msm_dpu" 46 #define DPU_DEBUGFS_HWMASKNAME "hw_log_mask" 47 48 #define MIN_IB_BW 400000000ULL /* Min ib vote 400MB */ 49 50 static int dpu_kms_hw_init(struct msm_kms *kms); 51 static void _dpu_kms_mmu_destroy(struct dpu_kms *dpu_kms); 52 53 #ifdef CONFIG_DEBUG_FS 54 static int _dpu_danger_signal_status(struct seq_file *s, 55 bool danger_status) 56 { 57 struct dpu_kms *kms = (struct dpu_kms *)s->private; 58 struct dpu_danger_safe_status status; 59 int i; 60 61 if (!kms->hw_mdp) { 62 DPU_ERROR("invalid arg(s)\n"); 63 return 0; 64 } 65 66 memset(&status, 0, sizeof(struct dpu_danger_safe_status)); 67 68 pm_runtime_get_sync(&kms->pdev->dev); 69 if (danger_status) { 70 seq_puts(s, "\nDanger signal status:\n"); 71 if (kms->hw_mdp->ops.get_danger_status) 72 kms->hw_mdp->ops.get_danger_status(kms->hw_mdp, 73 &status); 74 } else { 75 seq_puts(s, "\nSafe signal status:\n"); 76 if (kms->hw_mdp->ops.get_safe_status) 77 kms->hw_mdp->ops.get_safe_status(kms->hw_mdp, 78 &status); 79 } 80 pm_runtime_put_sync(&kms->pdev->dev); 81 82 seq_printf(s, "MDP : 0x%x\n", status.mdp); 83 84 for (i = SSPP_VIG0; i < SSPP_MAX; i++) 85 seq_printf(s, "SSPP%d : 0x%x \n", i - SSPP_VIG0, 86 status.sspp[i]); 87 seq_puts(s, "\n"); 88 89 return 0; 90 } 91 92 static int dpu_debugfs_danger_stats_show(struct seq_file *s, void *v) 93 { 94 return _dpu_danger_signal_status(s, true); 95 } 96 DEFINE_SHOW_ATTRIBUTE(dpu_debugfs_danger_stats); 97 98 static int dpu_debugfs_safe_stats_show(struct seq_file *s, void *v) 99 { 100 return _dpu_danger_signal_status(s, false); 101 } 102 DEFINE_SHOW_ATTRIBUTE(dpu_debugfs_safe_stats); 103 104 static ssize_t _dpu_plane_danger_read(struct file *file, 105 char __user *buff, size_t count, loff_t *ppos) 106 { 107 struct dpu_kms *kms = file->private_data; 108 int len; 109 char buf[40]; 110 111 len = scnprintf(buf, sizeof(buf), "%d\n", !kms->has_danger_ctrl); 112 113 return simple_read_from_buffer(buff, count, ppos, buf, len); 114 } 115 116 static void _dpu_plane_set_danger_state(struct dpu_kms *kms, bool enable) 117 { 118 struct drm_plane *plane; 119 120 drm_for_each_plane(plane, kms->dev) { 121 if (plane->fb && plane->state) { 122 dpu_plane_danger_signal_ctrl(plane, enable); 123 DPU_DEBUG("plane:%d img:%dx%d ", 124 plane->base.id, plane->fb->width, 125 plane->fb->height); 126 DPU_DEBUG("src[%d,%d,%d,%d] dst[%d,%d,%d,%d]\n", 127 plane->state->src_x >> 16, 128 plane->state->src_y >> 16, 129 plane->state->src_w >> 16, 130 plane->state->src_h >> 16, 131 plane->state->crtc_x, plane->state->crtc_y, 132 plane->state->crtc_w, plane->state->crtc_h); 133 } else { 134 DPU_DEBUG("Inactive plane:%d\n", plane->base.id); 135 } 136 } 137 } 138 139 static ssize_t _dpu_plane_danger_write(struct file *file, 140 const char __user *user_buf, size_t count, loff_t *ppos) 141 { 142 struct dpu_kms *kms = file->private_data; 143 int disable_panic; 144 int ret; 145 146 ret = kstrtouint_from_user(user_buf, count, 0, &disable_panic); 147 if (ret) 148 return ret; 149 150 if (disable_panic) { 151 /* Disable panic signal for all active pipes */ 152 DPU_DEBUG("Disabling danger:\n"); 153 _dpu_plane_set_danger_state(kms, false); 154 kms->has_danger_ctrl = false; 155 } else { 156 /* Enable panic signal for all active pipes */ 157 DPU_DEBUG("Enabling danger:\n"); 158 kms->has_danger_ctrl = true; 159 _dpu_plane_set_danger_state(kms, true); 160 } 161 162 return count; 163 } 164 165 static const struct file_operations dpu_plane_danger_enable = { 166 .open = simple_open, 167 .read = _dpu_plane_danger_read, 168 .write = _dpu_plane_danger_write, 169 }; 170 171 static void dpu_debugfs_danger_init(struct dpu_kms *dpu_kms, 172 struct dentry *parent) 173 { 174 struct dentry *entry = debugfs_create_dir("danger", parent); 175 176 debugfs_create_file("danger_status", 0600, entry, 177 dpu_kms, &dpu_debugfs_danger_stats_fops); 178 debugfs_create_file("safe_status", 0600, entry, 179 dpu_kms, &dpu_debugfs_safe_stats_fops); 180 debugfs_create_file("disable_danger", 0600, entry, 181 dpu_kms, &dpu_plane_danger_enable); 182 183 } 184 185 /* 186 * Companion structure for dpu_debugfs_create_regset32. 187 */ 188 struct dpu_debugfs_regset32 { 189 uint32_t offset; 190 uint32_t blk_len; 191 struct dpu_kms *dpu_kms; 192 }; 193 194 static int _dpu_debugfs_show_regset32(struct seq_file *s, void *data) 195 { 196 struct dpu_debugfs_regset32 *regset = s->private; 197 struct dpu_kms *dpu_kms = regset->dpu_kms; 198 void __iomem *base; 199 uint32_t i, addr; 200 201 if (!dpu_kms->mmio) 202 return 0; 203 204 base = dpu_kms->mmio + regset->offset; 205 206 /* insert padding spaces, if needed */ 207 if (regset->offset & 0xF) { 208 seq_printf(s, "[%x]", regset->offset & ~0xF); 209 for (i = 0; i < (regset->offset & 0xF); i += 4) 210 seq_puts(s, " "); 211 } 212 213 pm_runtime_get_sync(&dpu_kms->pdev->dev); 214 215 /* main register output */ 216 for (i = 0; i < regset->blk_len; i += 4) { 217 addr = regset->offset + i; 218 if ((addr & 0xF) == 0x0) 219 seq_printf(s, i ? "\n[%x]" : "[%x]", addr); 220 seq_printf(s, " %08x", readl_relaxed(base + i)); 221 } 222 seq_puts(s, "\n"); 223 pm_runtime_put_sync(&dpu_kms->pdev->dev); 224 225 return 0; 226 } 227 228 static int dpu_debugfs_open_regset32(struct inode *inode, 229 struct file *file) 230 { 231 return single_open(file, _dpu_debugfs_show_regset32, inode->i_private); 232 } 233 234 static const struct file_operations dpu_fops_regset32 = { 235 .open = dpu_debugfs_open_regset32, 236 .read = seq_read, 237 .llseek = seq_lseek, 238 .release = single_release, 239 }; 240 241 void dpu_debugfs_create_regset32(const char *name, umode_t mode, 242 void *parent, 243 uint32_t offset, uint32_t length, struct dpu_kms *dpu_kms) 244 { 245 struct dpu_debugfs_regset32 *regset; 246 247 if (WARN_ON(!name || !dpu_kms || !length)) 248 return; 249 250 regset = devm_kzalloc(&dpu_kms->pdev->dev, sizeof(*regset), GFP_KERNEL); 251 if (!regset) 252 return; 253 254 /* make sure offset is a multiple of 4 */ 255 regset->offset = round_down(offset, 4); 256 regset->blk_len = length; 257 regset->dpu_kms = dpu_kms; 258 259 debugfs_create_file(name, mode, parent, regset, &dpu_fops_regset32); 260 } 261 262 static int dpu_kms_debugfs_init(struct msm_kms *kms, struct drm_minor *minor) 263 { 264 struct dpu_kms *dpu_kms = to_dpu_kms(kms); 265 void *p = dpu_hw_util_get_log_mask_ptr(); 266 struct dentry *entry; 267 struct drm_device *dev; 268 struct msm_drm_private *priv; 269 int i; 270 271 if (!p) 272 return -EINVAL; 273 274 /* Only create a set of debugfs for the primary node, ignore render nodes */ 275 if (minor->type != DRM_MINOR_PRIMARY) 276 return 0; 277 278 dev = dpu_kms->dev; 279 priv = dev->dev_private; 280 281 entry = debugfs_create_dir("debug", minor->debugfs_root); 282 283 debugfs_create_x32(DPU_DEBUGFS_HWMASKNAME, 0600, entry, p); 284 285 dpu_debugfs_danger_init(dpu_kms, entry); 286 dpu_debugfs_vbif_init(dpu_kms, entry); 287 dpu_debugfs_core_irq_init(dpu_kms, entry); 288 dpu_debugfs_sspp_init(dpu_kms, entry); 289 290 for (i = 0; i < ARRAY_SIZE(priv->dp); i++) { 291 if (priv->dp[i]) 292 msm_dp_debugfs_init(priv->dp[i], minor); 293 } 294 295 return dpu_core_perf_debugfs_init(dpu_kms, entry); 296 } 297 #endif 298 299 /* Global/shared object state funcs */ 300 301 /* 302 * This is a helper that returns the private state currently in operation. 303 * Note that this would return the "old_state" if called in the atomic check 304 * path, and the "new_state" after the atomic swap has been done. 305 */ 306 struct dpu_global_state * 307 dpu_kms_get_existing_global_state(struct dpu_kms *dpu_kms) 308 { 309 return to_dpu_global_state(dpu_kms->global_state.state); 310 } 311 312 /* 313 * This acquires the modeset lock set aside for global state, creates 314 * a new duplicated private object state. 315 */ 316 struct dpu_global_state *dpu_kms_get_global_state(struct drm_atomic_state *s) 317 { 318 struct msm_drm_private *priv = s->dev->dev_private; 319 struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms); 320 struct drm_private_state *priv_state; 321 int ret; 322 323 ret = drm_modeset_lock(&dpu_kms->global_state_lock, s->acquire_ctx); 324 if (ret) 325 return ERR_PTR(ret); 326 327 priv_state = drm_atomic_get_private_obj_state(s, 328 &dpu_kms->global_state); 329 if (IS_ERR(priv_state)) 330 return ERR_CAST(priv_state); 331 332 return to_dpu_global_state(priv_state); 333 } 334 335 static struct drm_private_state * 336 dpu_kms_global_duplicate_state(struct drm_private_obj *obj) 337 { 338 struct dpu_global_state *state; 339 340 state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL); 341 if (!state) 342 return NULL; 343 344 __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base); 345 346 return &state->base; 347 } 348 349 static void dpu_kms_global_destroy_state(struct drm_private_obj *obj, 350 struct drm_private_state *state) 351 { 352 struct dpu_global_state *dpu_state = to_dpu_global_state(state); 353 354 kfree(dpu_state); 355 } 356 357 static const struct drm_private_state_funcs dpu_kms_global_state_funcs = { 358 .atomic_duplicate_state = dpu_kms_global_duplicate_state, 359 .atomic_destroy_state = dpu_kms_global_destroy_state, 360 }; 361 362 static int dpu_kms_global_obj_init(struct dpu_kms *dpu_kms) 363 { 364 struct dpu_global_state *state; 365 366 drm_modeset_lock_init(&dpu_kms->global_state_lock); 367 368 state = kzalloc(sizeof(*state), GFP_KERNEL); 369 if (!state) 370 return -ENOMEM; 371 372 drm_atomic_private_obj_init(dpu_kms->dev, &dpu_kms->global_state, 373 &state->base, 374 &dpu_kms_global_state_funcs); 375 return 0; 376 } 377 378 static int dpu_kms_parse_data_bus_icc_path(struct dpu_kms *dpu_kms) 379 { 380 struct icc_path *path0; 381 struct icc_path *path1; 382 struct drm_device *dev = dpu_kms->dev; 383 384 path0 = of_icc_get(dev->dev, "mdp0-mem"); 385 path1 = of_icc_get(dev->dev, "mdp1-mem"); 386 387 if (IS_ERR_OR_NULL(path0)) 388 return PTR_ERR_OR_ZERO(path0); 389 390 dpu_kms->path[0] = path0; 391 dpu_kms->num_paths = 1; 392 393 if (!IS_ERR_OR_NULL(path1)) { 394 dpu_kms->path[1] = path1; 395 dpu_kms->num_paths++; 396 } 397 return 0; 398 } 399 400 static int dpu_kms_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc) 401 { 402 return dpu_crtc_vblank(crtc, true); 403 } 404 405 static void dpu_kms_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc) 406 { 407 dpu_crtc_vblank(crtc, false); 408 } 409 410 static void dpu_kms_enable_commit(struct msm_kms *kms) 411 { 412 struct dpu_kms *dpu_kms = to_dpu_kms(kms); 413 pm_runtime_get_sync(&dpu_kms->pdev->dev); 414 } 415 416 static void dpu_kms_disable_commit(struct msm_kms *kms) 417 { 418 struct dpu_kms *dpu_kms = to_dpu_kms(kms); 419 pm_runtime_put_sync(&dpu_kms->pdev->dev); 420 } 421 422 static ktime_t dpu_kms_vsync_time(struct msm_kms *kms, struct drm_crtc *crtc) 423 { 424 struct drm_encoder *encoder; 425 426 drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) { 427 ktime_t vsync_time; 428 429 if (dpu_encoder_vsync_time(encoder, &vsync_time) == 0) 430 return vsync_time; 431 } 432 433 return ktime_get(); 434 } 435 436 static void dpu_kms_prepare_commit(struct msm_kms *kms, 437 struct drm_atomic_state *state) 438 { 439 struct drm_crtc *crtc; 440 struct drm_crtc_state *crtc_state; 441 struct drm_encoder *encoder; 442 int i; 443 444 if (!kms) 445 return; 446 447 /* Call prepare_commit for all affected encoders */ 448 for_each_new_crtc_in_state(state, crtc, crtc_state, i) { 449 drm_for_each_encoder_mask(encoder, crtc->dev, 450 crtc_state->encoder_mask) { 451 dpu_encoder_prepare_commit(encoder); 452 } 453 } 454 } 455 456 static void dpu_kms_flush_commit(struct msm_kms *kms, unsigned crtc_mask) 457 { 458 struct dpu_kms *dpu_kms = to_dpu_kms(kms); 459 struct drm_crtc *crtc; 460 461 for_each_crtc_mask(dpu_kms->dev, crtc, crtc_mask) { 462 if (!crtc->state->active) 463 continue; 464 465 trace_dpu_kms_commit(DRMID(crtc)); 466 dpu_crtc_commit_kickoff(crtc); 467 } 468 } 469 470 static void dpu_kms_complete_commit(struct msm_kms *kms, unsigned crtc_mask) 471 { 472 struct dpu_kms *dpu_kms = to_dpu_kms(kms); 473 struct drm_crtc *crtc; 474 475 DPU_ATRACE_BEGIN("kms_complete_commit"); 476 477 for_each_crtc_mask(dpu_kms->dev, crtc, crtc_mask) 478 dpu_crtc_complete_commit(crtc); 479 480 DPU_ATRACE_END("kms_complete_commit"); 481 } 482 483 static void dpu_kms_wait_for_commit_done(struct msm_kms *kms, 484 struct drm_crtc *crtc) 485 { 486 struct drm_encoder *encoder; 487 struct drm_device *dev; 488 int ret; 489 490 if (!kms || !crtc || !crtc->state) { 491 DPU_ERROR("invalid params\n"); 492 return; 493 } 494 495 dev = crtc->dev; 496 497 if (!crtc->state->enable) { 498 DPU_DEBUG("[crtc:%d] not enable\n", crtc->base.id); 499 return; 500 } 501 502 if (!crtc->state->active) { 503 DPU_DEBUG("[crtc:%d] not active\n", crtc->base.id); 504 return; 505 } 506 507 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 508 if (encoder->crtc != crtc) 509 continue; 510 /* 511 * Wait for post-flush if necessary to delay before 512 * plane_cleanup. For example, wait for vsync in case of video 513 * mode panels. This may be a no-op for command mode panels. 514 */ 515 trace_dpu_kms_wait_for_commit_done(DRMID(crtc)); 516 ret = dpu_encoder_wait_for_event(encoder, MSM_ENC_COMMIT_DONE); 517 if (ret && ret != -EWOULDBLOCK) { 518 DPU_ERROR("wait for commit done returned %d\n", ret); 519 break; 520 } 521 } 522 } 523 524 static void dpu_kms_wait_flush(struct msm_kms *kms, unsigned crtc_mask) 525 { 526 struct dpu_kms *dpu_kms = to_dpu_kms(kms); 527 struct drm_crtc *crtc; 528 529 for_each_crtc_mask(dpu_kms->dev, crtc, crtc_mask) 530 dpu_kms_wait_for_commit_done(kms, crtc); 531 } 532 533 static int _dpu_kms_initialize_dsi(struct drm_device *dev, 534 struct msm_drm_private *priv, 535 struct dpu_kms *dpu_kms) 536 { 537 struct drm_encoder *encoder = NULL; 538 struct msm_display_info info; 539 int i, rc = 0; 540 541 if (!(priv->dsi[0] || priv->dsi[1])) 542 return rc; 543 544 /* 545 * We support following confiurations: 546 * - Single DSI host (dsi0 or dsi1) 547 * - Two independent DSI hosts 548 * - Bonded DSI0 and DSI1 hosts 549 * 550 * TODO: Support swapping DSI0 and DSI1 in the bonded setup. 551 */ 552 for (i = 0; i < ARRAY_SIZE(priv->dsi); i++) { 553 int other = (i + 1) % 2; 554 555 if (!priv->dsi[i]) 556 continue; 557 558 if (msm_dsi_is_bonded_dsi(priv->dsi[i]) && 559 !msm_dsi_is_master_dsi(priv->dsi[i])) 560 continue; 561 562 encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_DSI); 563 if (IS_ERR(encoder)) { 564 DPU_ERROR("encoder init failed for dsi display\n"); 565 return PTR_ERR(encoder); 566 } 567 568 priv->encoders[priv->num_encoders++] = encoder; 569 570 memset(&info, 0, sizeof(info)); 571 info.intf_type = encoder->encoder_type; 572 573 rc = msm_dsi_modeset_init(priv->dsi[i], dev, encoder); 574 if (rc) { 575 DPU_ERROR("modeset_init failed for dsi[%d], rc = %d\n", 576 i, rc); 577 break; 578 } 579 580 info.h_tile_instance[info.num_of_h_tiles++] = i; 581 info.capabilities = msm_dsi_is_cmd_mode(priv->dsi[i]) ? 582 MSM_DISPLAY_CAP_CMD_MODE : 583 MSM_DISPLAY_CAP_VID_MODE; 584 585 if (msm_dsi_is_bonded_dsi(priv->dsi[i]) && priv->dsi[other]) { 586 rc = msm_dsi_modeset_init(priv->dsi[other], dev, encoder); 587 if (rc) { 588 DPU_ERROR("modeset_init failed for dsi[%d], rc = %d\n", 589 other, rc); 590 break; 591 } 592 593 info.h_tile_instance[info.num_of_h_tiles++] = other; 594 } 595 596 rc = dpu_encoder_setup(dev, encoder, &info); 597 if (rc) 598 DPU_ERROR("failed to setup DPU encoder %d: rc:%d\n", 599 encoder->base.id, rc); 600 } 601 602 return rc; 603 } 604 605 static int _dpu_kms_initialize_displayport(struct drm_device *dev, 606 struct msm_drm_private *priv, 607 struct dpu_kms *dpu_kms) 608 { 609 struct drm_encoder *encoder = NULL; 610 struct msm_display_info info; 611 int rc; 612 int i; 613 614 for (i = 0; i < ARRAY_SIZE(priv->dp); i++) { 615 if (!priv->dp[i]) 616 continue; 617 618 encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_TMDS); 619 if (IS_ERR(encoder)) { 620 DPU_ERROR("encoder init failed for dsi display\n"); 621 return PTR_ERR(encoder); 622 } 623 624 memset(&info, 0, sizeof(info)); 625 rc = msm_dp_modeset_init(priv->dp[i], dev, encoder); 626 if (rc) { 627 DPU_ERROR("modeset_init failed for DP, rc = %d\n", rc); 628 drm_encoder_cleanup(encoder); 629 return rc; 630 } 631 632 priv->encoders[priv->num_encoders++] = encoder; 633 634 info.num_of_h_tiles = 1; 635 info.h_tile_instance[0] = i; 636 info.capabilities = MSM_DISPLAY_CAP_VID_MODE; 637 info.intf_type = encoder->encoder_type; 638 rc = dpu_encoder_setup(dev, encoder, &info); 639 if (rc) { 640 DPU_ERROR("failed to setup DPU encoder %d: rc:%d\n", 641 encoder->base.id, rc); 642 return rc; 643 } 644 } 645 646 return 0; 647 } 648 649 /** 650 * _dpu_kms_setup_displays - create encoders, bridges and connectors 651 * for underlying displays 652 * @dev: Pointer to drm device structure 653 * @priv: Pointer to private drm device data 654 * @dpu_kms: Pointer to dpu kms structure 655 * Returns: Zero on success 656 */ 657 static int _dpu_kms_setup_displays(struct drm_device *dev, 658 struct msm_drm_private *priv, 659 struct dpu_kms *dpu_kms) 660 { 661 int rc = 0; 662 663 rc = _dpu_kms_initialize_dsi(dev, priv, dpu_kms); 664 if (rc) { 665 DPU_ERROR("initialize_dsi failed, rc = %d\n", rc); 666 return rc; 667 } 668 669 rc = _dpu_kms_initialize_displayport(dev, priv, dpu_kms); 670 if (rc) { 671 DPU_ERROR("initialize_DP failed, rc = %d\n", rc); 672 return rc; 673 } 674 675 return rc; 676 } 677 678 static void _dpu_kms_drm_obj_destroy(struct dpu_kms *dpu_kms) 679 { 680 struct msm_drm_private *priv; 681 int i; 682 683 priv = dpu_kms->dev->dev_private; 684 685 for (i = 0; i < priv->num_crtcs; i++) 686 priv->crtcs[i]->funcs->destroy(priv->crtcs[i]); 687 priv->num_crtcs = 0; 688 689 for (i = 0; i < priv->num_planes; i++) 690 priv->planes[i]->funcs->destroy(priv->planes[i]); 691 priv->num_planes = 0; 692 693 for (i = 0; i < priv->num_connectors; i++) 694 priv->connectors[i]->funcs->destroy(priv->connectors[i]); 695 priv->num_connectors = 0; 696 697 for (i = 0; i < priv->num_encoders; i++) 698 priv->encoders[i]->funcs->destroy(priv->encoders[i]); 699 priv->num_encoders = 0; 700 } 701 702 static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms) 703 { 704 struct drm_device *dev; 705 struct drm_plane *primary_planes[MAX_PLANES], *plane; 706 struct drm_plane *cursor_planes[MAX_PLANES] = { NULL }; 707 struct drm_crtc *crtc; 708 709 struct msm_drm_private *priv; 710 struct dpu_mdss_cfg *catalog; 711 712 int primary_planes_idx = 0, cursor_planes_idx = 0, i, ret; 713 int max_crtc_count; 714 dev = dpu_kms->dev; 715 priv = dev->dev_private; 716 catalog = dpu_kms->catalog; 717 718 /* 719 * Create encoder and query display drivers to create 720 * bridges and connectors 721 */ 722 ret = _dpu_kms_setup_displays(dev, priv, dpu_kms); 723 if (ret) 724 goto fail; 725 726 max_crtc_count = min(catalog->mixer_count, priv->num_encoders); 727 728 /* Create the planes, keeping track of one primary/cursor per crtc */ 729 for (i = 0; i < catalog->sspp_count; i++) { 730 enum drm_plane_type type; 731 732 if ((catalog->sspp[i].features & BIT(DPU_SSPP_CURSOR)) 733 && cursor_planes_idx < max_crtc_count) 734 type = DRM_PLANE_TYPE_CURSOR; 735 else if (primary_planes_idx < max_crtc_count) 736 type = DRM_PLANE_TYPE_PRIMARY; 737 else 738 type = DRM_PLANE_TYPE_OVERLAY; 739 740 DPU_DEBUG("Create plane type %d with features %lx (cur %lx)\n", 741 type, catalog->sspp[i].features, 742 catalog->sspp[i].features & BIT(DPU_SSPP_CURSOR)); 743 744 plane = dpu_plane_init(dev, catalog->sspp[i].id, type, 745 (1UL << max_crtc_count) - 1, 0); 746 if (IS_ERR(plane)) { 747 DPU_ERROR("dpu_plane_init failed\n"); 748 ret = PTR_ERR(plane); 749 goto fail; 750 } 751 priv->planes[priv->num_planes++] = plane; 752 753 if (type == DRM_PLANE_TYPE_CURSOR) 754 cursor_planes[cursor_planes_idx++] = plane; 755 else if (type == DRM_PLANE_TYPE_PRIMARY) 756 primary_planes[primary_planes_idx++] = plane; 757 } 758 759 max_crtc_count = min(max_crtc_count, primary_planes_idx); 760 761 /* Create one CRTC per encoder */ 762 for (i = 0; i < max_crtc_count; i++) { 763 crtc = dpu_crtc_init(dev, primary_planes[i], cursor_planes[i]); 764 if (IS_ERR(crtc)) { 765 ret = PTR_ERR(crtc); 766 goto fail; 767 } 768 priv->crtcs[priv->num_crtcs++] = crtc; 769 } 770 771 /* All CRTCs are compatible with all encoders */ 772 for (i = 0; i < priv->num_encoders; i++) 773 priv->encoders[i]->possible_crtcs = (1 << priv->num_crtcs) - 1; 774 775 return 0; 776 fail: 777 _dpu_kms_drm_obj_destroy(dpu_kms); 778 return ret; 779 } 780 781 static void _dpu_kms_hw_destroy(struct dpu_kms *dpu_kms) 782 { 783 int i; 784 785 if (dpu_kms->hw_intr) 786 dpu_hw_intr_destroy(dpu_kms->hw_intr); 787 dpu_kms->hw_intr = NULL; 788 789 /* safe to call these more than once during shutdown */ 790 _dpu_kms_mmu_destroy(dpu_kms); 791 792 if (dpu_kms->catalog) { 793 for (i = 0; i < dpu_kms->catalog->vbif_count; i++) { 794 u32 vbif_idx = dpu_kms->catalog->vbif[i].id; 795 796 if ((vbif_idx < VBIF_MAX) && dpu_kms->hw_vbif[vbif_idx]) 797 dpu_hw_vbif_destroy(dpu_kms->hw_vbif[vbif_idx]); 798 } 799 } 800 801 if (dpu_kms->rm_init) 802 dpu_rm_destroy(&dpu_kms->rm); 803 dpu_kms->rm_init = false; 804 805 if (dpu_kms->catalog) 806 dpu_hw_catalog_deinit(dpu_kms->catalog); 807 dpu_kms->catalog = NULL; 808 809 if (dpu_kms->vbif[VBIF_NRT]) 810 devm_iounmap(&dpu_kms->pdev->dev, dpu_kms->vbif[VBIF_NRT]); 811 dpu_kms->vbif[VBIF_NRT] = NULL; 812 813 if (dpu_kms->vbif[VBIF_RT]) 814 devm_iounmap(&dpu_kms->pdev->dev, dpu_kms->vbif[VBIF_RT]); 815 dpu_kms->vbif[VBIF_RT] = NULL; 816 817 if (dpu_kms->hw_mdp) 818 dpu_hw_mdp_destroy(dpu_kms->hw_mdp); 819 dpu_kms->hw_mdp = NULL; 820 821 if (dpu_kms->mmio) 822 devm_iounmap(&dpu_kms->pdev->dev, dpu_kms->mmio); 823 dpu_kms->mmio = NULL; 824 } 825 826 static void dpu_kms_destroy(struct msm_kms *kms) 827 { 828 struct dpu_kms *dpu_kms; 829 830 if (!kms) { 831 DPU_ERROR("invalid kms\n"); 832 return; 833 } 834 835 dpu_kms = to_dpu_kms(kms); 836 837 _dpu_kms_hw_destroy(dpu_kms); 838 839 msm_kms_destroy(&dpu_kms->base); 840 } 841 842 static irqreturn_t dpu_irq(struct msm_kms *kms) 843 { 844 struct dpu_kms *dpu_kms = to_dpu_kms(kms); 845 846 return dpu_core_irq(dpu_kms); 847 } 848 849 static void dpu_irq_preinstall(struct msm_kms *kms) 850 { 851 struct dpu_kms *dpu_kms = to_dpu_kms(kms); 852 853 dpu_core_irq_preinstall(dpu_kms); 854 } 855 856 static int dpu_irq_postinstall(struct msm_kms *kms) 857 { 858 struct msm_drm_private *priv; 859 struct dpu_kms *dpu_kms = to_dpu_kms(kms); 860 int i; 861 862 if (!dpu_kms || !dpu_kms->dev) 863 return -EINVAL; 864 865 priv = dpu_kms->dev->dev_private; 866 if (!priv) 867 return -EINVAL; 868 869 for (i = 0; i < ARRAY_SIZE(priv->dp); i++) 870 msm_dp_irq_postinstall(priv->dp[i]); 871 872 return 0; 873 } 874 875 static void dpu_irq_uninstall(struct msm_kms *kms) 876 { 877 struct dpu_kms *dpu_kms = to_dpu_kms(kms); 878 879 dpu_core_irq_uninstall(dpu_kms); 880 } 881 882 static void dpu_kms_mdp_snapshot(struct msm_disp_state *disp_state, struct msm_kms *kms) 883 { 884 int i; 885 struct dpu_kms *dpu_kms; 886 struct dpu_mdss_cfg *cat; 887 struct dpu_hw_mdp *top; 888 889 dpu_kms = to_dpu_kms(kms); 890 891 cat = dpu_kms->catalog; 892 top = dpu_kms->hw_mdp; 893 894 pm_runtime_get_sync(&dpu_kms->pdev->dev); 895 896 /* dump CTL sub-blocks HW regs info */ 897 for (i = 0; i < cat->ctl_count; i++) 898 msm_disp_snapshot_add_block(disp_state, cat->ctl[i].len, 899 dpu_kms->mmio + cat->ctl[i].base, "ctl_%d", i); 900 901 /* dump DSPP sub-blocks HW regs info */ 902 for (i = 0; i < cat->dspp_count; i++) 903 msm_disp_snapshot_add_block(disp_state, cat->dspp[i].len, 904 dpu_kms->mmio + cat->dspp[i].base, "dspp_%d", i); 905 906 /* dump INTF sub-blocks HW regs info */ 907 for (i = 0; i < cat->intf_count; i++) 908 msm_disp_snapshot_add_block(disp_state, cat->intf[i].len, 909 dpu_kms->mmio + cat->intf[i].base, "intf_%d", i); 910 911 /* dump PP sub-blocks HW regs info */ 912 for (i = 0; i < cat->pingpong_count; i++) 913 msm_disp_snapshot_add_block(disp_state, cat->pingpong[i].len, 914 dpu_kms->mmio + cat->pingpong[i].base, "pingpong_%d", i); 915 916 /* dump SSPP sub-blocks HW regs info */ 917 for (i = 0; i < cat->sspp_count; i++) 918 msm_disp_snapshot_add_block(disp_state, cat->sspp[i].len, 919 dpu_kms->mmio + cat->sspp[i].base, "sspp_%d", i); 920 921 /* dump LM sub-blocks HW regs info */ 922 for (i = 0; i < cat->mixer_count; i++) 923 msm_disp_snapshot_add_block(disp_state, cat->mixer[i].len, 924 dpu_kms->mmio + cat->mixer[i].base, "lm_%d", i); 925 926 msm_disp_snapshot_add_block(disp_state, top->hw.length, 927 dpu_kms->mmio + top->hw.blk_off, "top"); 928 929 pm_runtime_put_sync(&dpu_kms->pdev->dev); 930 } 931 932 static const struct msm_kms_funcs kms_funcs = { 933 .hw_init = dpu_kms_hw_init, 934 .irq_preinstall = dpu_irq_preinstall, 935 .irq_postinstall = dpu_irq_postinstall, 936 .irq_uninstall = dpu_irq_uninstall, 937 .irq = dpu_irq, 938 .enable_commit = dpu_kms_enable_commit, 939 .disable_commit = dpu_kms_disable_commit, 940 .vsync_time = dpu_kms_vsync_time, 941 .prepare_commit = dpu_kms_prepare_commit, 942 .flush_commit = dpu_kms_flush_commit, 943 .wait_flush = dpu_kms_wait_flush, 944 .complete_commit = dpu_kms_complete_commit, 945 .enable_vblank = dpu_kms_enable_vblank, 946 .disable_vblank = dpu_kms_disable_vblank, 947 .check_modified_format = dpu_format_check_modified_format, 948 .get_format = dpu_get_msm_format, 949 .destroy = dpu_kms_destroy, 950 .snapshot = dpu_kms_mdp_snapshot, 951 #ifdef CONFIG_DEBUG_FS 952 .debugfs_init = dpu_kms_debugfs_init, 953 #endif 954 }; 955 956 static void _dpu_kms_mmu_destroy(struct dpu_kms *dpu_kms) 957 { 958 struct msm_mmu *mmu; 959 960 if (!dpu_kms->base.aspace) 961 return; 962 963 mmu = dpu_kms->base.aspace->mmu; 964 965 mmu->funcs->detach(mmu); 966 msm_gem_address_space_put(dpu_kms->base.aspace); 967 968 dpu_kms->base.aspace = NULL; 969 } 970 971 static int _dpu_kms_mmu_init(struct dpu_kms *dpu_kms) 972 { 973 struct iommu_domain *domain; 974 struct msm_gem_address_space *aspace; 975 struct msm_mmu *mmu; 976 977 domain = iommu_domain_alloc(&platform_bus_type); 978 if (!domain) 979 return 0; 980 981 mmu = msm_iommu_new(dpu_kms->dev->dev, domain); 982 if (IS_ERR(mmu)) { 983 iommu_domain_free(domain); 984 return PTR_ERR(mmu); 985 } 986 aspace = msm_gem_address_space_create(mmu, "dpu1", 987 0x1000, 0x100000000 - 0x1000); 988 989 if (IS_ERR(aspace)) { 990 mmu->funcs->destroy(mmu); 991 return PTR_ERR(aspace); 992 } 993 994 dpu_kms->base.aspace = aspace; 995 return 0; 996 } 997 998 u64 dpu_kms_get_clk_rate(struct dpu_kms *dpu_kms, char *clock_name) 999 { 1000 struct clk *clk; 1001 1002 clk = msm_clk_bulk_get_clock(dpu_kms->clocks, dpu_kms->num_clocks, clock_name); 1003 if (!clk) 1004 return -EINVAL; 1005 1006 return clk_get_rate(clk); 1007 } 1008 1009 static int dpu_kms_hw_init(struct msm_kms *kms) 1010 { 1011 struct dpu_kms *dpu_kms; 1012 struct drm_device *dev; 1013 int i, rc = -EINVAL; 1014 1015 if (!kms) { 1016 DPU_ERROR("invalid kms\n"); 1017 return rc; 1018 } 1019 1020 dpu_kms = to_dpu_kms(kms); 1021 dev = dpu_kms->dev; 1022 1023 rc = dpu_kms_global_obj_init(dpu_kms); 1024 if (rc) 1025 return rc; 1026 1027 atomic_set(&dpu_kms->bandwidth_ref, 0); 1028 1029 dpu_kms->mmio = msm_ioremap(dpu_kms->pdev, "mdp"); 1030 if (IS_ERR(dpu_kms->mmio)) { 1031 rc = PTR_ERR(dpu_kms->mmio); 1032 DPU_ERROR("mdp register memory map failed: %d\n", rc); 1033 dpu_kms->mmio = NULL; 1034 goto error; 1035 } 1036 DRM_DEBUG("mapped dpu address space @%pK\n", dpu_kms->mmio); 1037 1038 dpu_kms->vbif[VBIF_RT] = msm_ioremap(dpu_kms->pdev, "vbif"); 1039 if (IS_ERR(dpu_kms->vbif[VBIF_RT])) { 1040 rc = PTR_ERR(dpu_kms->vbif[VBIF_RT]); 1041 DPU_ERROR("vbif register memory map failed: %d\n", rc); 1042 dpu_kms->vbif[VBIF_RT] = NULL; 1043 goto error; 1044 } 1045 dpu_kms->vbif[VBIF_NRT] = msm_ioremap_quiet(dpu_kms->pdev, "vbif_nrt"); 1046 if (IS_ERR(dpu_kms->vbif[VBIF_NRT])) { 1047 dpu_kms->vbif[VBIF_NRT] = NULL; 1048 DPU_DEBUG("VBIF NRT is not defined"); 1049 } 1050 1051 dpu_kms->reg_dma = msm_ioremap_quiet(dpu_kms->pdev, "regdma"); 1052 if (IS_ERR(dpu_kms->reg_dma)) { 1053 dpu_kms->reg_dma = NULL; 1054 DPU_DEBUG("REG_DMA is not defined"); 1055 } 1056 1057 dpu_kms_parse_data_bus_icc_path(dpu_kms); 1058 1059 pm_runtime_get_sync(&dpu_kms->pdev->dev); 1060 1061 dpu_kms->core_rev = readl_relaxed(dpu_kms->mmio + 0x0); 1062 1063 pr_info("dpu hardware revision:0x%x\n", dpu_kms->core_rev); 1064 1065 dpu_kms->catalog = dpu_hw_catalog_init(dpu_kms->core_rev); 1066 if (IS_ERR_OR_NULL(dpu_kms->catalog)) { 1067 rc = PTR_ERR(dpu_kms->catalog); 1068 if (!dpu_kms->catalog) 1069 rc = -EINVAL; 1070 DPU_ERROR("catalog init failed: %d\n", rc); 1071 dpu_kms->catalog = NULL; 1072 goto power_error; 1073 } 1074 1075 /* 1076 * Now we need to read the HW catalog and initialize resources such as 1077 * clocks, regulators, GDSC/MMAGIC, ioremap the register ranges etc 1078 */ 1079 rc = _dpu_kms_mmu_init(dpu_kms); 1080 if (rc) { 1081 DPU_ERROR("dpu_kms_mmu_init failed: %d\n", rc); 1082 goto power_error; 1083 } 1084 1085 rc = dpu_rm_init(&dpu_kms->rm, dpu_kms->catalog, dpu_kms->mmio); 1086 if (rc) { 1087 DPU_ERROR("rm init failed: %d\n", rc); 1088 goto power_error; 1089 } 1090 1091 dpu_kms->rm_init = true; 1092 1093 dpu_kms->hw_mdp = dpu_hw_mdptop_init(MDP_TOP, dpu_kms->mmio, 1094 dpu_kms->catalog); 1095 if (IS_ERR(dpu_kms->hw_mdp)) { 1096 rc = PTR_ERR(dpu_kms->hw_mdp); 1097 DPU_ERROR("failed to get hw_mdp: %d\n", rc); 1098 dpu_kms->hw_mdp = NULL; 1099 goto power_error; 1100 } 1101 1102 for (i = 0; i < dpu_kms->catalog->vbif_count; i++) { 1103 u32 vbif_idx = dpu_kms->catalog->vbif[i].id; 1104 1105 dpu_kms->hw_vbif[i] = dpu_hw_vbif_init(vbif_idx, 1106 dpu_kms->vbif[vbif_idx], dpu_kms->catalog); 1107 if (IS_ERR_OR_NULL(dpu_kms->hw_vbif[vbif_idx])) { 1108 rc = PTR_ERR(dpu_kms->hw_vbif[vbif_idx]); 1109 if (!dpu_kms->hw_vbif[vbif_idx]) 1110 rc = -EINVAL; 1111 DPU_ERROR("failed to init vbif %d: %d\n", vbif_idx, rc); 1112 dpu_kms->hw_vbif[vbif_idx] = NULL; 1113 goto power_error; 1114 } 1115 } 1116 1117 rc = dpu_core_perf_init(&dpu_kms->perf, dev, dpu_kms->catalog, 1118 msm_clk_bulk_get_clock(dpu_kms->clocks, dpu_kms->num_clocks, "core")); 1119 if (rc) { 1120 DPU_ERROR("failed to init perf %d\n", rc); 1121 goto perf_err; 1122 } 1123 1124 dpu_kms->hw_intr = dpu_hw_intr_init(dpu_kms->mmio, dpu_kms->catalog); 1125 if (IS_ERR_OR_NULL(dpu_kms->hw_intr)) { 1126 rc = PTR_ERR(dpu_kms->hw_intr); 1127 DPU_ERROR("hw_intr init failed: %d\n", rc); 1128 dpu_kms->hw_intr = NULL; 1129 goto hw_intr_init_err; 1130 } 1131 1132 dev->mode_config.min_width = 0; 1133 dev->mode_config.min_height = 0; 1134 1135 /* 1136 * max crtc width is equal to the max mixer width * 2 and max height is 1137 * is 4K 1138 */ 1139 dev->mode_config.max_width = 1140 dpu_kms->catalog->caps->max_mixer_width * 2; 1141 dev->mode_config.max_height = 4096; 1142 1143 dev->max_vblank_count = 0xffffffff; 1144 /* Disable vblank irqs aggressively for power-saving */ 1145 dev->vblank_disable_immediate = true; 1146 1147 /* 1148 * _dpu_kms_drm_obj_init should create the DRM related objects 1149 * i.e. CRTCs, planes, encoders, connectors and so forth 1150 */ 1151 rc = _dpu_kms_drm_obj_init(dpu_kms); 1152 if (rc) { 1153 DPU_ERROR("modeset init failed: %d\n", rc); 1154 goto drm_obj_init_err; 1155 } 1156 1157 dpu_vbif_init_memtypes(dpu_kms); 1158 1159 pm_runtime_put_sync(&dpu_kms->pdev->dev); 1160 1161 return 0; 1162 1163 drm_obj_init_err: 1164 dpu_core_perf_destroy(&dpu_kms->perf); 1165 hw_intr_init_err: 1166 perf_err: 1167 power_error: 1168 pm_runtime_put_sync(&dpu_kms->pdev->dev); 1169 error: 1170 _dpu_kms_hw_destroy(dpu_kms); 1171 1172 return rc; 1173 } 1174 1175 struct msm_kms *dpu_kms_init(struct drm_device *dev) 1176 { 1177 struct msm_drm_private *priv; 1178 struct dpu_kms *dpu_kms; 1179 int irq; 1180 1181 if (!dev) { 1182 DPU_ERROR("drm device node invalid\n"); 1183 return ERR_PTR(-EINVAL); 1184 } 1185 1186 priv = dev->dev_private; 1187 dpu_kms = to_dpu_kms(priv->kms); 1188 1189 irq = irq_of_parse_and_map(dpu_kms->pdev->dev.of_node, 0); 1190 if (irq < 0) { 1191 DPU_ERROR("failed to get irq: %d\n", irq); 1192 return ERR_PTR(irq); 1193 } 1194 dpu_kms->base.irq = irq; 1195 1196 return &dpu_kms->base; 1197 } 1198 1199 static int dpu_bind(struct device *dev, struct device *master, void *data) 1200 { 1201 struct msm_drm_private *priv = dev_get_drvdata(master); 1202 struct platform_device *pdev = to_platform_device(dev); 1203 struct drm_device *ddev = priv->dev; 1204 struct dpu_kms *dpu_kms; 1205 int ret = 0; 1206 1207 dpu_kms = devm_kzalloc(&pdev->dev, sizeof(*dpu_kms), GFP_KERNEL); 1208 if (!dpu_kms) 1209 return -ENOMEM; 1210 1211 ret = devm_pm_opp_set_clkname(dev, "core"); 1212 if (ret) 1213 return ret; 1214 /* OPP table is optional */ 1215 ret = devm_pm_opp_of_add_table(dev); 1216 if (ret && ret != -ENODEV) { 1217 dev_err(dev, "invalid OPP table in device tree\n"); 1218 return ret; 1219 } 1220 1221 ret = devm_clk_bulk_get_all(&pdev->dev, &dpu_kms->clocks); 1222 if (ret < 0) { 1223 DPU_ERROR("failed to parse clocks, ret=%d\n", ret); 1224 return ret; 1225 } 1226 dpu_kms->num_clocks = ret; 1227 1228 platform_set_drvdata(pdev, dpu_kms); 1229 1230 ret = msm_kms_init(&dpu_kms->base, &kms_funcs); 1231 if (ret) { 1232 DPU_ERROR("failed to init kms, ret=%d\n", ret); 1233 return ret; 1234 } 1235 dpu_kms->dev = ddev; 1236 dpu_kms->pdev = pdev; 1237 1238 pm_runtime_enable(&pdev->dev); 1239 dpu_kms->rpm_enabled = true; 1240 1241 priv->kms = &dpu_kms->base; 1242 1243 return ret; 1244 } 1245 1246 static void dpu_unbind(struct device *dev, struct device *master, void *data) 1247 { 1248 struct platform_device *pdev = to_platform_device(dev); 1249 struct dpu_kms *dpu_kms = platform_get_drvdata(pdev); 1250 1251 if (dpu_kms->rpm_enabled) 1252 pm_runtime_disable(&pdev->dev); 1253 } 1254 1255 static const struct component_ops dpu_ops = { 1256 .bind = dpu_bind, 1257 .unbind = dpu_unbind, 1258 }; 1259 1260 static int dpu_dev_probe(struct platform_device *pdev) 1261 { 1262 return component_add(&pdev->dev, &dpu_ops); 1263 } 1264 1265 static int dpu_dev_remove(struct platform_device *pdev) 1266 { 1267 component_del(&pdev->dev, &dpu_ops); 1268 return 0; 1269 } 1270 1271 static int __maybe_unused dpu_runtime_suspend(struct device *dev) 1272 { 1273 int i; 1274 struct platform_device *pdev = to_platform_device(dev); 1275 struct dpu_kms *dpu_kms = platform_get_drvdata(pdev); 1276 1277 /* Drop the performance state vote */ 1278 dev_pm_opp_set_rate(dev, 0); 1279 clk_bulk_disable_unprepare(dpu_kms->num_clocks, dpu_kms->clocks); 1280 1281 for (i = 0; i < dpu_kms->num_paths; i++) 1282 icc_set_bw(dpu_kms->path[i], 0, 0); 1283 1284 return 0; 1285 } 1286 1287 static int __maybe_unused dpu_runtime_resume(struct device *dev) 1288 { 1289 int rc = -1; 1290 struct platform_device *pdev = to_platform_device(dev); 1291 struct dpu_kms *dpu_kms = platform_get_drvdata(pdev); 1292 struct drm_encoder *encoder; 1293 struct drm_device *ddev; 1294 int i; 1295 1296 ddev = dpu_kms->dev; 1297 1298 WARN_ON(!(dpu_kms->num_paths)); 1299 /* Min vote of BW is required before turning on AXI clk */ 1300 for (i = 0; i < dpu_kms->num_paths; i++) 1301 icc_set_bw(dpu_kms->path[i], 0, Bps_to_icc(MIN_IB_BW)); 1302 1303 rc = clk_bulk_prepare_enable(dpu_kms->num_clocks, dpu_kms->clocks); 1304 if (rc) { 1305 DPU_ERROR("clock enable failed rc:%d\n", rc); 1306 return rc; 1307 } 1308 1309 dpu_vbif_init_memtypes(dpu_kms); 1310 1311 drm_for_each_encoder(encoder, ddev) 1312 dpu_encoder_virt_runtime_resume(encoder); 1313 1314 return rc; 1315 } 1316 1317 static const struct dev_pm_ops dpu_pm_ops = { 1318 SET_RUNTIME_PM_OPS(dpu_runtime_suspend, dpu_runtime_resume, NULL) 1319 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1320 pm_runtime_force_resume) 1321 }; 1322 1323 const struct of_device_id dpu_dt_match[] = { 1324 { .compatible = "qcom,msm8998-dpu", }, 1325 { .compatible = "qcom,qcm2290-dpu", }, 1326 { .compatible = "qcom,sdm845-dpu", }, 1327 { .compatible = "qcom,sc7180-dpu", }, 1328 { .compatible = "qcom,sc7280-dpu", }, 1329 { .compatible = "qcom,sc8180x-dpu", }, 1330 { .compatible = "qcom,sm8150-dpu", }, 1331 { .compatible = "qcom,sm8250-dpu", }, 1332 {} 1333 }; 1334 MODULE_DEVICE_TABLE(of, dpu_dt_match); 1335 1336 static struct platform_driver dpu_driver = { 1337 .probe = dpu_dev_probe, 1338 .remove = dpu_dev_remove, 1339 .driver = { 1340 .name = "msm_dpu", 1341 .of_match_table = dpu_dt_match, 1342 .pm = &dpu_pm_ops, 1343 }, 1344 }; 1345 1346 void __init msm_dpu_register(void) 1347 { 1348 platform_driver_register(&dpu_driver); 1349 } 1350 1351 void __exit msm_dpu_unregister(void) 1352 { 1353 platform_driver_unregister(&dpu_driver); 1354 } 1355