1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013 Red Hat 4 * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved. 5 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 6 * 7 * Author: Rob Clark <robdclark@gmail.com> 8 */ 9 10 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ 11 12 #include <linux/debugfs.h> 13 #include <linux/dma-buf.h> 14 #include <linux/of_irq.h> 15 #include <linux/pm_opp.h> 16 17 #include <drm/drm_crtc.h> 18 #include <drm/drm_file.h> 19 #include <drm/drm_framebuffer.h> 20 #include <drm/drm_vblank.h> 21 #include <drm/drm_writeback.h> 22 23 #include "msm_drv.h" 24 #include "msm_mmu.h" 25 #include "msm_gem.h" 26 #include "disp/msm_disp_snapshot.h" 27 28 #include "dpu_core_irq.h" 29 #include "dpu_crtc.h" 30 #include "dpu_encoder.h" 31 #include "dpu_formats.h" 32 #include "dpu_hw_vbif.h" 33 #include "dpu_kms.h" 34 #include "dpu_plane.h" 35 #include "dpu_vbif.h" 36 #include "dpu_writeback.h" 37 38 #define CREATE_TRACE_POINTS 39 #include "dpu_trace.h" 40 41 /* 42 * To enable overall DRM driver logging 43 * # echo 0x2 > /sys/module/drm/parameters/debug 44 * 45 * To enable DRM driver h/w logging 46 * # echo <mask> > /sys/kernel/debug/dri/0/debug/hw_log_mask 47 * 48 * See dpu_hw_mdss.h for h/w logging mask definitions (search for DPU_DBG_MASK_) 49 */ 50 #define DPU_DEBUGFS_DIR "msm_dpu" 51 #define DPU_DEBUGFS_HWMASKNAME "hw_log_mask" 52 53 static int dpu_kms_hw_init(struct msm_kms *kms); 54 static void _dpu_kms_mmu_destroy(struct dpu_kms *dpu_kms); 55 56 #ifdef CONFIG_DEBUG_FS 57 static int _dpu_danger_signal_status(struct seq_file *s, 58 bool danger_status) 59 { 60 struct dpu_kms *kms = (struct dpu_kms *)s->private; 61 struct dpu_danger_safe_status status; 62 int i; 63 64 if (!kms->hw_mdp) { 65 DPU_ERROR("invalid arg(s)\n"); 66 return 0; 67 } 68 69 memset(&status, 0, sizeof(struct dpu_danger_safe_status)); 70 71 pm_runtime_get_sync(&kms->pdev->dev); 72 if (danger_status) { 73 seq_puts(s, "\nDanger signal status:\n"); 74 if (kms->hw_mdp->ops.get_danger_status) 75 kms->hw_mdp->ops.get_danger_status(kms->hw_mdp, 76 &status); 77 } else { 78 seq_puts(s, "\nSafe signal status:\n"); 79 if (kms->hw_mdp->ops.get_safe_status) 80 kms->hw_mdp->ops.get_safe_status(kms->hw_mdp, 81 &status); 82 } 83 pm_runtime_put_sync(&kms->pdev->dev); 84 85 seq_printf(s, "MDP : 0x%x\n", status.mdp); 86 87 for (i = SSPP_VIG0; i < SSPP_MAX; i++) 88 seq_printf(s, "SSPP%d : 0x%x \n", i - SSPP_VIG0, 89 status.sspp[i]); 90 seq_puts(s, "\n"); 91 92 return 0; 93 } 94 95 static int dpu_debugfs_danger_stats_show(struct seq_file *s, void *v) 96 { 97 return _dpu_danger_signal_status(s, true); 98 } 99 DEFINE_SHOW_ATTRIBUTE(dpu_debugfs_danger_stats); 100 101 static int dpu_debugfs_safe_stats_show(struct seq_file *s, void *v) 102 { 103 return _dpu_danger_signal_status(s, false); 104 } 105 DEFINE_SHOW_ATTRIBUTE(dpu_debugfs_safe_stats); 106 107 static ssize_t _dpu_plane_danger_read(struct file *file, 108 char __user *buff, size_t count, loff_t *ppos) 109 { 110 struct dpu_kms *kms = file->private_data; 111 int len; 112 char buf[40]; 113 114 len = scnprintf(buf, sizeof(buf), "%d\n", !kms->has_danger_ctrl); 115 116 return simple_read_from_buffer(buff, count, ppos, buf, len); 117 } 118 119 static void _dpu_plane_set_danger_state(struct dpu_kms *kms, bool enable) 120 { 121 struct drm_plane *plane; 122 123 drm_for_each_plane(plane, kms->dev) { 124 if (plane->fb && plane->state) { 125 dpu_plane_danger_signal_ctrl(plane, enable); 126 DPU_DEBUG("plane:%d img:%dx%d ", 127 plane->base.id, plane->fb->width, 128 plane->fb->height); 129 DPU_DEBUG("src[%d,%d,%d,%d] dst[%d,%d,%d,%d]\n", 130 plane->state->src_x >> 16, 131 plane->state->src_y >> 16, 132 plane->state->src_w >> 16, 133 plane->state->src_h >> 16, 134 plane->state->crtc_x, plane->state->crtc_y, 135 plane->state->crtc_w, plane->state->crtc_h); 136 } else { 137 DPU_DEBUG("Inactive plane:%d\n", plane->base.id); 138 } 139 } 140 } 141 142 static ssize_t _dpu_plane_danger_write(struct file *file, 143 const char __user *user_buf, size_t count, loff_t *ppos) 144 { 145 struct dpu_kms *kms = file->private_data; 146 int disable_panic; 147 int ret; 148 149 ret = kstrtouint_from_user(user_buf, count, 0, &disable_panic); 150 if (ret) 151 return ret; 152 153 if (disable_panic) { 154 /* Disable panic signal for all active pipes */ 155 DPU_DEBUG("Disabling danger:\n"); 156 _dpu_plane_set_danger_state(kms, false); 157 kms->has_danger_ctrl = false; 158 } else { 159 /* Enable panic signal for all active pipes */ 160 DPU_DEBUG("Enabling danger:\n"); 161 kms->has_danger_ctrl = true; 162 _dpu_plane_set_danger_state(kms, true); 163 } 164 165 return count; 166 } 167 168 static const struct file_operations dpu_plane_danger_enable = { 169 .open = simple_open, 170 .read = _dpu_plane_danger_read, 171 .write = _dpu_plane_danger_write, 172 }; 173 174 static void dpu_debugfs_danger_init(struct dpu_kms *dpu_kms, 175 struct dentry *parent) 176 { 177 struct dentry *entry = debugfs_create_dir("danger", parent); 178 179 debugfs_create_file("danger_status", 0600, entry, 180 dpu_kms, &dpu_debugfs_danger_stats_fops); 181 debugfs_create_file("safe_status", 0600, entry, 182 dpu_kms, &dpu_debugfs_safe_stats_fops); 183 debugfs_create_file("disable_danger", 0600, entry, 184 dpu_kms, &dpu_plane_danger_enable); 185 186 } 187 188 /* 189 * Companion structure for dpu_debugfs_create_regset32. 190 */ 191 struct dpu_debugfs_regset32 { 192 uint32_t offset; 193 uint32_t blk_len; 194 struct dpu_kms *dpu_kms; 195 }; 196 197 static int _dpu_debugfs_show_regset32(struct seq_file *s, void *data) 198 { 199 struct dpu_debugfs_regset32 *regset = s->private; 200 struct dpu_kms *dpu_kms = regset->dpu_kms; 201 void __iomem *base; 202 uint32_t i, addr; 203 204 if (!dpu_kms->mmio) 205 return 0; 206 207 base = dpu_kms->mmio + regset->offset; 208 209 /* insert padding spaces, if needed */ 210 if (regset->offset & 0xF) { 211 seq_printf(s, "[%x]", regset->offset & ~0xF); 212 for (i = 0; i < (regset->offset & 0xF); i += 4) 213 seq_puts(s, " "); 214 } 215 216 pm_runtime_get_sync(&dpu_kms->pdev->dev); 217 218 /* main register output */ 219 for (i = 0; i < regset->blk_len; i += 4) { 220 addr = regset->offset + i; 221 if ((addr & 0xF) == 0x0) 222 seq_printf(s, i ? "\n[%x]" : "[%x]", addr); 223 seq_printf(s, " %08x", readl_relaxed(base + i)); 224 } 225 seq_puts(s, "\n"); 226 pm_runtime_put_sync(&dpu_kms->pdev->dev); 227 228 return 0; 229 } 230 231 static int dpu_debugfs_open_regset32(struct inode *inode, 232 struct file *file) 233 { 234 return single_open(file, _dpu_debugfs_show_regset32, inode->i_private); 235 } 236 237 static const struct file_operations dpu_fops_regset32 = { 238 .open = dpu_debugfs_open_regset32, 239 .read = seq_read, 240 .llseek = seq_lseek, 241 .release = single_release, 242 }; 243 244 void dpu_debugfs_create_regset32(const char *name, umode_t mode, 245 void *parent, 246 uint32_t offset, uint32_t length, struct dpu_kms *dpu_kms) 247 { 248 struct dpu_debugfs_regset32 *regset; 249 250 if (WARN_ON(!name || !dpu_kms || !length)) 251 return; 252 253 regset = devm_kzalloc(&dpu_kms->pdev->dev, sizeof(*regset), GFP_KERNEL); 254 if (!regset) 255 return; 256 257 /* make sure offset is a multiple of 4 */ 258 regset->offset = round_down(offset, 4); 259 regset->blk_len = length; 260 regset->dpu_kms = dpu_kms; 261 262 debugfs_create_file(name, mode, parent, regset, &dpu_fops_regset32); 263 } 264 265 static int dpu_kms_debugfs_init(struct msm_kms *kms, struct drm_minor *minor) 266 { 267 struct dpu_kms *dpu_kms = to_dpu_kms(kms); 268 void *p = dpu_hw_util_get_log_mask_ptr(); 269 struct dentry *entry; 270 struct drm_device *dev; 271 struct msm_drm_private *priv; 272 int i; 273 274 if (!p) 275 return -EINVAL; 276 277 /* Only create a set of debugfs for the primary node, ignore render nodes */ 278 if (minor->type != DRM_MINOR_PRIMARY) 279 return 0; 280 281 dev = dpu_kms->dev; 282 priv = dev->dev_private; 283 284 entry = debugfs_create_dir("debug", minor->debugfs_root); 285 286 debugfs_create_x32(DPU_DEBUGFS_HWMASKNAME, 0600, entry, p); 287 288 dpu_debugfs_danger_init(dpu_kms, entry); 289 dpu_debugfs_vbif_init(dpu_kms, entry); 290 dpu_debugfs_core_irq_init(dpu_kms, entry); 291 dpu_debugfs_sspp_init(dpu_kms, entry); 292 293 for (i = 0; i < ARRAY_SIZE(priv->dp); i++) { 294 if (priv->dp[i]) 295 msm_dp_debugfs_init(priv->dp[i], minor); 296 } 297 298 return dpu_core_perf_debugfs_init(dpu_kms, entry); 299 } 300 #endif 301 302 /* Global/shared object state funcs */ 303 304 /* 305 * This is a helper that returns the private state currently in operation. 306 * Note that this would return the "old_state" if called in the atomic check 307 * path, and the "new_state" after the atomic swap has been done. 308 */ 309 struct dpu_global_state * 310 dpu_kms_get_existing_global_state(struct dpu_kms *dpu_kms) 311 { 312 return to_dpu_global_state(dpu_kms->global_state.state); 313 } 314 315 /* 316 * This acquires the modeset lock set aside for global state, creates 317 * a new duplicated private object state. 318 */ 319 struct dpu_global_state *dpu_kms_get_global_state(struct drm_atomic_state *s) 320 { 321 struct msm_drm_private *priv = s->dev->dev_private; 322 struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms); 323 struct drm_private_state *priv_state; 324 int ret; 325 326 ret = drm_modeset_lock(&dpu_kms->global_state_lock, s->acquire_ctx); 327 if (ret) 328 return ERR_PTR(ret); 329 330 priv_state = drm_atomic_get_private_obj_state(s, 331 &dpu_kms->global_state); 332 if (IS_ERR(priv_state)) 333 return ERR_CAST(priv_state); 334 335 return to_dpu_global_state(priv_state); 336 } 337 338 static struct drm_private_state * 339 dpu_kms_global_duplicate_state(struct drm_private_obj *obj) 340 { 341 struct dpu_global_state *state; 342 343 state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL); 344 if (!state) 345 return NULL; 346 347 __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base); 348 349 return &state->base; 350 } 351 352 static void dpu_kms_global_destroy_state(struct drm_private_obj *obj, 353 struct drm_private_state *state) 354 { 355 struct dpu_global_state *dpu_state = to_dpu_global_state(state); 356 357 kfree(dpu_state); 358 } 359 360 static const struct drm_private_state_funcs dpu_kms_global_state_funcs = { 361 .atomic_duplicate_state = dpu_kms_global_duplicate_state, 362 .atomic_destroy_state = dpu_kms_global_destroy_state, 363 }; 364 365 static int dpu_kms_global_obj_init(struct dpu_kms *dpu_kms) 366 { 367 struct dpu_global_state *state; 368 369 drm_modeset_lock_init(&dpu_kms->global_state_lock); 370 371 state = kzalloc(sizeof(*state), GFP_KERNEL); 372 if (!state) 373 return -ENOMEM; 374 375 drm_atomic_private_obj_init(dpu_kms->dev, &dpu_kms->global_state, 376 &state->base, 377 &dpu_kms_global_state_funcs); 378 return 0; 379 } 380 381 static int dpu_kms_parse_data_bus_icc_path(struct dpu_kms *dpu_kms) 382 { 383 struct icc_path *path0; 384 struct icc_path *path1; 385 struct drm_device *dev = dpu_kms->dev; 386 struct device *dpu_dev = dev->dev; 387 struct device *mdss_dev = dpu_dev->parent; 388 389 /* Interconnects are a part of MDSS device tree binding, not the 390 * MDP/DPU device. */ 391 path0 = of_icc_get(mdss_dev, "mdp0-mem"); 392 path1 = of_icc_get(mdss_dev, "mdp1-mem"); 393 394 if (IS_ERR_OR_NULL(path0)) 395 return PTR_ERR_OR_ZERO(path0); 396 397 dpu_kms->path[0] = path0; 398 dpu_kms->num_paths = 1; 399 400 if (!IS_ERR_OR_NULL(path1)) { 401 dpu_kms->path[1] = path1; 402 dpu_kms->num_paths++; 403 } 404 return 0; 405 } 406 407 static int dpu_kms_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc) 408 { 409 return dpu_crtc_vblank(crtc, true); 410 } 411 412 static void dpu_kms_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc) 413 { 414 dpu_crtc_vblank(crtc, false); 415 } 416 417 static void dpu_kms_enable_commit(struct msm_kms *kms) 418 { 419 struct dpu_kms *dpu_kms = to_dpu_kms(kms); 420 pm_runtime_get_sync(&dpu_kms->pdev->dev); 421 } 422 423 static void dpu_kms_disable_commit(struct msm_kms *kms) 424 { 425 struct dpu_kms *dpu_kms = to_dpu_kms(kms); 426 pm_runtime_put_sync(&dpu_kms->pdev->dev); 427 } 428 429 static ktime_t dpu_kms_vsync_time(struct msm_kms *kms, struct drm_crtc *crtc) 430 { 431 struct drm_encoder *encoder; 432 433 drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) { 434 ktime_t vsync_time; 435 436 if (dpu_encoder_vsync_time(encoder, &vsync_time) == 0) 437 return vsync_time; 438 } 439 440 return ktime_get(); 441 } 442 443 static void dpu_kms_prepare_commit(struct msm_kms *kms, 444 struct drm_atomic_state *state) 445 { 446 struct drm_crtc *crtc; 447 struct drm_crtc_state *crtc_state; 448 struct drm_encoder *encoder; 449 int i; 450 451 if (!kms) 452 return; 453 454 /* Call prepare_commit for all affected encoders */ 455 for_each_new_crtc_in_state(state, crtc, crtc_state, i) { 456 drm_for_each_encoder_mask(encoder, crtc->dev, 457 crtc_state->encoder_mask) { 458 dpu_encoder_prepare_commit(encoder); 459 } 460 } 461 } 462 463 static void dpu_kms_flush_commit(struct msm_kms *kms, unsigned crtc_mask) 464 { 465 struct dpu_kms *dpu_kms = to_dpu_kms(kms); 466 struct drm_crtc *crtc; 467 468 for_each_crtc_mask(dpu_kms->dev, crtc, crtc_mask) { 469 if (!crtc->state->active) 470 continue; 471 472 trace_dpu_kms_commit(DRMID(crtc)); 473 dpu_crtc_commit_kickoff(crtc); 474 } 475 } 476 477 static void dpu_kms_complete_commit(struct msm_kms *kms, unsigned crtc_mask) 478 { 479 struct dpu_kms *dpu_kms = to_dpu_kms(kms); 480 struct drm_crtc *crtc; 481 482 DPU_ATRACE_BEGIN("kms_complete_commit"); 483 484 for_each_crtc_mask(dpu_kms->dev, crtc, crtc_mask) 485 dpu_crtc_complete_commit(crtc); 486 487 DPU_ATRACE_END("kms_complete_commit"); 488 } 489 490 static void dpu_kms_wait_for_commit_done(struct msm_kms *kms, 491 struct drm_crtc *crtc) 492 { 493 struct drm_encoder *encoder; 494 struct drm_device *dev; 495 int ret; 496 497 if (!kms || !crtc || !crtc->state) { 498 DPU_ERROR("invalid params\n"); 499 return; 500 } 501 502 dev = crtc->dev; 503 504 if (!crtc->state->enable) { 505 DPU_DEBUG("[crtc:%d] not enable\n", crtc->base.id); 506 return; 507 } 508 509 if (!crtc->state->active) { 510 DPU_DEBUG("[crtc:%d] not active\n", crtc->base.id); 511 return; 512 } 513 514 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 515 if (encoder->crtc != crtc) 516 continue; 517 /* 518 * Wait for post-flush if necessary to delay before 519 * plane_cleanup. For example, wait for vsync in case of video 520 * mode panels. This may be a no-op for command mode panels. 521 */ 522 trace_dpu_kms_wait_for_commit_done(DRMID(crtc)); 523 ret = dpu_encoder_wait_for_event(encoder, MSM_ENC_COMMIT_DONE); 524 if (ret && ret != -EWOULDBLOCK) { 525 DPU_ERROR("wait for commit done returned %d\n", ret); 526 break; 527 } 528 } 529 } 530 531 static void dpu_kms_wait_flush(struct msm_kms *kms, unsigned crtc_mask) 532 { 533 struct dpu_kms *dpu_kms = to_dpu_kms(kms); 534 struct drm_crtc *crtc; 535 536 for_each_crtc_mask(dpu_kms->dev, crtc, crtc_mask) 537 dpu_kms_wait_for_commit_done(kms, crtc); 538 } 539 540 static int _dpu_kms_initialize_dsi(struct drm_device *dev, 541 struct msm_drm_private *priv, 542 struct dpu_kms *dpu_kms) 543 { 544 struct drm_encoder *encoder = NULL; 545 struct msm_display_info info; 546 int i, rc = 0; 547 548 if (!(priv->dsi[0] || priv->dsi[1])) 549 return rc; 550 551 /* 552 * We support following confiurations: 553 * - Single DSI host (dsi0 or dsi1) 554 * - Two independent DSI hosts 555 * - Bonded DSI0 and DSI1 hosts 556 * 557 * TODO: Support swapping DSI0 and DSI1 in the bonded setup. 558 */ 559 for (i = 0; i < ARRAY_SIZE(priv->dsi); i++) { 560 int other = (i + 1) % 2; 561 562 if (!priv->dsi[i]) 563 continue; 564 565 if (msm_dsi_is_bonded_dsi(priv->dsi[i]) && 566 !msm_dsi_is_master_dsi(priv->dsi[i])) 567 continue; 568 569 encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_DSI); 570 if (IS_ERR(encoder)) { 571 DPU_ERROR("encoder init failed for dsi display\n"); 572 return PTR_ERR(encoder); 573 } 574 575 memset(&info, 0, sizeof(info)); 576 info.intf_type = encoder->encoder_type; 577 578 rc = msm_dsi_modeset_init(priv->dsi[i], dev, encoder); 579 if (rc) { 580 DPU_ERROR("modeset_init failed for dsi[%d], rc = %d\n", 581 i, rc); 582 break; 583 } 584 585 info.h_tile_instance[info.num_of_h_tiles++] = i; 586 info.capabilities = msm_dsi_is_cmd_mode(priv->dsi[i]) ? 587 MSM_DISPLAY_CAP_CMD_MODE : 588 MSM_DISPLAY_CAP_VID_MODE; 589 590 info.dsc = msm_dsi_get_dsc_config(priv->dsi[i]); 591 592 if (msm_dsi_is_bonded_dsi(priv->dsi[i]) && priv->dsi[other]) { 593 rc = msm_dsi_modeset_init(priv->dsi[other], dev, encoder); 594 if (rc) { 595 DPU_ERROR("modeset_init failed for dsi[%d], rc = %d\n", 596 other, rc); 597 break; 598 } 599 600 info.h_tile_instance[info.num_of_h_tiles++] = other; 601 } 602 603 rc = dpu_encoder_setup(dev, encoder, &info); 604 if (rc) 605 DPU_ERROR("failed to setup DPU encoder %d: rc:%d\n", 606 encoder->base.id, rc); 607 } 608 609 return rc; 610 } 611 612 static int _dpu_kms_initialize_displayport(struct drm_device *dev, 613 struct msm_drm_private *priv, 614 struct dpu_kms *dpu_kms) 615 { 616 struct drm_encoder *encoder = NULL; 617 struct msm_display_info info; 618 int rc; 619 int i; 620 621 for (i = 0; i < ARRAY_SIZE(priv->dp); i++) { 622 if (!priv->dp[i]) 623 continue; 624 625 encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_TMDS); 626 if (IS_ERR(encoder)) { 627 DPU_ERROR("encoder init failed for dsi display\n"); 628 return PTR_ERR(encoder); 629 } 630 631 memset(&info, 0, sizeof(info)); 632 rc = msm_dp_modeset_init(priv->dp[i], dev, encoder); 633 if (rc) { 634 DPU_ERROR("modeset_init failed for DP, rc = %d\n", rc); 635 drm_encoder_cleanup(encoder); 636 return rc; 637 } 638 639 info.num_of_h_tiles = 1; 640 info.h_tile_instance[0] = i; 641 info.capabilities = MSM_DISPLAY_CAP_VID_MODE; 642 info.intf_type = encoder->encoder_type; 643 rc = dpu_encoder_setup(dev, encoder, &info); 644 if (rc) { 645 DPU_ERROR("failed to setup DPU encoder %d: rc:%d\n", 646 encoder->base.id, rc); 647 return rc; 648 } 649 } 650 651 return 0; 652 } 653 654 static int _dpu_kms_initialize_writeback(struct drm_device *dev, 655 struct msm_drm_private *priv, struct dpu_kms *dpu_kms, 656 const u32 *wb_formats, int n_formats) 657 { 658 struct drm_encoder *encoder = NULL; 659 struct msm_display_info info; 660 int rc; 661 662 encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_VIRTUAL); 663 if (IS_ERR(encoder)) { 664 DPU_ERROR("encoder init failed for dsi display\n"); 665 return PTR_ERR(encoder); 666 } 667 668 memset(&info, 0, sizeof(info)); 669 670 rc = dpu_writeback_init(dev, encoder, wb_formats, 671 n_formats); 672 if (rc) { 673 DPU_ERROR("dpu_writeback_init, rc = %d\n", rc); 674 drm_encoder_cleanup(encoder); 675 return rc; 676 } 677 678 info.num_of_h_tiles = 1; 679 /* use only WB idx 2 instance for DPU */ 680 info.h_tile_instance[0] = WB_2; 681 info.intf_type = encoder->encoder_type; 682 683 rc = dpu_encoder_setup(dev, encoder, &info); 684 if (rc) { 685 DPU_ERROR("failed to setup DPU encoder %d: rc:%d\n", 686 encoder->base.id, rc); 687 return rc; 688 } 689 690 return 0; 691 } 692 693 /** 694 * _dpu_kms_setup_displays - create encoders, bridges and connectors 695 * for underlying displays 696 * @dev: Pointer to drm device structure 697 * @priv: Pointer to private drm device data 698 * @dpu_kms: Pointer to dpu kms structure 699 * Returns: Zero on success 700 */ 701 static int _dpu_kms_setup_displays(struct drm_device *dev, 702 struct msm_drm_private *priv, 703 struct dpu_kms *dpu_kms) 704 { 705 int rc = 0; 706 int i; 707 708 rc = _dpu_kms_initialize_dsi(dev, priv, dpu_kms); 709 if (rc) { 710 DPU_ERROR("initialize_dsi failed, rc = %d\n", rc); 711 return rc; 712 } 713 714 rc = _dpu_kms_initialize_displayport(dev, priv, dpu_kms); 715 if (rc) { 716 DPU_ERROR("initialize_DP failed, rc = %d\n", rc); 717 return rc; 718 } 719 720 /* Since WB isn't a driver check the catalog before initializing */ 721 if (dpu_kms->catalog->wb_count) { 722 for (i = 0; i < dpu_kms->catalog->wb_count; i++) { 723 if (dpu_kms->catalog->wb[i].id == WB_2) { 724 rc = _dpu_kms_initialize_writeback(dev, priv, dpu_kms, 725 dpu_kms->catalog->wb[i].format_list, 726 dpu_kms->catalog->wb[i].num_formats); 727 if (rc) { 728 DPU_ERROR("initialize_WB failed, rc = %d\n", rc); 729 return rc; 730 } 731 } 732 } 733 } 734 735 return rc; 736 } 737 738 #define MAX_PLANES 20 739 static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms) 740 { 741 struct drm_device *dev; 742 struct drm_plane *primary_planes[MAX_PLANES], *plane; 743 struct drm_plane *cursor_planes[MAX_PLANES] = { NULL }; 744 struct drm_crtc *crtc; 745 struct drm_encoder *encoder; 746 unsigned int num_encoders; 747 748 struct msm_drm_private *priv; 749 struct dpu_mdss_cfg *catalog; 750 751 int primary_planes_idx = 0, cursor_planes_idx = 0, i, ret; 752 int max_crtc_count; 753 dev = dpu_kms->dev; 754 priv = dev->dev_private; 755 catalog = dpu_kms->catalog; 756 757 /* 758 * Create encoder and query display drivers to create 759 * bridges and connectors 760 */ 761 ret = _dpu_kms_setup_displays(dev, priv, dpu_kms); 762 if (ret) 763 return ret; 764 765 num_encoders = 0; 766 drm_for_each_encoder(encoder, dev) 767 num_encoders++; 768 769 max_crtc_count = min(catalog->mixer_count, num_encoders); 770 771 /* Create the planes, keeping track of one primary/cursor per crtc */ 772 for (i = 0; i < catalog->sspp_count; i++) { 773 enum drm_plane_type type; 774 775 if ((catalog->sspp[i].features & BIT(DPU_SSPP_CURSOR)) 776 && cursor_planes_idx < max_crtc_count) 777 type = DRM_PLANE_TYPE_CURSOR; 778 else if (primary_planes_idx < max_crtc_count) 779 type = DRM_PLANE_TYPE_PRIMARY; 780 else 781 type = DRM_PLANE_TYPE_OVERLAY; 782 783 DPU_DEBUG("Create plane type %d with features %lx (cur %lx)\n", 784 type, catalog->sspp[i].features, 785 catalog->sspp[i].features & BIT(DPU_SSPP_CURSOR)); 786 787 plane = dpu_plane_init(dev, catalog->sspp[i].id, type, 788 (1UL << max_crtc_count) - 1, 0); 789 if (IS_ERR(plane)) { 790 DPU_ERROR("dpu_plane_init failed\n"); 791 ret = PTR_ERR(plane); 792 return ret; 793 } 794 795 if (type == DRM_PLANE_TYPE_CURSOR) 796 cursor_planes[cursor_planes_idx++] = plane; 797 else if (type == DRM_PLANE_TYPE_PRIMARY) 798 primary_planes[primary_planes_idx++] = plane; 799 } 800 801 max_crtc_count = min(max_crtc_count, primary_planes_idx); 802 803 /* Create one CRTC per encoder */ 804 for (i = 0; i < max_crtc_count; i++) { 805 crtc = dpu_crtc_init(dev, primary_planes[i], cursor_planes[i]); 806 if (IS_ERR(crtc)) { 807 ret = PTR_ERR(crtc); 808 return ret; 809 } 810 priv->crtcs[priv->num_crtcs++] = crtc; 811 } 812 813 /* All CRTCs are compatible with all encoders */ 814 drm_for_each_encoder(encoder, dev) 815 encoder->possible_crtcs = (1 << priv->num_crtcs) - 1; 816 817 return 0; 818 } 819 820 static void _dpu_kms_hw_destroy(struct dpu_kms *dpu_kms) 821 { 822 int i; 823 824 if (dpu_kms->hw_intr) 825 dpu_hw_intr_destroy(dpu_kms->hw_intr); 826 dpu_kms->hw_intr = NULL; 827 828 /* safe to call these more than once during shutdown */ 829 _dpu_kms_mmu_destroy(dpu_kms); 830 831 if (dpu_kms->catalog) { 832 for (i = 0; i < dpu_kms->catalog->vbif_count; i++) { 833 u32 vbif_idx = dpu_kms->catalog->vbif[i].id; 834 835 if ((vbif_idx < VBIF_MAX) && dpu_kms->hw_vbif[vbif_idx]) { 836 dpu_hw_vbif_destroy(dpu_kms->hw_vbif[vbif_idx]); 837 dpu_kms->hw_vbif[vbif_idx] = NULL; 838 } 839 } 840 } 841 842 if (dpu_kms->rm_init) 843 dpu_rm_destroy(&dpu_kms->rm); 844 dpu_kms->rm_init = false; 845 846 if (dpu_kms->catalog) 847 dpu_hw_catalog_deinit(dpu_kms->catalog); 848 dpu_kms->catalog = NULL; 849 850 if (dpu_kms->vbif[VBIF_NRT]) 851 devm_iounmap(&dpu_kms->pdev->dev, dpu_kms->vbif[VBIF_NRT]); 852 dpu_kms->vbif[VBIF_NRT] = NULL; 853 854 if (dpu_kms->vbif[VBIF_RT]) 855 devm_iounmap(&dpu_kms->pdev->dev, dpu_kms->vbif[VBIF_RT]); 856 dpu_kms->vbif[VBIF_RT] = NULL; 857 858 if (dpu_kms->hw_mdp) 859 dpu_hw_mdp_destroy(dpu_kms->hw_mdp); 860 dpu_kms->hw_mdp = NULL; 861 862 if (dpu_kms->mmio) 863 devm_iounmap(&dpu_kms->pdev->dev, dpu_kms->mmio); 864 dpu_kms->mmio = NULL; 865 } 866 867 static void dpu_kms_destroy(struct msm_kms *kms) 868 { 869 struct dpu_kms *dpu_kms; 870 871 if (!kms) { 872 DPU_ERROR("invalid kms\n"); 873 return; 874 } 875 876 dpu_kms = to_dpu_kms(kms); 877 878 _dpu_kms_hw_destroy(dpu_kms); 879 880 msm_kms_destroy(&dpu_kms->base); 881 882 if (dpu_kms->rpm_enabled) 883 pm_runtime_disable(&dpu_kms->pdev->dev); 884 } 885 886 static int dpu_irq_postinstall(struct msm_kms *kms) 887 { 888 struct msm_drm_private *priv; 889 struct dpu_kms *dpu_kms = to_dpu_kms(kms); 890 int i; 891 892 if (!dpu_kms || !dpu_kms->dev) 893 return -EINVAL; 894 895 priv = dpu_kms->dev->dev_private; 896 if (!priv) 897 return -EINVAL; 898 899 for (i = 0; i < ARRAY_SIZE(priv->dp); i++) 900 msm_dp_irq_postinstall(priv->dp[i]); 901 902 return 0; 903 } 904 905 static void dpu_kms_mdp_snapshot(struct msm_disp_state *disp_state, struct msm_kms *kms) 906 { 907 int i; 908 struct dpu_kms *dpu_kms; 909 struct dpu_mdss_cfg *cat; 910 struct dpu_hw_mdp *top; 911 912 dpu_kms = to_dpu_kms(kms); 913 914 cat = dpu_kms->catalog; 915 top = dpu_kms->hw_mdp; 916 917 pm_runtime_get_sync(&dpu_kms->pdev->dev); 918 919 /* dump CTL sub-blocks HW regs info */ 920 for (i = 0; i < cat->ctl_count; i++) 921 msm_disp_snapshot_add_block(disp_state, cat->ctl[i].len, 922 dpu_kms->mmio + cat->ctl[i].base, "ctl_%d", i); 923 924 /* dump DSPP sub-blocks HW regs info */ 925 for (i = 0; i < cat->dspp_count; i++) 926 msm_disp_snapshot_add_block(disp_state, cat->dspp[i].len, 927 dpu_kms->mmio + cat->dspp[i].base, "dspp_%d", i); 928 929 /* dump INTF sub-blocks HW regs info */ 930 for (i = 0; i < cat->intf_count; i++) 931 msm_disp_snapshot_add_block(disp_state, cat->intf[i].len, 932 dpu_kms->mmio + cat->intf[i].base, "intf_%d", i); 933 934 /* dump PP sub-blocks HW regs info */ 935 for (i = 0; i < cat->pingpong_count; i++) 936 msm_disp_snapshot_add_block(disp_state, cat->pingpong[i].len, 937 dpu_kms->mmio + cat->pingpong[i].base, "pingpong_%d", i); 938 939 /* dump SSPP sub-blocks HW regs info */ 940 for (i = 0; i < cat->sspp_count; i++) 941 msm_disp_snapshot_add_block(disp_state, cat->sspp[i].len, 942 dpu_kms->mmio + cat->sspp[i].base, "sspp_%d", i); 943 944 /* dump LM sub-blocks HW regs info */ 945 for (i = 0; i < cat->mixer_count; i++) 946 msm_disp_snapshot_add_block(disp_state, cat->mixer[i].len, 947 dpu_kms->mmio + cat->mixer[i].base, "lm_%d", i); 948 949 /* dump WB sub-blocks HW regs info */ 950 for (i = 0; i < cat->wb_count; i++) 951 msm_disp_snapshot_add_block(disp_state, cat->wb[i].len, 952 dpu_kms->mmio + cat->wb[i].base, "wb_%d", i); 953 954 msm_disp_snapshot_add_block(disp_state, top->hw.length, 955 dpu_kms->mmio + top->hw.blk_off, "top"); 956 957 pm_runtime_put_sync(&dpu_kms->pdev->dev); 958 } 959 960 static const struct msm_kms_funcs kms_funcs = { 961 .hw_init = dpu_kms_hw_init, 962 .irq_preinstall = dpu_core_irq_preinstall, 963 .irq_postinstall = dpu_irq_postinstall, 964 .irq_uninstall = dpu_core_irq_uninstall, 965 .irq = dpu_core_irq, 966 .enable_commit = dpu_kms_enable_commit, 967 .disable_commit = dpu_kms_disable_commit, 968 .vsync_time = dpu_kms_vsync_time, 969 .prepare_commit = dpu_kms_prepare_commit, 970 .flush_commit = dpu_kms_flush_commit, 971 .wait_flush = dpu_kms_wait_flush, 972 .complete_commit = dpu_kms_complete_commit, 973 .enable_vblank = dpu_kms_enable_vblank, 974 .disable_vblank = dpu_kms_disable_vblank, 975 .check_modified_format = dpu_format_check_modified_format, 976 .get_format = dpu_get_msm_format, 977 .destroy = dpu_kms_destroy, 978 .snapshot = dpu_kms_mdp_snapshot, 979 #ifdef CONFIG_DEBUG_FS 980 .debugfs_init = dpu_kms_debugfs_init, 981 #endif 982 }; 983 984 static void _dpu_kms_mmu_destroy(struct dpu_kms *dpu_kms) 985 { 986 struct msm_mmu *mmu; 987 988 if (!dpu_kms->base.aspace) 989 return; 990 991 mmu = dpu_kms->base.aspace->mmu; 992 993 mmu->funcs->detach(mmu); 994 msm_gem_address_space_put(dpu_kms->base.aspace); 995 996 dpu_kms->base.aspace = NULL; 997 } 998 999 static int _dpu_kms_mmu_init(struct dpu_kms *dpu_kms) 1000 { 1001 struct iommu_domain *domain; 1002 struct msm_gem_address_space *aspace; 1003 struct msm_mmu *mmu; 1004 struct device *dpu_dev = dpu_kms->dev->dev; 1005 struct device *mdss_dev = dpu_dev->parent; 1006 1007 domain = iommu_domain_alloc(&platform_bus_type); 1008 if (!domain) 1009 return 0; 1010 1011 /* IOMMUs are a part of MDSS device tree binding, not the 1012 * MDP/DPU device. */ 1013 mmu = msm_iommu_new(mdss_dev, domain); 1014 if (IS_ERR(mmu)) { 1015 iommu_domain_free(domain); 1016 return PTR_ERR(mmu); 1017 } 1018 aspace = msm_gem_address_space_create(mmu, "dpu1", 1019 0x1000, 0x100000000 - 0x1000); 1020 1021 if (IS_ERR(aspace)) { 1022 mmu->funcs->destroy(mmu); 1023 return PTR_ERR(aspace); 1024 } 1025 1026 dpu_kms->base.aspace = aspace; 1027 return 0; 1028 } 1029 1030 u64 dpu_kms_get_clk_rate(struct dpu_kms *dpu_kms, char *clock_name) 1031 { 1032 struct clk *clk; 1033 1034 clk = msm_clk_bulk_get_clock(dpu_kms->clocks, dpu_kms->num_clocks, clock_name); 1035 if (!clk) 1036 return -EINVAL; 1037 1038 return clk_get_rate(clk); 1039 } 1040 1041 static int dpu_kms_hw_init(struct msm_kms *kms) 1042 { 1043 struct dpu_kms *dpu_kms; 1044 struct drm_device *dev; 1045 int i, rc = -EINVAL; 1046 1047 if (!kms) { 1048 DPU_ERROR("invalid kms\n"); 1049 return rc; 1050 } 1051 1052 dpu_kms = to_dpu_kms(kms); 1053 dev = dpu_kms->dev; 1054 1055 rc = dpu_kms_global_obj_init(dpu_kms); 1056 if (rc) 1057 return rc; 1058 1059 atomic_set(&dpu_kms->bandwidth_ref, 0); 1060 1061 dpu_kms->mmio = msm_ioremap(dpu_kms->pdev, "mdp"); 1062 if (IS_ERR(dpu_kms->mmio)) { 1063 rc = PTR_ERR(dpu_kms->mmio); 1064 DPU_ERROR("mdp register memory map failed: %d\n", rc); 1065 dpu_kms->mmio = NULL; 1066 goto error; 1067 } 1068 DRM_DEBUG("mapped dpu address space @%pK\n", dpu_kms->mmio); 1069 1070 dpu_kms->vbif[VBIF_RT] = msm_ioremap(dpu_kms->pdev, "vbif"); 1071 if (IS_ERR(dpu_kms->vbif[VBIF_RT])) { 1072 rc = PTR_ERR(dpu_kms->vbif[VBIF_RT]); 1073 DPU_ERROR("vbif register memory map failed: %d\n", rc); 1074 dpu_kms->vbif[VBIF_RT] = NULL; 1075 goto error; 1076 } 1077 dpu_kms->vbif[VBIF_NRT] = msm_ioremap_quiet(dpu_kms->pdev, "vbif_nrt"); 1078 if (IS_ERR(dpu_kms->vbif[VBIF_NRT])) { 1079 dpu_kms->vbif[VBIF_NRT] = NULL; 1080 DPU_DEBUG("VBIF NRT is not defined"); 1081 } 1082 1083 dpu_kms->reg_dma = msm_ioremap_quiet(dpu_kms->pdev, "regdma"); 1084 if (IS_ERR(dpu_kms->reg_dma)) { 1085 dpu_kms->reg_dma = NULL; 1086 DPU_DEBUG("REG_DMA is not defined"); 1087 } 1088 1089 dpu_kms_parse_data_bus_icc_path(dpu_kms); 1090 1091 rc = pm_runtime_resume_and_get(&dpu_kms->pdev->dev); 1092 if (rc < 0) 1093 goto error; 1094 1095 dpu_kms->core_rev = readl_relaxed(dpu_kms->mmio + 0x0); 1096 1097 pr_info("dpu hardware revision:0x%x\n", dpu_kms->core_rev); 1098 1099 dpu_kms->catalog = dpu_hw_catalog_init(dpu_kms->core_rev); 1100 if (IS_ERR_OR_NULL(dpu_kms->catalog)) { 1101 rc = PTR_ERR(dpu_kms->catalog); 1102 if (!dpu_kms->catalog) 1103 rc = -EINVAL; 1104 DPU_ERROR("catalog init failed: %d\n", rc); 1105 dpu_kms->catalog = NULL; 1106 goto power_error; 1107 } 1108 1109 /* 1110 * Now we need to read the HW catalog and initialize resources such as 1111 * clocks, regulators, GDSC/MMAGIC, ioremap the register ranges etc 1112 */ 1113 rc = _dpu_kms_mmu_init(dpu_kms); 1114 if (rc) { 1115 DPU_ERROR("dpu_kms_mmu_init failed: %d\n", rc); 1116 goto power_error; 1117 } 1118 1119 rc = dpu_rm_init(&dpu_kms->rm, dpu_kms->catalog, dpu_kms->mmio); 1120 if (rc) { 1121 DPU_ERROR("rm init failed: %d\n", rc); 1122 goto power_error; 1123 } 1124 1125 dpu_kms->rm_init = true; 1126 1127 dpu_kms->hw_mdp = dpu_hw_mdptop_init(MDP_TOP, dpu_kms->mmio, 1128 dpu_kms->catalog); 1129 if (IS_ERR(dpu_kms->hw_mdp)) { 1130 rc = PTR_ERR(dpu_kms->hw_mdp); 1131 DPU_ERROR("failed to get hw_mdp: %d\n", rc); 1132 dpu_kms->hw_mdp = NULL; 1133 goto power_error; 1134 } 1135 1136 for (i = 0; i < dpu_kms->catalog->vbif_count; i++) { 1137 u32 vbif_idx = dpu_kms->catalog->vbif[i].id; 1138 1139 dpu_kms->hw_vbif[i] = dpu_hw_vbif_init(vbif_idx, 1140 dpu_kms->vbif[vbif_idx], dpu_kms->catalog); 1141 if (IS_ERR_OR_NULL(dpu_kms->hw_vbif[vbif_idx])) { 1142 rc = PTR_ERR(dpu_kms->hw_vbif[vbif_idx]); 1143 if (!dpu_kms->hw_vbif[vbif_idx]) 1144 rc = -EINVAL; 1145 DPU_ERROR("failed to init vbif %d: %d\n", vbif_idx, rc); 1146 dpu_kms->hw_vbif[vbif_idx] = NULL; 1147 goto power_error; 1148 } 1149 } 1150 1151 rc = dpu_core_perf_init(&dpu_kms->perf, dev, dpu_kms->catalog, 1152 msm_clk_bulk_get_clock(dpu_kms->clocks, dpu_kms->num_clocks, "core")); 1153 if (rc) { 1154 DPU_ERROR("failed to init perf %d\n", rc); 1155 goto perf_err; 1156 } 1157 1158 dpu_kms->hw_intr = dpu_hw_intr_init(dpu_kms->mmio, dpu_kms->catalog); 1159 if (IS_ERR_OR_NULL(dpu_kms->hw_intr)) { 1160 rc = PTR_ERR(dpu_kms->hw_intr); 1161 DPU_ERROR("hw_intr init failed: %d\n", rc); 1162 dpu_kms->hw_intr = NULL; 1163 goto hw_intr_init_err; 1164 } 1165 1166 dev->mode_config.min_width = 0; 1167 dev->mode_config.min_height = 0; 1168 1169 /* 1170 * max crtc width is equal to the max mixer width * 2 and max height is 1171 * is 4K 1172 */ 1173 dev->mode_config.max_width = 1174 dpu_kms->catalog->caps->max_mixer_width * 2; 1175 dev->mode_config.max_height = 4096; 1176 1177 dev->max_vblank_count = 0xffffffff; 1178 /* Disable vblank irqs aggressively for power-saving */ 1179 dev->vblank_disable_immediate = true; 1180 1181 /* 1182 * _dpu_kms_drm_obj_init should create the DRM related objects 1183 * i.e. CRTCs, planes, encoders, connectors and so forth 1184 */ 1185 rc = _dpu_kms_drm_obj_init(dpu_kms); 1186 if (rc) { 1187 DPU_ERROR("modeset init failed: %d\n", rc); 1188 goto drm_obj_init_err; 1189 } 1190 1191 dpu_vbif_init_memtypes(dpu_kms); 1192 1193 pm_runtime_put_sync(&dpu_kms->pdev->dev); 1194 1195 return 0; 1196 1197 drm_obj_init_err: 1198 dpu_core_perf_destroy(&dpu_kms->perf); 1199 hw_intr_init_err: 1200 perf_err: 1201 power_error: 1202 pm_runtime_put_sync(&dpu_kms->pdev->dev); 1203 error: 1204 _dpu_kms_hw_destroy(dpu_kms); 1205 1206 return rc; 1207 } 1208 1209 static int dpu_kms_init(struct drm_device *ddev) 1210 { 1211 struct msm_drm_private *priv = ddev->dev_private; 1212 struct device *dev = ddev->dev; 1213 struct platform_device *pdev = to_platform_device(dev); 1214 struct dpu_kms *dpu_kms; 1215 int irq; 1216 struct dev_pm_opp *opp; 1217 int ret = 0; 1218 unsigned long max_freq = ULONG_MAX; 1219 1220 dpu_kms = devm_kzalloc(&pdev->dev, sizeof(*dpu_kms), GFP_KERNEL); 1221 if (!dpu_kms) 1222 return -ENOMEM; 1223 1224 ret = devm_pm_opp_set_clkname(dev, "core"); 1225 if (ret) 1226 return ret; 1227 /* OPP table is optional */ 1228 ret = devm_pm_opp_of_add_table(dev); 1229 if (ret && ret != -ENODEV) { 1230 dev_err(dev, "invalid OPP table in device tree\n"); 1231 return ret; 1232 } 1233 1234 ret = devm_clk_bulk_get_all(&pdev->dev, &dpu_kms->clocks); 1235 if (ret < 0) { 1236 DPU_ERROR("failed to parse clocks, ret=%d\n", ret); 1237 return ret; 1238 } 1239 dpu_kms->num_clocks = ret; 1240 1241 opp = dev_pm_opp_find_freq_floor(dev, &max_freq); 1242 if (!IS_ERR(opp)) 1243 dev_pm_opp_put(opp); 1244 1245 dev_pm_opp_set_rate(dev, max_freq); 1246 1247 ret = msm_kms_init(&dpu_kms->base, &kms_funcs); 1248 if (ret) { 1249 DPU_ERROR("failed to init kms, ret=%d\n", ret); 1250 return ret; 1251 } 1252 dpu_kms->dev = ddev; 1253 dpu_kms->pdev = pdev; 1254 1255 pm_runtime_enable(&pdev->dev); 1256 dpu_kms->rpm_enabled = true; 1257 1258 priv->kms = &dpu_kms->base; 1259 1260 irq = irq_of_parse_and_map(dpu_kms->pdev->dev.of_node, 0); 1261 if (!irq) { 1262 DPU_ERROR("failed to get irq\n"); 1263 return -EINVAL; 1264 } 1265 dpu_kms->base.irq = irq; 1266 1267 return 0; 1268 } 1269 1270 static int dpu_dev_probe(struct platform_device *pdev) 1271 { 1272 return msm_drv_probe(&pdev->dev, dpu_kms_init); 1273 } 1274 1275 static int dpu_dev_remove(struct platform_device *pdev) 1276 { 1277 component_master_del(&pdev->dev, &msm_drm_ops); 1278 1279 return 0; 1280 } 1281 1282 static int __maybe_unused dpu_runtime_suspend(struct device *dev) 1283 { 1284 int i; 1285 struct platform_device *pdev = to_platform_device(dev); 1286 struct msm_drm_private *priv = platform_get_drvdata(pdev); 1287 struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms); 1288 1289 /* Drop the performance state vote */ 1290 dev_pm_opp_set_rate(dev, 0); 1291 clk_bulk_disable_unprepare(dpu_kms->num_clocks, dpu_kms->clocks); 1292 1293 for (i = 0; i < dpu_kms->num_paths; i++) 1294 icc_set_bw(dpu_kms->path[i], 0, 0); 1295 1296 return 0; 1297 } 1298 1299 static int __maybe_unused dpu_runtime_resume(struct device *dev) 1300 { 1301 int rc = -1; 1302 struct platform_device *pdev = to_platform_device(dev); 1303 struct msm_drm_private *priv = platform_get_drvdata(pdev); 1304 struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms); 1305 struct drm_encoder *encoder; 1306 struct drm_device *ddev; 1307 1308 ddev = dpu_kms->dev; 1309 1310 rc = clk_bulk_prepare_enable(dpu_kms->num_clocks, dpu_kms->clocks); 1311 if (rc) { 1312 DPU_ERROR("clock enable failed rc:%d\n", rc); 1313 return rc; 1314 } 1315 1316 dpu_vbif_init_memtypes(dpu_kms); 1317 1318 drm_for_each_encoder(encoder, ddev) 1319 dpu_encoder_virt_runtime_resume(encoder); 1320 1321 return rc; 1322 } 1323 1324 static const struct dev_pm_ops dpu_pm_ops = { 1325 SET_RUNTIME_PM_OPS(dpu_runtime_suspend, dpu_runtime_resume, NULL) 1326 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1327 pm_runtime_force_resume) 1328 .prepare = msm_pm_prepare, 1329 .complete = msm_pm_complete, 1330 }; 1331 1332 static const struct of_device_id dpu_dt_match[] = { 1333 { .compatible = "qcom,msm8998-dpu", }, 1334 { .compatible = "qcom,qcm2290-dpu", }, 1335 { .compatible = "qcom,sdm845-dpu", }, 1336 { .compatible = "qcom,sc7180-dpu", }, 1337 { .compatible = "qcom,sc7280-dpu", }, 1338 { .compatible = "qcom,sc8180x-dpu", }, 1339 { .compatible = "qcom,sm8150-dpu", }, 1340 { .compatible = "qcom,sm8250-dpu", }, 1341 {} 1342 }; 1343 MODULE_DEVICE_TABLE(of, dpu_dt_match); 1344 1345 static struct platform_driver dpu_driver = { 1346 .probe = dpu_dev_probe, 1347 .remove = dpu_dev_remove, 1348 .shutdown = msm_drv_shutdown, 1349 .driver = { 1350 .name = "msm_dpu", 1351 .of_match_table = dpu_dt_match, 1352 .pm = &dpu_pm_ops, 1353 }, 1354 }; 1355 1356 void __init msm_dpu_register(void) 1357 { 1358 platform_driver_register(&dpu_driver); 1359 } 1360 1361 void __exit msm_dpu_unregister(void) 1362 { 1363 platform_driver_unregister(&dpu_driver); 1364 } 1365