1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013 Red Hat 4 * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved. 5 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 6 * 7 * Author: Rob Clark <robdclark@gmail.com> 8 */ 9 10 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ 11 12 #include <linux/debugfs.h> 13 #include <linux/dma-buf.h> 14 #include <linux/of_irq.h> 15 #include <linux/pm_opp.h> 16 17 #include <drm/drm_crtc.h> 18 #include <drm/drm_file.h> 19 #include <drm/drm_framebuffer.h> 20 #include <drm/drm_vblank.h> 21 #include <drm/drm_writeback.h> 22 23 #include "msm_drv.h" 24 #include "msm_mmu.h" 25 #include "msm_gem.h" 26 #include "disp/msm_disp_snapshot.h" 27 28 #include "dpu_core_irq.h" 29 #include "dpu_crtc.h" 30 #include "dpu_encoder.h" 31 #include "dpu_formats.h" 32 #include "dpu_hw_vbif.h" 33 #include "dpu_kms.h" 34 #include "dpu_plane.h" 35 #include "dpu_vbif.h" 36 #include "dpu_writeback.h" 37 38 #define CREATE_TRACE_POINTS 39 #include "dpu_trace.h" 40 41 /* 42 * To enable overall DRM driver logging 43 * # echo 0x2 > /sys/module/drm/parameters/debug 44 * 45 * To enable DRM driver h/w logging 46 * # echo <mask> > /sys/kernel/debug/dri/0/debug/hw_log_mask 47 * 48 * See dpu_hw_mdss.h for h/w logging mask definitions (search for DPU_DBG_MASK_) 49 */ 50 #define DPU_DEBUGFS_DIR "msm_dpu" 51 #define DPU_DEBUGFS_HWMASKNAME "hw_log_mask" 52 53 static int dpu_kms_hw_init(struct msm_kms *kms); 54 static void _dpu_kms_mmu_destroy(struct dpu_kms *dpu_kms); 55 56 #ifdef CONFIG_DEBUG_FS 57 static int _dpu_danger_signal_status(struct seq_file *s, 58 bool danger_status) 59 { 60 struct dpu_danger_safe_status status; 61 struct dpu_kms *kms = s->private; 62 int i; 63 64 if (!kms->hw_mdp) { 65 DPU_ERROR("invalid arg(s)\n"); 66 return 0; 67 } 68 69 memset(&status, 0, sizeof(struct dpu_danger_safe_status)); 70 71 pm_runtime_get_sync(&kms->pdev->dev); 72 if (danger_status) { 73 seq_puts(s, "\nDanger signal status:\n"); 74 if (kms->hw_mdp->ops.get_danger_status) 75 kms->hw_mdp->ops.get_danger_status(kms->hw_mdp, 76 &status); 77 } else { 78 seq_puts(s, "\nSafe signal status:\n"); 79 if (kms->hw_mdp->ops.get_safe_status) 80 kms->hw_mdp->ops.get_safe_status(kms->hw_mdp, 81 &status); 82 } 83 pm_runtime_put_sync(&kms->pdev->dev); 84 85 seq_printf(s, "MDP : 0x%x\n", status.mdp); 86 87 for (i = SSPP_VIG0; i < SSPP_MAX; i++) 88 seq_printf(s, "SSPP%d : 0x%x \n", i - SSPP_VIG0, 89 status.sspp[i]); 90 seq_puts(s, "\n"); 91 92 return 0; 93 } 94 95 static int dpu_debugfs_danger_stats_show(struct seq_file *s, void *v) 96 { 97 return _dpu_danger_signal_status(s, true); 98 } 99 DEFINE_SHOW_ATTRIBUTE(dpu_debugfs_danger_stats); 100 101 static int dpu_debugfs_safe_stats_show(struct seq_file *s, void *v) 102 { 103 return _dpu_danger_signal_status(s, false); 104 } 105 DEFINE_SHOW_ATTRIBUTE(dpu_debugfs_safe_stats); 106 107 static ssize_t _dpu_plane_danger_read(struct file *file, 108 char __user *buff, size_t count, loff_t *ppos) 109 { 110 struct dpu_kms *kms = file->private_data; 111 int len; 112 char buf[40]; 113 114 len = scnprintf(buf, sizeof(buf), "%d\n", !kms->has_danger_ctrl); 115 116 return simple_read_from_buffer(buff, count, ppos, buf, len); 117 } 118 119 static void _dpu_plane_set_danger_state(struct dpu_kms *kms, bool enable) 120 { 121 struct drm_plane *plane; 122 123 drm_for_each_plane(plane, kms->dev) { 124 if (plane->fb && plane->state) { 125 dpu_plane_danger_signal_ctrl(plane, enable); 126 DPU_DEBUG("plane:%d img:%dx%d ", 127 plane->base.id, plane->fb->width, 128 plane->fb->height); 129 DPU_DEBUG("src[%d,%d,%d,%d] dst[%d,%d,%d,%d]\n", 130 plane->state->src_x >> 16, 131 plane->state->src_y >> 16, 132 plane->state->src_w >> 16, 133 plane->state->src_h >> 16, 134 plane->state->crtc_x, plane->state->crtc_y, 135 plane->state->crtc_w, plane->state->crtc_h); 136 } else { 137 DPU_DEBUG("Inactive plane:%d\n", plane->base.id); 138 } 139 } 140 } 141 142 static ssize_t _dpu_plane_danger_write(struct file *file, 143 const char __user *user_buf, size_t count, loff_t *ppos) 144 { 145 struct dpu_kms *kms = file->private_data; 146 int disable_panic; 147 int ret; 148 149 ret = kstrtouint_from_user(user_buf, count, 0, &disable_panic); 150 if (ret) 151 return ret; 152 153 if (disable_panic) { 154 /* Disable panic signal for all active pipes */ 155 DPU_DEBUG("Disabling danger:\n"); 156 _dpu_plane_set_danger_state(kms, false); 157 kms->has_danger_ctrl = false; 158 } else { 159 /* Enable panic signal for all active pipes */ 160 DPU_DEBUG("Enabling danger:\n"); 161 kms->has_danger_ctrl = true; 162 _dpu_plane_set_danger_state(kms, true); 163 } 164 165 return count; 166 } 167 168 static const struct file_operations dpu_plane_danger_enable = { 169 .open = simple_open, 170 .read = _dpu_plane_danger_read, 171 .write = _dpu_plane_danger_write, 172 }; 173 174 static void dpu_debugfs_danger_init(struct dpu_kms *dpu_kms, 175 struct dentry *parent) 176 { 177 struct dentry *entry = debugfs_create_dir("danger", parent); 178 179 debugfs_create_file("danger_status", 0600, entry, 180 dpu_kms, &dpu_debugfs_danger_stats_fops); 181 debugfs_create_file("safe_status", 0600, entry, 182 dpu_kms, &dpu_debugfs_safe_stats_fops); 183 debugfs_create_file("disable_danger", 0600, entry, 184 dpu_kms, &dpu_plane_danger_enable); 185 186 } 187 188 /* 189 * Companion structure for dpu_debugfs_create_regset32. 190 */ 191 struct dpu_debugfs_regset32 { 192 uint32_t offset; 193 uint32_t blk_len; 194 struct dpu_kms *dpu_kms; 195 }; 196 197 static int dpu_regset32_show(struct seq_file *s, void *data) 198 { 199 struct dpu_debugfs_regset32 *regset = s->private; 200 struct dpu_kms *dpu_kms = regset->dpu_kms; 201 void __iomem *base; 202 uint32_t i, addr; 203 204 if (!dpu_kms->mmio) 205 return 0; 206 207 base = dpu_kms->mmio + regset->offset; 208 209 /* insert padding spaces, if needed */ 210 if (regset->offset & 0xF) { 211 seq_printf(s, "[%x]", regset->offset & ~0xF); 212 for (i = 0; i < (regset->offset & 0xF); i += 4) 213 seq_puts(s, " "); 214 } 215 216 pm_runtime_get_sync(&dpu_kms->pdev->dev); 217 218 /* main register output */ 219 for (i = 0; i < regset->blk_len; i += 4) { 220 addr = regset->offset + i; 221 if ((addr & 0xF) == 0x0) 222 seq_printf(s, i ? "\n[%x]" : "[%x]", addr); 223 seq_printf(s, " %08x", readl_relaxed(base + i)); 224 } 225 seq_puts(s, "\n"); 226 pm_runtime_put_sync(&dpu_kms->pdev->dev); 227 228 return 0; 229 } 230 DEFINE_SHOW_ATTRIBUTE(dpu_regset32); 231 232 void dpu_debugfs_create_regset32(const char *name, umode_t mode, 233 void *parent, 234 uint32_t offset, uint32_t length, struct dpu_kms *dpu_kms) 235 { 236 struct dpu_debugfs_regset32 *regset; 237 238 if (WARN_ON(!name || !dpu_kms || !length)) 239 return; 240 241 regset = devm_kzalloc(&dpu_kms->pdev->dev, sizeof(*regset), GFP_KERNEL); 242 if (!regset) 243 return; 244 245 /* make sure offset is a multiple of 4 */ 246 regset->offset = round_down(offset, 4); 247 regset->blk_len = length; 248 regset->dpu_kms = dpu_kms; 249 250 debugfs_create_file(name, mode, parent, regset, &dpu_regset32_fops); 251 } 252 253 static void dpu_debugfs_sspp_init(struct dpu_kms *dpu_kms, struct dentry *debugfs_root) 254 { 255 struct dentry *entry = debugfs_create_dir("sspp", debugfs_root); 256 int i; 257 258 if (IS_ERR(entry)) 259 return; 260 261 for (i = SSPP_NONE; i < SSPP_MAX; i++) { 262 struct dpu_hw_sspp *hw = dpu_rm_get_sspp(&dpu_kms->rm, i); 263 264 if (!hw) 265 continue; 266 267 _dpu_hw_sspp_init_debugfs(hw, dpu_kms, entry); 268 } 269 } 270 271 static int dpu_kms_debugfs_init(struct msm_kms *kms, struct drm_minor *minor) 272 { 273 struct dpu_kms *dpu_kms = to_dpu_kms(kms); 274 void *p = dpu_hw_util_get_log_mask_ptr(); 275 struct dentry *entry; 276 struct drm_device *dev; 277 struct msm_drm_private *priv; 278 int i; 279 280 if (!p) 281 return -EINVAL; 282 283 /* Only create a set of debugfs for the primary node, ignore render nodes */ 284 if (minor->type != DRM_MINOR_PRIMARY) 285 return 0; 286 287 dev = dpu_kms->dev; 288 priv = dev->dev_private; 289 290 entry = debugfs_create_dir("debug", minor->debugfs_root); 291 292 debugfs_create_x32(DPU_DEBUGFS_HWMASKNAME, 0600, entry, p); 293 294 dpu_debugfs_danger_init(dpu_kms, entry); 295 dpu_debugfs_vbif_init(dpu_kms, entry); 296 dpu_debugfs_core_irq_init(dpu_kms, entry); 297 dpu_debugfs_sspp_init(dpu_kms, entry); 298 299 for (i = 0; i < ARRAY_SIZE(priv->dp); i++) { 300 if (priv->dp[i]) 301 msm_dp_debugfs_init(priv->dp[i], minor); 302 } 303 304 return dpu_core_perf_debugfs_init(dpu_kms, entry); 305 } 306 #endif 307 308 /* Global/shared object state funcs */ 309 310 /* 311 * This is a helper that returns the private state currently in operation. 312 * Note that this would return the "old_state" if called in the atomic check 313 * path, and the "new_state" after the atomic swap has been done. 314 */ 315 struct dpu_global_state * 316 dpu_kms_get_existing_global_state(struct dpu_kms *dpu_kms) 317 { 318 return to_dpu_global_state(dpu_kms->global_state.state); 319 } 320 321 /* 322 * This acquires the modeset lock set aside for global state, creates 323 * a new duplicated private object state. 324 */ 325 struct dpu_global_state *dpu_kms_get_global_state(struct drm_atomic_state *s) 326 { 327 struct msm_drm_private *priv = s->dev->dev_private; 328 struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms); 329 struct drm_private_state *priv_state; 330 int ret; 331 332 ret = drm_modeset_lock(&dpu_kms->global_state_lock, s->acquire_ctx); 333 if (ret) 334 return ERR_PTR(ret); 335 336 priv_state = drm_atomic_get_private_obj_state(s, 337 &dpu_kms->global_state); 338 if (IS_ERR(priv_state)) 339 return ERR_CAST(priv_state); 340 341 return to_dpu_global_state(priv_state); 342 } 343 344 static struct drm_private_state * 345 dpu_kms_global_duplicate_state(struct drm_private_obj *obj) 346 { 347 struct dpu_global_state *state; 348 349 state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL); 350 if (!state) 351 return NULL; 352 353 __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base); 354 355 return &state->base; 356 } 357 358 static void dpu_kms_global_destroy_state(struct drm_private_obj *obj, 359 struct drm_private_state *state) 360 { 361 struct dpu_global_state *dpu_state = to_dpu_global_state(state); 362 363 kfree(dpu_state); 364 } 365 366 static const struct drm_private_state_funcs dpu_kms_global_state_funcs = { 367 .atomic_duplicate_state = dpu_kms_global_duplicate_state, 368 .atomic_destroy_state = dpu_kms_global_destroy_state, 369 }; 370 371 static int dpu_kms_global_obj_init(struct dpu_kms *dpu_kms) 372 { 373 struct dpu_global_state *state; 374 375 drm_modeset_lock_init(&dpu_kms->global_state_lock); 376 377 state = kzalloc(sizeof(*state), GFP_KERNEL); 378 if (!state) 379 return -ENOMEM; 380 381 drm_atomic_private_obj_init(dpu_kms->dev, &dpu_kms->global_state, 382 &state->base, 383 &dpu_kms_global_state_funcs); 384 return 0; 385 } 386 387 static int dpu_kms_parse_data_bus_icc_path(struct dpu_kms *dpu_kms) 388 { 389 struct icc_path *path0; 390 struct icc_path *path1; 391 struct drm_device *dev = dpu_kms->dev; 392 struct device *dpu_dev = dev->dev; 393 394 path0 = msm_icc_get(dpu_dev, "mdp0-mem"); 395 path1 = msm_icc_get(dpu_dev, "mdp1-mem"); 396 397 if (IS_ERR_OR_NULL(path0)) 398 return PTR_ERR_OR_ZERO(path0); 399 400 dpu_kms->path[0] = path0; 401 dpu_kms->num_paths = 1; 402 403 if (!IS_ERR_OR_NULL(path1)) { 404 dpu_kms->path[1] = path1; 405 dpu_kms->num_paths++; 406 } 407 return 0; 408 } 409 410 static int dpu_kms_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc) 411 { 412 return dpu_crtc_vblank(crtc, true); 413 } 414 415 static void dpu_kms_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc) 416 { 417 dpu_crtc_vblank(crtc, false); 418 } 419 420 static void dpu_kms_enable_commit(struct msm_kms *kms) 421 { 422 struct dpu_kms *dpu_kms = to_dpu_kms(kms); 423 pm_runtime_get_sync(&dpu_kms->pdev->dev); 424 } 425 426 static void dpu_kms_disable_commit(struct msm_kms *kms) 427 { 428 struct dpu_kms *dpu_kms = to_dpu_kms(kms); 429 pm_runtime_put_sync(&dpu_kms->pdev->dev); 430 } 431 432 static void dpu_kms_flush_commit(struct msm_kms *kms, unsigned crtc_mask) 433 { 434 struct dpu_kms *dpu_kms = to_dpu_kms(kms); 435 struct drm_crtc *crtc; 436 437 for_each_crtc_mask(dpu_kms->dev, crtc, crtc_mask) { 438 if (!crtc->state->active) 439 continue; 440 441 trace_dpu_kms_commit(DRMID(crtc)); 442 dpu_crtc_commit_kickoff(crtc); 443 } 444 } 445 446 static void dpu_kms_complete_commit(struct msm_kms *kms, unsigned crtc_mask) 447 { 448 struct dpu_kms *dpu_kms = to_dpu_kms(kms); 449 struct drm_crtc *crtc; 450 451 DPU_ATRACE_BEGIN("kms_complete_commit"); 452 453 for_each_crtc_mask(dpu_kms->dev, crtc, crtc_mask) 454 dpu_crtc_complete_commit(crtc); 455 456 DPU_ATRACE_END("kms_complete_commit"); 457 } 458 459 static void dpu_kms_wait_for_commit_done(struct msm_kms *kms, 460 struct drm_crtc *crtc) 461 { 462 struct drm_encoder *encoder; 463 struct drm_device *dev; 464 int ret; 465 466 if (!kms || !crtc || !crtc->state) { 467 DPU_ERROR("invalid params\n"); 468 return; 469 } 470 471 dev = crtc->dev; 472 473 if (!crtc->state->enable) { 474 DPU_DEBUG("[crtc:%d] not enable\n", crtc->base.id); 475 return; 476 } 477 478 if (!drm_atomic_crtc_effectively_active(crtc->state)) { 479 DPU_DEBUG("[crtc:%d] not active\n", crtc->base.id); 480 return; 481 } 482 483 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 484 if (encoder->crtc != crtc) 485 continue; 486 /* 487 * Wait for post-flush if necessary to delay before 488 * plane_cleanup. For example, wait for vsync in case of video 489 * mode panels. This may be a no-op for command mode panels. 490 */ 491 trace_dpu_kms_wait_for_commit_done(DRMID(crtc)); 492 ret = dpu_encoder_wait_for_event(encoder, MSM_ENC_COMMIT_DONE); 493 if (ret && ret != -EWOULDBLOCK) { 494 DPU_ERROR("wait for commit done returned %d\n", ret); 495 break; 496 } 497 } 498 } 499 500 static void dpu_kms_wait_flush(struct msm_kms *kms, unsigned crtc_mask) 501 { 502 struct dpu_kms *dpu_kms = to_dpu_kms(kms); 503 struct drm_crtc *crtc; 504 505 for_each_crtc_mask(dpu_kms->dev, crtc, crtc_mask) 506 dpu_kms_wait_for_commit_done(kms, crtc); 507 } 508 509 static int _dpu_kms_initialize_dsi(struct drm_device *dev, 510 struct msm_drm_private *priv, 511 struct dpu_kms *dpu_kms) 512 { 513 struct drm_encoder *encoder = NULL; 514 struct msm_display_info info; 515 int i, rc = 0; 516 517 if (!(priv->dsi[0] || priv->dsi[1])) 518 return rc; 519 520 /* 521 * We support following confiurations: 522 * - Single DSI host (dsi0 or dsi1) 523 * - Two independent DSI hosts 524 * - Bonded DSI0 and DSI1 hosts 525 * 526 * TODO: Support swapping DSI0 and DSI1 in the bonded setup. 527 */ 528 for (i = 0; i < ARRAY_SIZE(priv->dsi); i++) { 529 int other = (i + 1) % 2; 530 531 if (!priv->dsi[i]) 532 continue; 533 534 if (msm_dsi_is_bonded_dsi(priv->dsi[i]) && 535 !msm_dsi_is_master_dsi(priv->dsi[i])) 536 continue; 537 538 memset(&info, 0, sizeof(info)); 539 info.intf_type = INTF_DSI; 540 541 info.h_tile_instance[info.num_of_h_tiles++] = i; 542 if (msm_dsi_is_bonded_dsi(priv->dsi[i])) 543 info.h_tile_instance[info.num_of_h_tiles++] = other; 544 545 info.is_cmd_mode = msm_dsi_is_cmd_mode(priv->dsi[i]); 546 547 encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_DSI, &info); 548 if (IS_ERR(encoder)) { 549 DPU_ERROR("encoder init failed for dsi display\n"); 550 return PTR_ERR(encoder); 551 } 552 553 rc = msm_dsi_modeset_init(priv->dsi[i], dev, encoder); 554 if (rc) { 555 DPU_ERROR("modeset_init failed for dsi[%d], rc = %d\n", 556 i, rc); 557 break; 558 } 559 560 if (msm_dsi_is_bonded_dsi(priv->dsi[i]) && priv->dsi[other]) { 561 rc = msm_dsi_modeset_init(priv->dsi[other], dev, encoder); 562 if (rc) { 563 DPU_ERROR("modeset_init failed for dsi[%d], rc = %d\n", 564 other, rc); 565 break; 566 } 567 } 568 } 569 570 return rc; 571 } 572 573 static int _dpu_kms_initialize_displayport(struct drm_device *dev, 574 struct msm_drm_private *priv, 575 struct dpu_kms *dpu_kms) 576 { 577 struct drm_encoder *encoder = NULL; 578 struct msm_display_info info; 579 int rc; 580 int i; 581 582 for (i = 0; i < ARRAY_SIZE(priv->dp); i++) { 583 if (!priv->dp[i]) 584 continue; 585 586 memset(&info, 0, sizeof(info)); 587 info.num_of_h_tiles = 1; 588 info.h_tile_instance[0] = i; 589 info.intf_type = INTF_DP; 590 591 encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_TMDS, &info); 592 if (IS_ERR(encoder)) { 593 DPU_ERROR("encoder init failed for dsi display\n"); 594 return PTR_ERR(encoder); 595 } 596 597 rc = msm_dp_modeset_init(priv->dp[i], dev, encoder); 598 if (rc) { 599 DPU_ERROR("modeset_init failed for DP, rc = %d\n", rc); 600 drm_encoder_cleanup(encoder); 601 return rc; 602 } 603 } 604 605 return 0; 606 } 607 608 static int _dpu_kms_initialize_hdmi(struct drm_device *dev, 609 struct msm_drm_private *priv, 610 struct dpu_kms *dpu_kms) 611 { 612 struct drm_encoder *encoder = NULL; 613 struct msm_display_info info; 614 int rc; 615 616 if (!priv->hdmi) 617 return 0; 618 619 memset(&info, 0, sizeof(info)); 620 info.num_of_h_tiles = 1; 621 info.h_tile_instance[0] = 0; 622 info.intf_type = INTF_HDMI; 623 624 encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_TMDS, &info); 625 if (IS_ERR(encoder)) { 626 DPU_ERROR("encoder init failed for HDMI display\n"); 627 return PTR_ERR(encoder); 628 } 629 630 rc = msm_hdmi_modeset_init(priv->hdmi, dev, encoder); 631 if (rc) { 632 DPU_ERROR("modeset_init failed for DP, rc = %d\n", rc); 633 drm_encoder_cleanup(encoder); 634 return rc; 635 } 636 637 return 0; 638 } 639 640 static int _dpu_kms_initialize_writeback(struct drm_device *dev, 641 struct msm_drm_private *priv, struct dpu_kms *dpu_kms, 642 const u32 *wb_formats, int n_formats) 643 { 644 struct drm_encoder *encoder = NULL; 645 struct msm_display_info info; 646 int rc; 647 648 memset(&info, 0, sizeof(info)); 649 650 info.num_of_h_tiles = 1; 651 /* use only WB idx 2 instance for DPU */ 652 info.h_tile_instance[0] = WB_2; 653 info.intf_type = INTF_WB; 654 655 encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_VIRTUAL, &info); 656 if (IS_ERR(encoder)) { 657 DPU_ERROR("encoder init failed for dsi display\n"); 658 return PTR_ERR(encoder); 659 } 660 661 rc = dpu_writeback_init(dev, encoder, wb_formats, 662 n_formats); 663 if (rc) { 664 DPU_ERROR("dpu_writeback_init, rc = %d\n", rc); 665 drm_encoder_cleanup(encoder); 666 return rc; 667 } 668 669 return 0; 670 } 671 672 /** 673 * _dpu_kms_setup_displays - create encoders, bridges and connectors 674 * for underlying displays 675 * @dev: Pointer to drm device structure 676 * @priv: Pointer to private drm device data 677 * @dpu_kms: Pointer to dpu kms structure 678 * Returns: Zero on success 679 */ 680 static int _dpu_kms_setup_displays(struct drm_device *dev, 681 struct msm_drm_private *priv, 682 struct dpu_kms *dpu_kms) 683 { 684 int rc = 0; 685 int i; 686 687 rc = _dpu_kms_initialize_dsi(dev, priv, dpu_kms); 688 if (rc) { 689 DPU_ERROR("initialize_dsi failed, rc = %d\n", rc); 690 return rc; 691 } 692 693 rc = _dpu_kms_initialize_displayport(dev, priv, dpu_kms); 694 if (rc) { 695 DPU_ERROR("initialize_DP failed, rc = %d\n", rc); 696 return rc; 697 } 698 699 rc = _dpu_kms_initialize_hdmi(dev, priv, dpu_kms); 700 if (rc) { 701 DPU_ERROR("initialize HDMI failed, rc = %d\n", rc); 702 return rc; 703 } 704 705 /* Since WB isn't a driver check the catalog before initializing */ 706 if (dpu_kms->catalog->wb_count) { 707 for (i = 0; i < dpu_kms->catalog->wb_count; i++) { 708 if (dpu_kms->catalog->wb[i].id == WB_2) { 709 rc = _dpu_kms_initialize_writeback(dev, priv, dpu_kms, 710 dpu_kms->catalog->wb[i].format_list, 711 dpu_kms->catalog->wb[i].num_formats); 712 if (rc) { 713 DPU_ERROR("initialize_WB failed, rc = %d\n", rc); 714 return rc; 715 } 716 } 717 } 718 } 719 720 return rc; 721 } 722 723 #define MAX_PLANES 20 724 static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms) 725 { 726 struct drm_device *dev; 727 struct drm_plane *primary_planes[MAX_PLANES], *plane; 728 struct drm_plane *cursor_planes[MAX_PLANES] = { NULL }; 729 struct drm_crtc *crtc; 730 struct drm_encoder *encoder; 731 unsigned int num_encoders; 732 733 struct msm_drm_private *priv; 734 const struct dpu_mdss_cfg *catalog; 735 736 int primary_planes_idx = 0, cursor_planes_idx = 0, i, ret; 737 int max_crtc_count; 738 dev = dpu_kms->dev; 739 priv = dev->dev_private; 740 catalog = dpu_kms->catalog; 741 742 /* 743 * Create encoder and query display drivers to create 744 * bridges and connectors 745 */ 746 ret = _dpu_kms_setup_displays(dev, priv, dpu_kms); 747 if (ret) 748 return ret; 749 750 num_encoders = 0; 751 drm_for_each_encoder(encoder, dev) 752 num_encoders++; 753 754 max_crtc_count = min(catalog->mixer_count, num_encoders); 755 756 /* Create the planes, keeping track of one primary/cursor per crtc */ 757 for (i = 0; i < catalog->sspp_count; i++) { 758 enum drm_plane_type type; 759 760 if ((catalog->sspp[i].features & BIT(DPU_SSPP_CURSOR)) 761 && cursor_planes_idx < max_crtc_count) 762 type = DRM_PLANE_TYPE_CURSOR; 763 else if (primary_planes_idx < max_crtc_count) 764 type = DRM_PLANE_TYPE_PRIMARY; 765 else 766 type = DRM_PLANE_TYPE_OVERLAY; 767 768 DPU_DEBUG("Create plane type %d with features %lx (cur %lx)\n", 769 type, catalog->sspp[i].features, 770 catalog->sspp[i].features & BIT(DPU_SSPP_CURSOR)); 771 772 plane = dpu_plane_init(dev, catalog->sspp[i].id, type, 773 (1UL << max_crtc_count) - 1); 774 if (IS_ERR(plane)) { 775 DPU_ERROR("dpu_plane_init failed\n"); 776 ret = PTR_ERR(plane); 777 return ret; 778 } 779 780 if (type == DRM_PLANE_TYPE_CURSOR) 781 cursor_planes[cursor_planes_idx++] = plane; 782 else if (type == DRM_PLANE_TYPE_PRIMARY) 783 primary_planes[primary_planes_idx++] = plane; 784 } 785 786 max_crtc_count = min(max_crtc_count, primary_planes_idx); 787 788 /* Create one CRTC per encoder */ 789 for (i = 0; i < max_crtc_count; i++) { 790 crtc = dpu_crtc_init(dev, primary_planes[i], cursor_planes[i]); 791 if (IS_ERR(crtc)) { 792 ret = PTR_ERR(crtc); 793 return ret; 794 } 795 priv->num_crtcs++; 796 } 797 798 /* All CRTCs are compatible with all encoders */ 799 drm_for_each_encoder(encoder, dev) 800 encoder->possible_crtcs = (1 << priv->num_crtcs) - 1; 801 802 return 0; 803 } 804 805 static void _dpu_kms_hw_destroy(struct dpu_kms *dpu_kms) 806 { 807 int i; 808 809 if (dpu_kms->hw_intr) 810 dpu_hw_intr_destroy(dpu_kms->hw_intr); 811 dpu_kms->hw_intr = NULL; 812 813 /* safe to call these more than once during shutdown */ 814 _dpu_kms_mmu_destroy(dpu_kms); 815 816 if (dpu_kms->catalog) { 817 for (i = 0; i < ARRAY_SIZE(dpu_kms->hw_vbif); i++) { 818 if (dpu_kms->hw_vbif[i]) { 819 dpu_hw_vbif_destroy(dpu_kms->hw_vbif[i]); 820 dpu_kms->hw_vbif[i] = NULL; 821 } 822 } 823 } 824 825 if (dpu_kms->rm_init) 826 dpu_rm_destroy(&dpu_kms->rm); 827 dpu_kms->rm_init = false; 828 829 dpu_kms->catalog = NULL; 830 831 if (dpu_kms->vbif[VBIF_NRT]) 832 devm_iounmap(&dpu_kms->pdev->dev, dpu_kms->vbif[VBIF_NRT]); 833 dpu_kms->vbif[VBIF_NRT] = NULL; 834 835 if (dpu_kms->vbif[VBIF_RT]) 836 devm_iounmap(&dpu_kms->pdev->dev, dpu_kms->vbif[VBIF_RT]); 837 dpu_kms->vbif[VBIF_RT] = NULL; 838 839 if (dpu_kms->hw_mdp) 840 dpu_hw_mdp_destroy(dpu_kms->hw_mdp); 841 dpu_kms->hw_mdp = NULL; 842 843 if (dpu_kms->mmio) 844 devm_iounmap(&dpu_kms->pdev->dev, dpu_kms->mmio); 845 dpu_kms->mmio = NULL; 846 } 847 848 static void dpu_kms_destroy(struct msm_kms *kms) 849 { 850 struct dpu_kms *dpu_kms; 851 852 if (!kms) { 853 DPU_ERROR("invalid kms\n"); 854 return; 855 } 856 857 dpu_kms = to_dpu_kms(kms); 858 859 _dpu_kms_hw_destroy(dpu_kms); 860 861 msm_kms_destroy(&dpu_kms->base); 862 863 if (dpu_kms->rpm_enabled) 864 pm_runtime_disable(&dpu_kms->pdev->dev); 865 } 866 867 static int dpu_irq_postinstall(struct msm_kms *kms) 868 { 869 struct msm_drm_private *priv; 870 struct dpu_kms *dpu_kms = to_dpu_kms(kms); 871 int i; 872 873 if (!dpu_kms || !dpu_kms->dev) 874 return -EINVAL; 875 876 priv = dpu_kms->dev->dev_private; 877 if (!priv) 878 return -EINVAL; 879 880 for (i = 0; i < ARRAY_SIZE(priv->dp); i++) 881 msm_dp_irq_postinstall(priv->dp[i]); 882 883 return 0; 884 } 885 886 static void dpu_kms_mdp_snapshot(struct msm_disp_state *disp_state, struct msm_kms *kms) 887 { 888 int i; 889 struct dpu_kms *dpu_kms; 890 const struct dpu_mdss_cfg *cat; 891 892 dpu_kms = to_dpu_kms(kms); 893 894 cat = dpu_kms->catalog; 895 896 pm_runtime_get_sync(&dpu_kms->pdev->dev); 897 898 /* dump CTL sub-blocks HW regs info */ 899 for (i = 0; i < cat->ctl_count; i++) 900 msm_disp_snapshot_add_block(disp_state, cat->ctl[i].len, 901 dpu_kms->mmio + cat->ctl[i].base, "ctl_%d", i); 902 903 /* dump DSPP sub-blocks HW regs info */ 904 for (i = 0; i < cat->dspp_count; i++) 905 msm_disp_snapshot_add_block(disp_state, cat->dspp[i].len, 906 dpu_kms->mmio + cat->dspp[i].base, "dspp_%d", i); 907 908 /* dump INTF sub-blocks HW regs info */ 909 for (i = 0; i < cat->intf_count; i++) 910 msm_disp_snapshot_add_block(disp_state, cat->intf[i].len, 911 dpu_kms->mmio + cat->intf[i].base, "intf_%d", i); 912 913 /* dump PP sub-blocks HW regs info */ 914 for (i = 0; i < cat->pingpong_count; i++) 915 msm_disp_snapshot_add_block(disp_state, cat->pingpong[i].len, 916 dpu_kms->mmio + cat->pingpong[i].base, "pingpong_%d", i); 917 918 /* dump SSPP sub-blocks HW regs info */ 919 for (i = 0; i < cat->sspp_count; i++) 920 msm_disp_snapshot_add_block(disp_state, cat->sspp[i].len, 921 dpu_kms->mmio + cat->sspp[i].base, "sspp_%d", i); 922 923 /* dump LM sub-blocks HW regs info */ 924 for (i = 0; i < cat->mixer_count; i++) 925 msm_disp_snapshot_add_block(disp_state, cat->mixer[i].len, 926 dpu_kms->mmio + cat->mixer[i].base, "lm_%d", i); 927 928 /* dump WB sub-blocks HW regs info */ 929 for (i = 0; i < cat->wb_count; i++) 930 msm_disp_snapshot_add_block(disp_state, cat->wb[i].len, 931 dpu_kms->mmio + cat->wb[i].base, "wb_%d", i); 932 933 if (cat->mdp[0].features & BIT(DPU_MDP_PERIPH_0_REMOVED)) { 934 msm_disp_snapshot_add_block(disp_state, MDP_PERIPH_TOP0, 935 dpu_kms->mmio + cat->mdp[0].base, "top"); 936 msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len - MDP_PERIPH_TOP0_END, 937 dpu_kms->mmio + cat->mdp[0].base + MDP_PERIPH_TOP0_END, "top_2"); 938 } else { 939 msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len, 940 dpu_kms->mmio + cat->mdp[0].base, "top"); 941 } 942 943 /* dump DSC sub-blocks HW regs info */ 944 for (i = 0; i < cat->dsc_count; i++) 945 msm_disp_snapshot_add_block(disp_state, cat->dsc[i].len, 946 dpu_kms->mmio + cat->dsc[i].base, "dsc_%d", i); 947 948 pm_runtime_put_sync(&dpu_kms->pdev->dev); 949 } 950 951 static const struct msm_kms_funcs kms_funcs = { 952 .hw_init = dpu_kms_hw_init, 953 .irq_preinstall = dpu_core_irq_preinstall, 954 .irq_postinstall = dpu_irq_postinstall, 955 .irq_uninstall = dpu_core_irq_uninstall, 956 .irq = dpu_core_irq, 957 .enable_commit = dpu_kms_enable_commit, 958 .disable_commit = dpu_kms_disable_commit, 959 .flush_commit = dpu_kms_flush_commit, 960 .wait_flush = dpu_kms_wait_flush, 961 .complete_commit = dpu_kms_complete_commit, 962 .enable_vblank = dpu_kms_enable_vblank, 963 .disable_vblank = dpu_kms_disable_vblank, 964 .check_modified_format = dpu_format_check_modified_format, 965 .get_format = dpu_get_msm_format, 966 .destroy = dpu_kms_destroy, 967 .snapshot = dpu_kms_mdp_snapshot, 968 #ifdef CONFIG_DEBUG_FS 969 .debugfs_init = dpu_kms_debugfs_init, 970 #endif 971 }; 972 973 static void _dpu_kms_mmu_destroy(struct dpu_kms *dpu_kms) 974 { 975 struct msm_mmu *mmu; 976 977 if (!dpu_kms->base.aspace) 978 return; 979 980 mmu = dpu_kms->base.aspace->mmu; 981 982 mmu->funcs->detach(mmu); 983 msm_gem_address_space_put(dpu_kms->base.aspace); 984 985 dpu_kms->base.aspace = NULL; 986 } 987 988 static int _dpu_kms_mmu_init(struct dpu_kms *dpu_kms) 989 { 990 struct msm_gem_address_space *aspace; 991 992 aspace = msm_kms_init_aspace(dpu_kms->dev); 993 if (IS_ERR(aspace)) 994 return PTR_ERR(aspace); 995 996 dpu_kms->base.aspace = aspace; 997 998 return 0; 999 } 1000 1001 unsigned long dpu_kms_get_clk_rate(struct dpu_kms *dpu_kms, char *clock_name) 1002 { 1003 struct clk *clk; 1004 1005 clk = msm_clk_bulk_get_clock(dpu_kms->clocks, dpu_kms->num_clocks, clock_name); 1006 if (!clk) 1007 return 0; 1008 1009 return clk_get_rate(clk); 1010 } 1011 1012 static int dpu_kms_hw_init(struct msm_kms *kms) 1013 { 1014 struct dpu_kms *dpu_kms; 1015 struct drm_device *dev; 1016 int i, rc = -EINVAL; 1017 u32 core_rev; 1018 1019 if (!kms) { 1020 DPU_ERROR("invalid kms\n"); 1021 return rc; 1022 } 1023 1024 dpu_kms = to_dpu_kms(kms); 1025 dev = dpu_kms->dev; 1026 1027 dev->mode_config.cursor_width = 512; 1028 dev->mode_config.cursor_height = 512; 1029 1030 rc = dpu_kms_global_obj_init(dpu_kms); 1031 if (rc) 1032 return rc; 1033 1034 atomic_set(&dpu_kms->bandwidth_ref, 0); 1035 1036 dpu_kms->mmio = msm_ioremap(dpu_kms->pdev, "mdp"); 1037 if (IS_ERR(dpu_kms->mmio)) { 1038 rc = PTR_ERR(dpu_kms->mmio); 1039 DPU_ERROR("mdp register memory map failed: %d\n", rc); 1040 dpu_kms->mmio = NULL; 1041 goto error; 1042 } 1043 DRM_DEBUG("mapped dpu address space @%pK\n", dpu_kms->mmio); 1044 1045 dpu_kms->vbif[VBIF_RT] = msm_ioremap(dpu_kms->pdev, "vbif"); 1046 if (IS_ERR(dpu_kms->vbif[VBIF_RT])) { 1047 rc = PTR_ERR(dpu_kms->vbif[VBIF_RT]); 1048 DPU_ERROR("vbif register memory map failed: %d\n", rc); 1049 dpu_kms->vbif[VBIF_RT] = NULL; 1050 goto error; 1051 } 1052 dpu_kms->vbif[VBIF_NRT] = msm_ioremap_quiet(dpu_kms->pdev, "vbif_nrt"); 1053 if (IS_ERR(dpu_kms->vbif[VBIF_NRT])) { 1054 dpu_kms->vbif[VBIF_NRT] = NULL; 1055 DPU_DEBUG("VBIF NRT is not defined"); 1056 } 1057 1058 dpu_kms_parse_data_bus_icc_path(dpu_kms); 1059 1060 rc = pm_runtime_resume_and_get(&dpu_kms->pdev->dev); 1061 if (rc < 0) 1062 goto error; 1063 1064 core_rev = readl_relaxed(dpu_kms->mmio + 0x0); 1065 1066 pr_info("dpu hardware revision:0x%x\n", core_rev); 1067 1068 dpu_kms->catalog = of_device_get_match_data(dev->dev); 1069 if (!dpu_kms->catalog) { 1070 DPU_ERROR("device config not known!\n"); 1071 rc = -EINVAL; 1072 goto power_error; 1073 } 1074 1075 /* 1076 * Now we need to read the HW catalog and initialize resources such as 1077 * clocks, regulators, GDSC/MMAGIC, ioremap the register ranges etc 1078 */ 1079 rc = _dpu_kms_mmu_init(dpu_kms); 1080 if (rc) { 1081 DPU_ERROR("dpu_kms_mmu_init failed: %d\n", rc); 1082 goto power_error; 1083 } 1084 1085 rc = dpu_rm_init(&dpu_kms->rm, dpu_kms->catalog, dpu_kms->mmio); 1086 if (rc) { 1087 DPU_ERROR("rm init failed: %d\n", rc); 1088 goto power_error; 1089 } 1090 1091 dpu_kms->rm_init = true; 1092 1093 dpu_kms->hw_mdp = dpu_hw_mdptop_init(dpu_kms->catalog->mdp, 1094 dpu_kms->mmio, 1095 dpu_kms->catalog); 1096 if (IS_ERR(dpu_kms->hw_mdp)) { 1097 rc = PTR_ERR(dpu_kms->hw_mdp); 1098 DPU_ERROR("failed to get hw_mdp: %d\n", rc); 1099 dpu_kms->hw_mdp = NULL; 1100 goto power_error; 1101 } 1102 1103 for (i = 0; i < dpu_kms->catalog->vbif_count; i++) { 1104 struct dpu_hw_vbif *hw; 1105 const struct dpu_vbif_cfg *vbif = &dpu_kms->catalog->vbif[i]; 1106 1107 hw = dpu_hw_vbif_init(vbif, dpu_kms->vbif[vbif->id]); 1108 if (IS_ERR(hw)) { 1109 rc = PTR_ERR(hw); 1110 DPU_ERROR("failed to init vbif %d: %d\n", vbif->id, rc); 1111 goto power_error; 1112 } 1113 1114 dpu_kms->hw_vbif[vbif->id] = hw; 1115 } 1116 1117 rc = dpu_core_perf_init(&dpu_kms->perf, dev, dpu_kms->catalog, 1118 msm_clk_bulk_get_clock(dpu_kms->clocks, dpu_kms->num_clocks, "core")); 1119 if (rc) { 1120 DPU_ERROR("failed to init perf %d\n", rc); 1121 goto perf_err; 1122 } 1123 1124 dpu_kms->hw_intr = dpu_hw_intr_init(dpu_kms->mmio, dpu_kms->catalog); 1125 if (IS_ERR_OR_NULL(dpu_kms->hw_intr)) { 1126 rc = PTR_ERR(dpu_kms->hw_intr); 1127 DPU_ERROR("hw_intr init failed: %d\n", rc); 1128 dpu_kms->hw_intr = NULL; 1129 goto hw_intr_init_err; 1130 } 1131 1132 dev->mode_config.min_width = 0; 1133 dev->mode_config.min_height = 0; 1134 1135 /* 1136 * max crtc width is equal to the max mixer width * 2 and max height is 1137 * is 4K 1138 */ 1139 dev->mode_config.max_width = 1140 dpu_kms->catalog->caps->max_mixer_width * 2; 1141 dev->mode_config.max_height = 4096; 1142 1143 dev->max_vblank_count = 0xffffffff; 1144 /* Disable vblank irqs aggressively for power-saving */ 1145 dev->vblank_disable_immediate = true; 1146 1147 /* 1148 * _dpu_kms_drm_obj_init should create the DRM related objects 1149 * i.e. CRTCs, planes, encoders, connectors and so forth 1150 */ 1151 rc = _dpu_kms_drm_obj_init(dpu_kms); 1152 if (rc) { 1153 DPU_ERROR("modeset init failed: %d\n", rc); 1154 goto drm_obj_init_err; 1155 } 1156 1157 dpu_vbif_init_memtypes(dpu_kms); 1158 1159 pm_runtime_put_sync(&dpu_kms->pdev->dev); 1160 1161 return 0; 1162 1163 drm_obj_init_err: 1164 dpu_core_perf_destroy(&dpu_kms->perf); 1165 hw_intr_init_err: 1166 perf_err: 1167 power_error: 1168 pm_runtime_put_sync(&dpu_kms->pdev->dev); 1169 error: 1170 _dpu_kms_hw_destroy(dpu_kms); 1171 1172 return rc; 1173 } 1174 1175 static int dpu_kms_init(struct drm_device *ddev) 1176 { 1177 struct msm_drm_private *priv = ddev->dev_private; 1178 struct device *dev = ddev->dev; 1179 struct platform_device *pdev = to_platform_device(dev); 1180 struct dpu_kms *dpu_kms; 1181 int irq; 1182 struct dev_pm_opp *opp; 1183 int ret = 0; 1184 unsigned long max_freq = ULONG_MAX; 1185 1186 dpu_kms = devm_kzalloc(&pdev->dev, sizeof(*dpu_kms), GFP_KERNEL); 1187 if (!dpu_kms) 1188 return -ENOMEM; 1189 1190 ret = devm_pm_opp_set_clkname(dev, "core"); 1191 if (ret) 1192 return ret; 1193 /* OPP table is optional */ 1194 ret = devm_pm_opp_of_add_table(dev); 1195 if (ret && ret != -ENODEV) { 1196 dev_err(dev, "invalid OPP table in device tree\n"); 1197 return ret; 1198 } 1199 1200 ret = devm_clk_bulk_get_all(&pdev->dev, &dpu_kms->clocks); 1201 if (ret < 0) { 1202 DPU_ERROR("failed to parse clocks, ret=%d\n", ret); 1203 return ret; 1204 } 1205 dpu_kms->num_clocks = ret; 1206 1207 opp = dev_pm_opp_find_freq_floor(dev, &max_freq); 1208 if (!IS_ERR(opp)) 1209 dev_pm_opp_put(opp); 1210 1211 dev_pm_opp_set_rate(dev, max_freq); 1212 1213 ret = msm_kms_init(&dpu_kms->base, &kms_funcs); 1214 if (ret) { 1215 DPU_ERROR("failed to init kms, ret=%d\n", ret); 1216 return ret; 1217 } 1218 dpu_kms->dev = ddev; 1219 dpu_kms->pdev = pdev; 1220 1221 pm_runtime_enable(&pdev->dev); 1222 dpu_kms->rpm_enabled = true; 1223 1224 priv->kms = &dpu_kms->base; 1225 1226 irq = irq_of_parse_and_map(dpu_kms->pdev->dev.of_node, 0); 1227 if (!irq) { 1228 DPU_ERROR("failed to get irq\n"); 1229 return -EINVAL; 1230 } 1231 dpu_kms->base.irq = irq; 1232 1233 return 0; 1234 } 1235 1236 static int dpu_dev_probe(struct platform_device *pdev) 1237 { 1238 return msm_drv_probe(&pdev->dev, dpu_kms_init); 1239 } 1240 1241 static int dpu_dev_remove(struct platform_device *pdev) 1242 { 1243 component_master_del(&pdev->dev, &msm_drm_ops); 1244 1245 return 0; 1246 } 1247 1248 static int __maybe_unused dpu_runtime_suspend(struct device *dev) 1249 { 1250 int i; 1251 struct platform_device *pdev = to_platform_device(dev); 1252 struct msm_drm_private *priv = platform_get_drvdata(pdev); 1253 struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms); 1254 1255 /* Drop the performance state vote */ 1256 dev_pm_opp_set_rate(dev, 0); 1257 clk_bulk_disable_unprepare(dpu_kms->num_clocks, dpu_kms->clocks); 1258 1259 for (i = 0; i < dpu_kms->num_paths; i++) 1260 icc_set_bw(dpu_kms->path[i], 0, 0); 1261 1262 return 0; 1263 } 1264 1265 static int __maybe_unused dpu_runtime_resume(struct device *dev) 1266 { 1267 int rc = -1; 1268 struct platform_device *pdev = to_platform_device(dev); 1269 struct msm_drm_private *priv = platform_get_drvdata(pdev); 1270 struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms); 1271 struct drm_encoder *encoder; 1272 struct drm_device *ddev; 1273 1274 ddev = dpu_kms->dev; 1275 1276 rc = clk_bulk_prepare_enable(dpu_kms->num_clocks, dpu_kms->clocks); 1277 if (rc) { 1278 DPU_ERROR("clock enable failed rc:%d\n", rc); 1279 return rc; 1280 } 1281 1282 dpu_vbif_init_memtypes(dpu_kms); 1283 1284 drm_for_each_encoder(encoder, ddev) 1285 dpu_encoder_virt_runtime_resume(encoder); 1286 1287 return rc; 1288 } 1289 1290 static const struct dev_pm_ops dpu_pm_ops = { 1291 SET_RUNTIME_PM_OPS(dpu_runtime_suspend, dpu_runtime_resume, NULL) 1292 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1293 pm_runtime_force_resume) 1294 .prepare = msm_pm_prepare, 1295 .complete = msm_pm_complete, 1296 }; 1297 1298 static const struct of_device_id dpu_dt_match[] = { 1299 { .compatible = "qcom,msm8998-dpu", .data = &dpu_msm8998_cfg, }, 1300 { .compatible = "qcom,qcm2290-dpu", .data = &dpu_qcm2290_cfg, }, 1301 { .compatible = "qcom,sdm845-dpu", .data = &dpu_sdm845_cfg, }, 1302 { .compatible = "qcom,sc7180-dpu", .data = &dpu_sc7180_cfg, }, 1303 { .compatible = "qcom,sc7280-dpu", .data = &dpu_sc7280_cfg, }, 1304 { .compatible = "qcom,sc8180x-dpu", .data = &dpu_sc8180x_cfg, }, 1305 { .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, }, 1306 { .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, }, 1307 { .compatible = "qcom,sm6350-dpu", .data = &dpu_sm6350_cfg, }, 1308 { .compatible = "qcom,sm6375-dpu", .data = &dpu_sm6375_cfg, }, 1309 { .compatible = "qcom,sm8150-dpu", .data = &dpu_sm8150_cfg, }, 1310 { .compatible = "qcom,sm8250-dpu", .data = &dpu_sm8250_cfg, }, 1311 { .compatible = "qcom,sm8350-dpu", .data = &dpu_sm8350_cfg, }, 1312 { .compatible = "qcom,sm8450-dpu", .data = &dpu_sm8450_cfg, }, 1313 { .compatible = "qcom,sm8550-dpu", .data = &dpu_sm8550_cfg, }, 1314 {} 1315 }; 1316 MODULE_DEVICE_TABLE(of, dpu_dt_match); 1317 1318 static struct platform_driver dpu_driver = { 1319 .probe = dpu_dev_probe, 1320 .remove = dpu_dev_remove, 1321 .shutdown = msm_drv_shutdown, 1322 .driver = { 1323 .name = "msm_dpu", 1324 .of_match_table = dpu_dt_match, 1325 .pm = &dpu_pm_ops, 1326 }, 1327 }; 1328 1329 void __init msm_dpu_register(void) 1330 { 1331 platform_driver_register(&dpu_driver); 1332 } 1333 1334 void __exit msm_dpu_unregister(void) 1335 { 1336 platform_driver_unregister(&dpu_driver); 1337 } 1338