1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ 9 10 #include <linux/debugfs.h> 11 #include <linux/dma-buf.h> 12 #include <linux/of_irq.h> 13 #include <linux/pm_opp.h> 14 15 #include <drm/drm_crtc.h> 16 #include <drm/drm_file.h> 17 #include <drm/drm_vblank.h> 18 19 #include "msm_drv.h" 20 #include "msm_mmu.h" 21 #include "msm_gem.h" 22 #include "disp/msm_disp_snapshot.h" 23 24 #include "dpu_core_irq.h" 25 #include "dpu_crtc.h" 26 #include "dpu_encoder.h" 27 #include "dpu_formats.h" 28 #include "dpu_hw_vbif.h" 29 #include "dpu_kms.h" 30 #include "dpu_plane.h" 31 #include "dpu_vbif.h" 32 33 #define CREATE_TRACE_POINTS 34 #include "dpu_trace.h" 35 36 /* 37 * To enable overall DRM driver logging 38 * # echo 0x2 > /sys/module/drm/parameters/debug 39 * 40 * To enable DRM driver h/w logging 41 * # echo <mask> > /sys/kernel/debug/dri/0/debug/hw_log_mask 42 * 43 * See dpu_hw_mdss.h for h/w logging mask definitions (search for DPU_DBG_MASK_) 44 */ 45 #define DPU_DEBUGFS_DIR "msm_dpu" 46 #define DPU_DEBUGFS_HWMASKNAME "hw_log_mask" 47 48 #define MIN_IB_BW 400000000ULL /* Min ib vote 400MB */ 49 50 static int dpu_kms_hw_init(struct msm_kms *kms); 51 static void _dpu_kms_mmu_destroy(struct dpu_kms *dpu_kms); 52 53 #ifdef CONFIG_DEBUG_FS 54 static int _dpu_danger_signal_status(struct seq_file *s, 55 bool danger_status) 56 { 57 struct dpu_kms *kms = (struct dpu_kms *)s->private; 58 struct dpu_danger_safe_status status; 59 int i; 60 61 if (!kms->hw_mdp) { 62 DPU_ERROR("invalid arg(s)\n"); 63 return 0; 64 } 65 66 memset(&status, 0, sizeof(struct dpu_danger_safe_status)); 67 68 pm_runtime_get_sync(&kms->pdev->dev); 69 if (danger_status) { 70 seq_puts(s, "\nDanger signal status:\n"); 71 if (kms->hw_mdp->ops.get_danger_status) 72 kms->hw_mdp->ops.get_danger_status(kms->hw_mdp, 73 &status); 74 } else { 75 seq_puts(s, "\nSafe signal status:\n"); 76 if (kms->hw_mdp->ops.get_safe_status) 77 kms->hw_mdp->ops.get_safe_status(kms->hw_mdp, 78 &status); 79 } 80 pm_runtime_put_sync(&kms->pdev->dev); 81 82 seq_printf(s, "MDP : 0x%x\n", status.mdp); 83 84 for (i = SSPP_VIG0; i < SSPP_MAX; i++) 85 seq_printf(s, "SSPP%d : 0x%x \n", i - SSPP_VIG0, 86 status.sspp[i]); 87 seq_puts(s, "\n"); 88 89 return 0; 90 } 91 92 static int dpu_debugfs_danger_stats_show(struct seq_file *s, void *v) 93 { 94 return _dpu_danger_signal_status(s, true); 95 } 96 DEFINE_SHOW_ATTRIBUTE(dpu_debugfs_danger_stats); 97 98 static int dpu_debugfs_safe_stats_show(struct seq_file *s, void *v) 99 { 100 return _dpu_danger_signal_status(s, false); 101 } 102 DEFINE_SHOW_ATTRIBUTE(dpu_debugfs_safe_stats); 103 104 static ssize_t _dpu_plane_danger_read(struct file *file, 105 char __user *buff, size_t count, loff_t *ppos) 106 { 107 struct dpu_kms *kms = file->private_data; 108 int len; 109 char buf[40]; 110 111 len = scnprintf(buf, sizeof(buf), "%d\n", !kms->has_danger_ctrl); 112 113 return simple_read_from_buffer(buff, count, ppos, buf, len); 114 } 115 116 static void _dpu_plane_set_danger_state(struct dpu_kms *kms, bool enable) 117 { 118 struct drm_plane *plane; 119 120 drm_for_each_plane(plane, kms->dev) { 121 if (plane->fb && plane->state) { 122 dpu_plane_danger_signal_ctrl(plane, enable); 123 DPU_DEBUG("plane:%d img:%dx%d ", 124 plane->base.id, plane->fb->width, 125 plane->fb->height); 126 DPU_DEBUG("src[%d,%d,%d,%d] dst[%d,%d,%d,%d]\n", 127 plane->state->src_x >> 16, 128 plane->state->src_y >> 16, 129 plane->state->src_w >> 16, 130 plane->state->src_h >> 16, 131 plane->state->crtc_x, plane->state->crtc_y, 132 plane->state->crtc_w, plane->state->crtc_h); 133 } else { 134 DPU_DEBUG("Inactive plane:%d\n", plane->base.id); 135 } 136 } 137 } 138 139 static ssize_t _dpu_plane_danger_write(struct file *file, 140 const char __user *user_buf, size_t count, loff_t *ppos) 141 { 142 struct dpu_kms *kms = file->private_data; 143 int disable_panic; 144 int ret; 145 146 ret = kstrtouint_from_user(user_buf, count, 0, &disable_panic); 147 if (ret) 148 return ret; 149 150 if (disable_panic) { 151 /* Disable panic signal for all active pipes */ 152 DPU_DEBUG("Disabling danger:\n"); 153 _dpu_plane_set_danger_state(kms, false); 154 kms->has_danger_ctrl = false; 155 } else { 156 /* Enable panic signal for all active pipes */ 157 DPU_DEBUG("Enabling danger:\n"); 158 kms->has_danger_ctrl = true; 159 _dpu_plane_set_danger_state(kms, true); 160 } 161 162 return count; 163 } 164 165 static const struct file_operations dpu_plane_danger_enable = { 166 .open = simple_open, 167 .read = _dpu_plane_danger_read, 168 .write = _dpu_plane_danger_write, 169 }; 170 171 static void dpu_debugfs_danger_init(struct dpu_kms *dpu_kms, 172 struct dentry *parent) 173 { 174 struct dentry *entry = debugfs_create_dir("danger", parent); 175 176 debugfs_create_file("danger_status", 0600, entry, 177 dpu_kms, &dpu_debugfs_danger_stats_fops); 178 debugfs_create_file("safe_status", 0600, entry, 179 dpu_kms, &dpu_debugfs_safe_stats_fops); 180 debugfs_create_file("disable_danger", 0600, entry, 181 dpu_kms, &dpu_plane_danger_enable); 182 183 } 184 185 /* 186 * Companion structure for dpu_debugfs_create_regset32. 187 */ 188 struct dpu_debugfs_regset32 { 189 uint32_t offset; 190 uint32_t blk_len; 191 struct dpu_kms *dpu_kms; 192 }; 193 194 static int _dpu_debugfs_show_regset32(struct seq_file *s, void *data) 195 { 196 struct dpu_debugfs_regset32 *regset = s->private; 197 struct dpu_kms *dpu_kms = regset->dpu_kms; 198 void __iomem *base; 199 uint32_t i, addr; 200 201 if (!dpu_kms->mmio) 202 return 0; 203 204 base = dpu_kms->mmio + regset->offset; 205 206 /* insert padding spaces, if needed */ 207 if (regset->offset & 0xF) { 208 seq_printf(s, "[%x]", regset->offset & ~0xF); 209 for (i = 0; i < (regset->offset & 0xF); i += 4) 210 seq_puts(s, " "); 211 } 212 213 pm_runtime_get_sync(&dpu_kms->pdev->dev); 214 215 /* main register output */ 216 for (i = 0; i < regset->blk_len; i += 4) { 217 addr = regset->offset + i; 218 if ((addr & 0xF) == 0x0) 219 seq_printf(s, i ? "\n[%x]" : "[%x]", addr); 220 seq_printf(s, " %08x", readl_relaxed(base + i)); 221 } 222 seq_puts(s, "\n"); 223 pm_runtime_put_sync(&dpu_kms->pdev->dev); 224 225 return 0; 226 } 227 228 static int dpu_debugfs_open_regset32(struct inode *inode, 229 struct file *file) 230 { 231 return single_open(file, _dpu_debugfs_show_regset32, inode->i_private); 232 } 233 234 static const struct file_operations dpu_fops_regset32 = { 235 .open = dpu_debugfs_open_regset32, 236 .read = seq_read, 237 .llseek = seq_lseek, 238 .release = single_release, 239 }; 240 241 void dpu_debugfs_create_regset32(const char *name, umode_t mode, 242 void *parent, 243 uint32_t offset, uint32_t length, struct dpu_kms *dpu_kms) 244 { 245 struct dpu_debugfs_regset32 *regset; 246 247 if (WARN_ON(!name || !dpu_kms || !length)) 248 return; 249 250 regset = devm_kzalloc(&dpu_kms->pdev->dev, sizeof(*regset), GFP_KERNEL); 251 if (!regset) 252 return; 253 254 /* make sure offset is a multiple of 4 */ 255 regset->offset = round_down(offset, 4); 256 regset->blk_len = length; 257 regset->dpu_kms = dpu_kms; 258 259 debugfs_create_file(name, mode, parent, regset, &dpu_fops_regset32); 260 } 261 262 static int dpu_kms_debugfs_init(struct msm_kms *kms, struct drm_minor *minor) 263 { 264 struct dpu_kms *dpu_kms = to_dpu_kms(kms); 265 void *p = dpu_hw_util_get_log_mask_ptr(); 266 struct dentry *entry; 267 struct drm_device *dev; 268 struct msm_drm_private *priv; 269 int i; 270 271 if (!p) 272 return -EINVAL; 273 274 dev = dpu_kms->dev; 275 priv = dev->dev_private; 276 277 entry = debugfs_create_dir("debug", minor->debugfs_root); 278 279 debugfs_create_x32(DPU_DEBUGFS_HWMASKNAME, 0600, entry, p); 280 281 dpu_debugfs_danger_init(dpu_kms, entry); 282 dpu_debugfs_vbif_init(dpu_kms, entry); 283 dpu_debugfs_core_irq_init(dpu_kms, entry); 284 dpu_debugfs_sspp_init(dpu_kms, entry); 285 286 for (i = 0; i < ARRAY_SIZE(priv->dp); i++) { 287 if (priv->dp[i]) 288 msm_dp_debugfs_init(priv->dp[i], minor); 289 } 290 291 return dpu_core_perf_debugfs_init(dpu_kms, entry); 292 } 293 #endif 294 295 /* Global/shared object state funcs */ 296 297 /* 298 * This is a helper that returns the private state currently in operation. 299 * Note that this would return the "old_state" if called in the atomic check 300 * path, and the "new_state" after the atomic swap has been done. 301 */ 302 struct dpu_global_state * 303 dpu_kms_get_existing_global_state(struct dpu_kms *dpu_kms) 304 { 305 return to_dpu_global_state(dpu_kms->global_state.state); 306 } 307 308 /* 309 * This acquires the modeset lock set aside for global state, creates 310 * a new duplicated private object state. 311 */ 312 struct dpu_global_state *dpu_kms_get_global_state(struct drm_atomic_state *s) 313 { 314 struct msm_drm_private *priv = s->dev->dev_private; 315 struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms); 316 struct drm_private_state *priv_state; 317 int ret; 318 319 ret = drm_modeset_lock(&dpu_kms->global_state_lock, s->acquire_ctx); 320 if (ret) 321 return ERR_PTR(ret); 322 323 priv_state = drm_atomic_get_private_obj_state(s, 324 &dpu_kms->global_state); 325 if (IS_ERR(priv_state)) 326 return ERR_CAST(priv_state); 327 328 return to_dpu_global_state(priv_state); 329 } 330 331 static struct drm_private_state * 332 dpu_kms_global_duplicate_state(struct drm_private_obj *obj) 333 { 334 struct dpu_global_state *state; 335 336 state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL); 337 if (!state) 338 return NULL; 339 340 __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base); 341 342 return &state->base; 343 } 344 345 static void dpu_kms_global_destroy_state(struct drm_private_obj *obj, 346 struct drm_private_state *state) 347 { 348 struct dpu_global_state *dpu_state = to_dpu_global_state(state); 349 350 kfree(dpu_state); 351 } 352 353 static const struct drm_private_state_funcs dpu_kms_global_state_funcs = { 354 .atomic_duplicate_state = dpu_kms_global_duplicate_state, 355 .atomic_destroy_state = dpu_kms_global_destroy_state, 356 }; 357 358 static int dpu_kms_global_obj_init(struct dpu_kms *dpu_kms) 359 { 360 struct dpu_global_state *state; 361 362 drm_modeset_lock_init(&dpu_kms->global_state_lock); 363 364 state = kzalloc(sizeof(*state), GFP_KERNEL); 365 if (!state) 366 return -ENOMEM; 367 368 drm_atomic_private_obj_init(dpu_kms->dev, &dpu_kms->global_state, 369 &state->base, 370 &dpu_kms_global_state_funcs); 371 return 0; 372 } 373 374 static int dpu_kms_parse_data_bus_icc_path(struct dpu_kms *dpu_kms) 375 { 376 struct icc_path *path0; 377 struct icc_path *path1; 378 struct drm_device *dev = dpu_kms->dev; 379 380 path0 = of_icc_get(dev->dev, "mdp0-mem"); 381 path1 = of_icc_get(dev->dev, "mdp1-mem"); 382 383 if (IS_ERR_OR_NULL(path0)) 384 return PTR_ERR_OR_ZERO(path0); 385 386 dpu_kms->path[0] = path0; 387 dpu_kms->num_paths = 1; 388 389 if (!IS_ERR_OR_NULL(path1)) { 390 dpu_kms->path[1] = path1; 391 dpu_kms->num_paths++; 392 } 393 return 0; 394 } 395 396 static int dpu_kms_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc) 397 { 398 return dpu_crtc_vblank(crtc, true); 399 } 400 401 static void dpu_kms_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc) 402 { 403 dpu_crtc_vblank(crtc, false); 404 } 405 406 static void dpu_kms_enable_commit(struct msm_kms *kms) 407 { 408 struct dpu_kms *dpu_kms = to_dpu_kms(kms); 409 pm_runtime_get_sync(&dpu_kms->pdev->dev); 410 } 411 412 static void dpu_kms_disable_commit(struct msm_kms *kms) 413 { 414 struct dpu_kms *dpu_kms = to_dpu_kms(kms); 415 pm_runtime_put_sync(&dpu_kms->pdev->dev); 416 } 417 418 static ktime_t dpu_kms_vsync_time(struct msm_kms *kms, struct drm_crtc *crtc) 419 { 420 struct drm_encoder *encoder; 421 422 drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) { 423 ktime_t vsync_time; 424 425 if (dpu_encoder_vsync_time(encoder, &vsync_time) == 0) 426 return vsync_time; 427 } 428 429 return ktime_get(); 430 } 431 432 static void dpu_kms_prepare_commit(struct msm_kms *kms, 433 struct drm_atomic_state *state) 434 { 435 struct drm_crtc *crtc; 436 struct drm_crtc_state *crtc_state; 437 struct drm_encoder *encoder; 438 int i; 439 440 if (!kms) 441 return; 442 443 /* Call prepare_commit for all affected encoders */ 444 for_each_new_crtc_in_state(state, crtc, crtc_state, i) { 445 drm_for_each_encoder_mask(encoder, crtc->dev, 446 crtc_state->encoder_mask) { 447 dpu_encoder_prepare_commit(encoder); 448 } 449 } 450 } 451 452 static void dpu_kms_flush_commit(struct msm_kms *kms, unsigned crtc_mask) 453 { 454 struct dpu_kms *dpu_kms = to_dpu_kms(kms); 455 struct drm_crtc *crtc; 456 457 for_each_crtc_mask(dpu_kms->dev, crtc, crtc_mask) { 458 if (!crtc->state->active) 459 continue; 460 461 trace_dpu_kms_commit(DRMID(crtc)); 462 dpu_crtc_commit_kickoff(crtc); 463 } 464 } 465 466 static void dpu_kms_complete_commit(struct msm_kms *kms, unsigned crtc_mask) 467 { 468 struct dpu_kms *dpu_kms = to_dpu_kms(kms); 469 struct drm_crtc *crtc; 470 471 DPU_ATRACE_BEGIN("kms_complete_commit"); 472 473 for_each_crtc_mask(dpu_kms->dev, crtc, crtc_mask) 474 dpu_crtc_complete_commit(crtc); 475 476 DPU_ATRACE_END("kms_complete_commit"); 477 } 478 479 static void dpu_kms_wait_for_commit_done(struct msm_kms *kms, 480 struct drm_crtc *crtc) 481 { 482 struct drm_encoder *encoder; 483 struct drm_device *dev; 484 int ret; 485 486 if (!kms || !crtc || !crtc->state) { 487 DPU_ERROR("invalid params\n"); 488 return; 489 } 490 491 dev = crtc->dev; 492 493 if (!crtc->state->enable) { 494 DPU_DEBUG("[crtc:%d] not enable\n", crtc->base.id); 495 return; 496 } 497 498 if (!crtc->state->active) { 499 DPU_DEBUG("[crtc:%d] not active\n", crtc->base.id); 500 return; 501 } 502 503 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 504 if (encoder->crtc != crtc) 505 continue; 506 /* 507 * Wait for post-flush if necessary to delay before 508 * plane_cleanup. For example, wait for vsync in case of video 509 * mode panels. This may be a no-op for command mode panels. 510 */ 511 trace_dpu_kms_wait_for_commit_done(DRMID(crtc)); 512 ret = dpu_encoder_wait_for_event(encoder, MSM_ENC_COMMIT_DONE); 513 if (ret && ret != -EWOULDBLOCK) { 514 DPU_ERROR("wait for commit done returned %d\n", ret); 515 break; 516 } 517 } 518 } 519 520 static void dpu_kms_wait_flush(struct msm_kms *kms, unsigned crtc_mask) 521 { 522 struct dpu_kms *dpu_kms = to_dpu_kms(kms); 523 struct drm_crtc *crtc; 524 525 for_each_crtc_mask(dpu_kms->dev, crtc, crtc_mask) 526 dpu_kms_wait_for_commit_done(kms, crtc); 527 } 528 529 static int _dpu_kms_initialize_dsi(struct drm_device *dev, 530 struct msm_drm_private *priv, 531 struct dpu_kms *dpu_kms) 532 { 533 struct drm_encoder *encoder = NULL; 534 struct msm_display_info info; 535 int i, rc = 0; 536 537 if (!(priv->dsi[0] || priv->dsi[1])) 538 return rc; 539 540 /* 541 * We support following confiurations: 542 * - Single DSI host (dsi0 or dsi1) 543 * - Two independent DSI hosts 544 * - Bonded DSI0 and DSI1 hosts 545 * 546 * TODO: Support swapping DSI0 and DSI1 in the bonded setup. 547 */ 548 for (i = 0; i < ARRAY_SIZE(priv->dsi); i++) { 549 int other = (i + 1) % 2; 550 551 if (!priv->dsi[i]) 552 continue; 553 554 if (msm_dsi_is_bonded_dsi(priv->dsi[i]) && 555 !msm_dsi_is_master_dsi(priv->dsi[i])) 556 continue; 557 558 encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_DSI); 559 if (IS_ERR(encoder)) { 560 DPU_ERROR("encoder init failed for dsi display\n"); 561 return PTR_ERR(encoder); 562 } 563 564 priv->encoders[priv->num_encoders++] = encoder; 565 566 memset(&info, 0, sizeof(info)); 567 info.intf_type = encoder->encoder_type; 568 569 rc = msm_dsi_modeset_init(priv->dsi[i], dev, encoder); 570 if (rc) { 571 DPU_ERROR("modeset_init failed for dsi[%d], rc = %d\n", 572 i, rc); 573 break; 574 } 575 576 info.h_tile_instance[info.num_of_h_tiles++] = i; 577 info.capabilities = msm_dsi_is_cmd_mode(priv->dsi[i]) ? 578 MSM_DISPLAY_CAP_CMD_MODE : 579 MSM_DISPLAY_CAP_VID_MODE; 580 581 if (msm_dsi_is_bonded_dsi(priv->dsi[i]) && priv->dsi[other]) { 582 rc = msm_dsi_modeset_init(priv->dsi[other], dev, encoder); 583 if (rc) { 584 DPU_ERROR("modeset_init failed for dsi[%d], rc = %d\n", 585 other, rc); 586 break; 587 } 588 589 info.h_tile_instance[info.num_of_h_tiles++] = other; 590 } 591 592 rc = dpu_encoder_setup(dev, encoder, &info); 593 if (rc) 594 DPU_ERROR("failed to setup DPU encoder %d: rc:%d\n", 595 encoder->base.id, rc); 596 } 597 598 return rc; 599 } 600 601 static int _dpu_kms_initialize_displayport(struct drm_device *dev, 602 struct msm_drm_private *priv, 603 struct dpu_kms *dpu_kms) 604 { 605 struct drm_encoder *encoder = NULL; 606 struct msm_display_info info; 607 int rc; 608 int i; 609 610 for (i = 0; i < ARRAY_SIZE(priv->dp); i++) { 611 if (!priv->dp[i]) 612 continue; 613 614 encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_TMDS); 615 if (IS_ERR(encoder)) { 616 DPU_ERROR("encoder init failed for dsi display\n"); 617 return PTR_ERR(encoder); 618 } 619 620 memset(&info, 0, sizeof(info)); 621 rc = msm_dp_modeset_init(priv->dp[i], dev, encoder); 622 if (rc) { 623 DPU_ERROR("modeset_init failed for DP, rc = %d\n", rc); 624 drm_encoder_cleanup(encoder); 625 return rc; 626 } 627 628 priv->encoders[priv->num_encoders++] = encoder; 629 630 info.num_of_h_tiles = 1; 631 info.h_tile_instance[0] = i; 632 info.capabilities = MSM_DISPLAY_CAP_VID_MODE; 633 info.intf_type = encoder->encoder_type; 634 rc = dpu_encoder_setup(dev, encoder, &info); 635 if (rc) { 636 DPU_ERROR("failed to setup DPU encoder %d: rc:%d\n", 637 encoder->base.id, rc); 638 return rc; 639 } 640 } 641 642 return 0; 643 } 644 645 /** 646 * _dpu_kms_setup_displays - create encoders, bridges and connectors 647 * for underlying displays 648 * @dev: Pointer to drm device structure 649 * @priv: Pointer to private drm device data 650 * @dpu_kms: Pointer to dpu kms structure 651 * Returns: Zero on success 652 */ 653 static int _dpu_kms_setup_displays(struct drm_device *dev, 654 struct msm_drm_private *priv, 655 struct dpu_kms *dpu_kms) 656 { 657 int rc = 0; 658 659 rc = _dpu_kms_initialize_dsi(dev, priv, dpu_kms); 660 if (rc) { 661 DPU_ERROR("initialize_dsi failed, rc = %d\n", rc); 662 return rc; 663 } 664 665 rc = _dpu_kms_initialize_displayport(dev, priv, dpu_kms); 666 if (rc) { 667 DPU_ERROR("initialize_DP failed, rc = %d\n", rc); 668 return rc; 669 } 670 671 return rc; 672 } 673 674 static void _dpu_kms_drm_obj_destroy(struct dpu_kms *dpu_kms) 675 { 676 struct msm_drm_private *priv; 677 int i; 678 679 priv = dpu_kms->dev->dev_private; 680 681 for (i = 0; i < priv->num_crtcs; i++) 682 priv->crtcs[i]->funcs->destroy(priv->crtcs[i]); 683 priv->num_crtcs = 0; 684 685 for (i = 0; i < priv->num_planes; i++) 686 priv->planes[i]->funcs->destroy(priv->planes[i]); 687 priv->num_planes = 0; 688 689 for (i = 0; i < priv->num_connectors; i++) 690 priv->connectors[i]->funcs->destroy(priv->connectors[i]); 691 priv->num_connectors = 0; 692 693 for (i = 0; i < priv->num_encoders; i++) 694 priv->encoders[i]->funcs->destroy(priv->encoders[i]); 695 priv->num_encoders = 0; 696 } 697 698 static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms) 699 { 700 struct drm_device *dev; 701 struct drm_plane *primary_planes[MAX_PLANES], *plane; 702 struct drm_plane *cursor_planes[MAX_PLANES] = { NULL }; 703 struct drm_crtc *crtc; 704 705 struct msm_drm_private *priv; 706 struct dpu_mdss_cfg *catalog; 707 708 int primary_planes_idx = 0, cursor_planes_idx = 0, i, ret; 709 int max_crtc_count; 710 dev = dpu_kms->dev; 711 priv = dev->dev_private; 712 catalog = dpu_kms->catalog; 713 714 /* 715 * Create encoder and query display drivers to create 716 * bridges and connectors 717 */ 718 ret = _dpu_kms_setup_displays(dev, priv, dpu_kms); 719 if (ret) 720 goto fail; 721 722 max_crtc_count = min(catalog->mixer_count, priv->num_encoders); 723 724 /* Create the planes, keeping track of one primary/cursor per crtc */ 725 for (i = 0; i < catalog->sspp_count; i++) { 726 enum drm_plane_type type; 727 728 if ((catalog->sspp[i].features & BIT(DPU_SSPP_CURSOR)) 729 && cursor_planes_idx < max_crtc_count) 730 type = DRM_PLANE_TYPE_CURSOR; 731 else if (primary_planes_idx < max_crtc_count) 732 type = DRM_PLANE_TYPE_PRIMARY; 733 else 734 type = DRM_PLANE_TYPE_OVERLAY; 735 736 DPU_DEBUG("Create plane type %d with features %lx (cur %lx)\n", 737 type, catalog->sspp[i].features, 738 catalog->sspp[i].features & BIT(DPU_SSPP_CURSOR)); 739 740 plane = dpu_plane_init(dev, catalog->sspp[i].id, type, 741 (1UL << max_crtc_count) - 1, 0); 742 if (IS_ERR(plane)) { 743 DPU_ERROR("dpu_plane_init failed\n"); 744 ret = PTR_ERR(plane); 745 goto fail; 746 } 747 priv->planes[priv->num_planes++] = plane; 748 749 if (type == DRM_PLANE_TYPE_CURSOR) 750 cursor_planes[cursor_planes_idx++] = plane; 751 else if (type == DRM_PLANE_TYPE_PRIMARY) 752 primary_planes[primary_planes_idx++] = plane; 753 } 754 755 max_crtc_count = min(max_crtc_count, primary_planes_idx); 756 757 /* Create one CRTC per encoder */ 758 for (i = 0; i < max_crtc_count; i++) { 759 crtc = dpu_crtc_init(dev, primary_planes[i], cursor_planes[i]); 760 if (IS_ERR(crtc)) { 761 ret = PTR_ERR(crtc); 762 goto fail; 763 } 764 priv->crtcs[priv->num_crtcs++] = crtc; 765 } 766 767 /* All CRTCs are compatible with all encoders */ 768 for (i = 0; i < priv->num_encoders; i++) 769 priv->encoders[i]->possible_crtcs = (1 << priv->num_crtcs) - 1; 770 771 return 0; 772 fail: 773 _dpu_kms_drm_obj_destroy(dpu_kms); 774 return ret; 775 } 776 777 static long dpu_kms_round_pixclk(struct msm_kms *kms, unsigned long rate, 778 struct drm_encoder *encoder) 779 { 780 return rate; 781 } 782 783 static void _dpu_kms_hw_destroy(struct dpu_kms *dpu_kms) 784 { 785 int i; 786 787 if (dpu_kms->hw_intr) 788 dpu_hw_intr_destroy(dpu_kms->hw_intr); 789 dpu_kms->hw_intr = NULL; 790 791 /* safe to call these more than once during shutdown */ 792 _dpu_kms_mmu_destroy(dpu_kms); 793 794 if (dpu_kms->catalog) { 795 for (i = 0; i < dpu_kms->catalog->vbif_count; i++) { 796 u32 vbif_idx = dpu_kms->catalog->vbif[i].id; 797 798 if ((vbif_idx < VBIF_MAX) && dpu_kms->hw_vbif[vbif_idx]) 799 dpu_hw_vbif_destroy(dpu_kms->hw_vbif[vbif_idx]); 800 } 801 } 802 803 if (dpu_kms->rm_init) 804 dpu_rm_destroy(&dpu_kms->rm); 805 dpu_kms->rm_init = false; 806 807 if (dpu_kms->catalog) 808 dpu_hw_catalog_deinit(dpu_kms->catalog); 809 dpu_kms->catalog = NULL; 810 811 if (dpu_kms->vbif[VBIF_NRT]) 812 devm_iounmap(&dpu_kms->pdev->dev, dpu_kms->vbif[VBIF_NRT]); 813 dpu_kms->vbif[VBIF_NRT] = NULL; 814 815 if (dpu_kms->vbif[VBIF_RT]) 816 devm_iounmap(&dpu_kms->pdev->dev, dpu_kms->vbif[VBIF_RT]); 817 dpu_kms->vbif[VBIF_RT] = NULL; 818 819 if (dpu_kms->hw_mdp) 820 dpu_hw_mdp_destroy(dpu_kms->hw_mdp); 821 dpu_kms->hw_mdp = NULL; 822 823 if (dpu_kms->mmio) 824 devm_iounmap(&dpu_kms->pdev->dev, dpu_kms->mmio); 825 dpu_kms->mmio = NULL; 826 } 827 828 static void dpu_kms_destroy(struct msm_kms *kms) 829 { 830 struct dpu_kms *dpu_kms; 831 832 if (!kms) { 833 DPU_ERROR("invalid kms\n"); 834 return; 835 } 836 837 dpu_kms = to_dpu_kms(kms); 838 839 _dpu_kms_hw_destroy(dpu_kms); 840 841 msm_kms_destroy(&dpu_kms->base); 842 } 843 844 static irqreturn_t dpu_irq(struct msm_kms *kms) 845 { 846 struct dpu_kms *dpu_kms = to_dpu_kms(kms); 847 848 return dpu_core_irq(dpu_kms); 849 } 850 851 static void dpu_irq_preinstall(struct msm_kms *kms) 852 { 853 struct dpu_kms *dpu_kms = to_dpu_kms(kms); 854 855 dpu_core_irq_preinstall(dpu_kms); 856 } 857 858 static int dpu_irq_postinstall(struct msm_kms *kms) 859 { 860 struct msm_drm_private *priv; 861 struct dpu_kms *dpu_kms = to_dpu_kms(kms); 862 int i; 863 864 if (!dpu_kms || !dpu_kms->dev) 865 return -EINVAL; 866 867 priv = dpu_kms->dev->dev_private; 868 if (!priv) 869 return -EINVAL; 870 871 for (i = 0; i < ARRAY_SIZE(priv->dp); i++) 872 msm_dp_irq_postinstall(priv->dp[i]); 873 874 return 0; 875 } 876 877 static void dpu_irq_uninstall(struct msm_kms *kms) 878 { 879 struct dpu_kms *dpu_kms = to_dpu_kms(kms); 880 881 dpu_core_irq_uninstall(dpu_kms); 882 } 883 884 static void dpu_kms_mdp_snapshot(struct msm_disp_state *disp_state, struct msm_kms *kms) 885 { 886 int i; 887 struct dpu_kms *dpu_kms; 888 struct dpu_mdss_cfg *cat; 889 struct dpu_hw_mdp *top; 890 891 dpu_kms = to_dpu_kms(kms); 892 893 cat = dpu_kms->catalog; 894 top = dpu_kms->hw_mdp; 895 896 pm_runtime_get_sync(&dpu_kms->pdev->dev); 897 898 /* dump CTL sub-blocks HW regs info */ 899 for (i = 0; i < cat->ctl_count; i++) 900 msm_disp_snapshot_add_block(disp_state, cat->ctl[i].len, 901 dpu_kms->mmio + cat->ctl[i].base, "ctl_%d", i); 902 903 /* dump DSPP sub-blocks HW regs info */ 904 for (i = 0; i < cat->dspp_count; i++) 905 msm_disp_snapshot_add_block(disp_state, cat->dspp[i].len, 906 dpu_kms->mmio + cat->dspp[i].base, "dspp_%d", i); 907 908 /* dump INTF sub-blocks HW regs info */ 909 for (i = 0; i < cat->intf_count; i++) 910 msm_disp_snapshot_add_block(disp_state, cat->intf[i].len, 911 dpu_kms->mmio + cat->intf[i].base, "intf_%d", i); 912 913 /* dump PP sub-blocks HW regs info */ 914 for (i = 0; i < cat->pingpong_count; i++) 915 msm_disp_snapshot_add_block(disp_state, cat->pingpong[i].len, 916 dpu_kms->mmio + cat->pingpong[i].base, "pingpong_%d", i); 917 918 /* dump SSPP sub-blocks HW regs info */ 919 for (i = 0; i < cat->sspp_count; i++) 920 msm_disp_snapshot_add_block(disp_state, cat->sspp[i].len, 921 dpu_kms->mmio + cat->sspp[i].base, "sspp_%d", i); 922 923 /* dump LM sub-blocks HW regs info */ 924 for (i = 0; i < cat->mixer_count; i++) 925 msm_disp_snapshot_add_block(disp_state, cat->mixer[i].len, 926 dpu_kms->mmio + cat->mixer[i].base, "lm_%d", i); 927 928 msm_disp_snapshot_add_block(disp_state, top->hw.length, 929 dpu_kms->mmio + top->hw.blk_off, "top"); 930 931 pm_runtime_put_sync(&dpu_kms->pdev->dev); 932 } 933 934 static const struct msm_kms_funcs kms_funcs = { 935 .hw_init = dpu_kms_hw_init, 936 .irq_preinstall = dpu_irq_preinstall, 937 .irq_postinstall = dpu_irq_postinstall, 938 .irq_uninstall = dpu_irq_uninstall, 939 .irq = dpu_irq, 940 .enable_commit = dpu_kms_enable_commit, 941 .disable_commit = dpu_kms_disable_commit, 942 .vsync_time = dpu_kms_vsync_time, 943 .prepare_commit = dpu_kms_prepare_commit, 944 .flush_commit = dpu_kms_flush_commit, 945 .wait_flush = dpu_kms_wait_flush, 946 .complete_commit = dpu_kms_complete_commit, 947 .enable_vblank = dpu_kms_enable_vblank, 948 .disable_vblank = dpu_kms_disable_vblank, 949 .check_modified_format = dpu_format_check_modified_format, 950 .get_format = dpu_get_msm_format, 951 .round_pixclk = dpu_kms_round_pixclk, 952 .destroy = dpu_kms_destroy, 953 .snapshot = dpu_kms_mdp_snapshot, 954 #ifdef CONFIG_DEBUG_FS 955 .debugfs_init = dpu_kms_debugfs_init, 956 #endif 957 }; 958 959 static void _dpu_kms_mmu_destroy(struct dpu_kms *dpu_kms) 960 { 961 struct msm_mmu *mmu; 962 963 if (!dpu_kms->base.aspace) 964 return; 965 966 mmu = dpu_kms->base.aspace->mmu; 967 968 mmu->funcs->detach(mmu); 969 msm_gem_address_space_put(dpu_kms->base.aspace); 970 971 dpu_kms->base.aspace = NULL; 972 } 973 974 static int _dpu_kms_mmu_init(struct dpu_kms *dpu_kms) 975 { 976 struct iommu_domain *domain; 977 struct msm_gem_address_space *aspace; 978 struct msm_mmu *mmu; 979 980 domain = iommu_domain_alloc(&platform_bus_type); 981 if (!domain) 982 return 0; 983 984 mmu = msm_iommu_new(dpu_kms->dev->dev, domain); 985 if (IS_ERR(mmu)) { 986 iommu_domain_free(domain); 987 return PTR_ERR(mmu); 988 } 989 aspace = msm_gem_address_space_create(mmu, "dpu1", 990 0x1000, 0x100000000 - 0x1000); 991 992 if (IS_ERR(aspace)) { 993 mmu->funcs->destroy(mmu); 994 return PTR_ERR(aspace); 995 } 996 997 dpu_kms->base.aspace = aspace; 998 return 0; 999 } 1000 1001 static struct dss_clk *_dpu_kms_get_clk(struct dpu_kms *dpu_kms, 1002 char *clock_name) 1003 { 1004 struct dss_module_power *mp = &dpu_kms->mp; 1005 int i; 1006 1007 for (i = 0; i < mp->num_clk; i++) { 1008 if (!strcmp(mp->clk_config[i].clk_name, clock_name)) 1009 return &mp->clk_config[i]; 1010 } 1011 1012 return NULL; 1013 } 1014 1015 u64 dpu_kms_get_clk_rate(struct dpu_kms *dpu_kms, char *clock_name) 1016 { 1017 struct dss_clk *clk; 1018 1019 clk = _dpu_kms_get_clk(dpu_kms, clock_name); 1020 if (!clk) 1021 return -EINVAL; 1022 1023 return clk_get_rate(clk->clk); 1024 } 1025 1026 static int dpu_kms_hw_init(struct msm_kms *kms) 1027 { 1028 struct dpu_kms *dpu_kms; 1029 struct drm_device *dev; 1030 int i, rc = -EINVAL; 1031 1032 if (!kms) { 1033 DPU_ERROR("invalid kms\n"); 1034 return rc; 1035 } 1036 1037 dpu_kms = to_dpu_kms(kms); 1038 dev = dpu_kms->dev; 1039 1040 rc = dpu_kms_global_obj_init(dpu_kms); 1041 if (rc) 1042 return rc; 1043 1044 atomic_set(&dpu_kms->bandwidth_ref, 0); 1045 1046 dpu_kms->mmio = msm_ioremap(dpu_kms->pdev, "mdp", "mdp"); 1047 if (IS_ERR(dpu_kms->mmio)) { 1048 rc = PTR_ERR(dpu_kms->mmio); 1049 DPU_ERROR("mdp register memory map failed: %d\n", rc); 1050 dpu_kms->mmio = NULL; 1051 goto error; 1052 } 1053 DRM_DEBUG("mapped dpu address space @%pK\n", dpu_kms->mmio); 1054 1055 dpu_kms->vbif[VBIF_RT] = msm_ioremap(dpu_kms->pdev, "vbif", "vbif"); 1056 if (IS_ERR(dpu_kms->vbif[VBIF_RT])) { 1057 rc = PTR_ERR(dpu_kms->vbif[VBIF_RT]); 1058 DPU_ERROR("vbif register memory map failed: %d\n", rc); 1059 dpu_kms->vbif[VBIF_RT] = NULL; 1060 goto error; 1061 } 1062 dpu_kms->vbif[VBIF_NRT] = msm_ioremap_quiet(dpu_kms->pdev, "vbif_nrt", "vbif_nrt"); 1063 if (IS_ERR(dpu_kms->vbif[VBIF_NRT])) { 1064 dpu_kms->vbif[VBIF_NRT] = NULL; 1065 DPU_DEBUG("VBIF NRT is not defined"); 1066 } 1067 1068 dpu_kms->reg_dma = msm_ioremap_quiet(dpu_kms->pdev, "regdma", "regdma"); 1069 if (IS_ERR(dpu_kms->reg_dma)) { 1070 dpu_kms->reg_dma = NULL; 1071 DPU_DEBUG("REG_DMA is not defined"); 1072 } 1073 1074 dpu_kms_parse_data_bus_icc_path(dpu_kms); 1075 1076 pm_runtime_get_sync(&dpu_kms->pdev->dev); 1077 1078 dpu_kms->core_rev = readl_relaxed(dpu_kms->mmio + 0x0); 1079 1080 pr_info("dpu hardware revision:0x%x\n", dpu_kms->core_rev); 1081 1082 dpu_kms->catalog = dpu_hw_catalog_init(dpu_kms->core_rev); 1083 if (IS_ERR_OR_NULL(dpu_kms->catalog)) { 1084 rc = PTR_ERR(dpu_kms->catalog); 1085 if (!dpu_kms->catalog) 1086 rc = -EINVAL; 1087 DPU_ERROR("catalog init failed: %d\n", rc); 1088 dpu_kms->catalog = NULL; 1089 goto power_error; 1090 } 1091 1092 /* 1093 * Now we need to read the HW catalog and initialize resources such as 1094 * clocks, regulators, GDSC/MMAGIC, ioremap the register ranges etc 1095 */ 1096 rc = _dpu_kms_mmu_init(dpu_kms); 1097 if (rc) { 1098 DPU_ERROR("dpu_kms_mmu_init failed: %d\n", rc); 1099 goto power_error; 1100 } 1101 1102 rc = dpu_rm_init(&dpu_kms->rm, dpu_kms->catalog, dpu_kms->mmio); 1103 if (rc) { 1104 DPU_ERROR("rm init failed: %d\n", rc); 1105 goto power_error; 1106 } 1107 1108 dpu_kms->rm_init = true; 1109 1110 dpu_kms->hw_mdp = dpu_hw_mdptop_init(MDP_TOP, dpu_kms->mmio, 1111 dpu_kms->catalog); 1112 if (IS_ERR(dpu_kms->hw_mdp)) { 1113 rc = PTR_ERR(dpu_kms->hw_mdp); 1114 DPU_ERROR("failed to get hw_mdp: %d\n", rc); 1115 dpu_kms->hw_mdp = NULL; 1116 goto power_error; 1117 } 1118 1119 for (i = 0; i < dpu_kms->catalog->vbif_count; i++) { 1120 u32 vbif_idx = dpu_kms->catalog->vbif[i].id; 1121 1122 dpu_kms->hw_vbif[i] = dpu_hw_vbif_init(vbif_idx, 1123 dpu_kms->vbif[vbif_idx], dpu_kms->catalog); 1124 if (IS_ERR_OR_NULL(dpu_kms->hw_vbif[vbif_idx])) { 1125 rc = PTR_ERR(dpu_kms->hw_vbif[vbif_idx]); 1126 if (!dpu_kms->hw_vbif[vbif_idx]) 1127 rc = -EINVAL; 1128 DPU_ERROR("failed to init vbif %d: %d\n", vbif_idx, rc); 1129 dpu_kms->hw_vbif[vbif_idx] = NULL; 1130 goto power_error; 1131 } 1132 } 1133 1134 rc = dpu_core_perf_init(&dpu_kms->perf, dev, dpu_kms->catalog, 1135 _dpu_kms_get_clk(dpu_kms, "core")); 1136 if (rc) { 1137 DPU_ERROR("failed to init perf %d\n", rc); 1138 goto perf_err; 1139 } 1140 1141 dpu_kms->hw_intr = dpu_hw_intr_init(dpu_kms->mmio, dpu_kms->catalog); 1142 if (IS_ERR_OR_NULL(dpu_kms->hw_intr)) { 1143 rc = PTR_ERR(dpu_kms->hw_intr); 1144 DPU_ERROR("hw_intr init failed: %d\n", rc); 1145 dpu_kms->hw_intr = NULL; 1146 goto hw_intr_init_err; 1147 } 1148 1149 dev->mode_config.min_width = 0; 1150 dev->mode_config.min_height = 0; 1151 1152 /* 1153 * max crtc width is equal to the max mixer width * 2 and max height is 1154 * is 4K 1155 */ 1156 dev->mode_config.max_width = 1157 dpu_kms->catalog->caps->max_mixer_width * 2; 1158 dev->mode_config.max_height = 4096; 1159 1160 dev->max_vblank_count = 0xffffffff; 1161 /* Disable vblank irqs aggressively for power-saving */ 1162 dev->vblank_disable_immediate = true; 1163 1164 /* 1165 * _dpu_kms_drm_obj_init should create the DRM related objects 1166 * i.e. CRTCs, planes, encoders, connectors and so forth 1167 */ 1168 rc = _dpu_kms_drm_obj_init(dpu_kms); 1169 if (rc) { 1170 DPU_ERROR("modeset init failed: %d\n", rc); 1171 goto drm_obj_init_err; 1172 } 1173 1174 dpu_vbif_init_memtypes(dpu_kms); 1175 1176 pm_runtime_put_sync(&dpu_kms->pdev->dev); 1177 1178 return 0; 1179 1180 drm_obj_init_err: 1181 dpu_core_perf_destroy(&dpu_kms->perf); 1182 hw_intr_init_err: 1183 perf_err: 1184 power_error: 1185 pm_runtime_put_sync(&dpu_kms->pdev->dev); 1186 error: 1187 _dpu_kms_hw_destroy(dpu_kms); 1188 1189 return rc; 1190 } 1191 1192 struct msm_kms *dpu_kms_init(struct drm_device *dev) 1193 { 1194 struct msm_drm_private *priv; 1195 struct dpu_kms *dpu_kms; 1196 int irq; 1197 1198 if (!dev) { 1199 DPU_ERROR("drm device node invalid\n"); 1200 return ERR_PTR(-EINVAL); 1201 } 1202 1203 priv = dev->dev_private; 1204 dpu_kms = to_dpu_kms(priv->kms); 1205 1206 irq = irq_of_parse_and_map(dpu_kms->pdev->dev.of_node, 0); 1207 if (irq < 0) { 1208 DPU_ERROR("failed to get irq: %d\n", irq); 1209 return ERR_PTR(irq); 1210 } 1211 dpu_kms->base.irq = irq; 1212 1213 return &dpu_kms->base; 1214 } 1215 1216 static int dpu_bind(struct device *dev, struct device *master, void *data) 1217 { 1218 struct msm_drm_private *priv = dev_get_drvdata(master); 1219 struct platform_device *pdev = to_platform_device(dev); 1220 struct drm_device *ddev = priv->dev; 1221 struct dpu_kms *dpu_kms; 1222 struct dss_module_power *mp; 1223 int ret = 0; 1224 1225 dpu_kms = devm_kzalloc(&pdev->dev, sizeof(*dpu_kms), GFP_KERNEL); 1226 if (!dpu_kms) 1227 return -ENOMEM; 1228 1229 ret = devm_pm_opp_set_clkname(dev, "core"); 1230 if (ret) 1231 return ret; 1232 /* OPP table is optional */ 1233 ret = devm_pm_opp_of_add_table(dev); 1234 if (ret && ret != -ENODEV) { 1235 dev_err(dev, "invalid OPP table in device tree\n"); 1236 return ret; 1237 } 1238 1239 mp = &dpu_kms->mp; 1240 ret = msm_dss_parse_clock(pdev, mp); 1241 if (ret) { 1242 DPU_ERROR("failed to parse clocks, ret=%d\n", ret); 1243 return ret; 1244 } 1245 1246 platform_set_drvdata(pdev, dpu_kms); 1247 1248 ret = msm_kms_init(&dpu_kms->base, &kms_funcs); 1249 if (ret) { 1250 DPU_ERROR("failed to init kms, ret=%d\n", ret); 1251 return ret; 1252 } 1253 dpu_kms->dev = ddev; 1254 dpu_kms->pdev = pdev; 1255 1256 pm_runtime_enable(&pdev->dev); 1257 dpu_kms->rpm_enabled = true; 1258 1259 priv->kms = &dpu_kms->base; 1260 1261 return ret; 1262 } 1263 1264 static void dpu_unbind(struct device *dev, struct device *master, void *data) 1265 { 1266 struct platform_device *pdev = to_platform_device(dev); 1267 struct dpu_kms *dpu_kms = platform_get_drvdata(pdev); 1268 struct dss_module_power *mp = &dpu_kms->mp; 1269 1270 msm_dss_put_clk(mp->clk_config, mp->num_clk); 1271 devm_kfree(&pdev->dev, mp->clk_config); 1272 mp->num_clk = 0; 1273 1274 if (dpu_kms->rpm_enabled) 1275 pm_runtime_disable(&pdev->dev); 1276 } 1277 1278 static const struct component_ops dpu_ops = { 1279 .bind = dpu_bind, 1280 .unbind = dpu_unbind, 1281 }; 1282 1283 static int dpu_dev_probe(struct platform_device *pdev) 1284 { 1285 return component_add(&pdev->dev, &dpu_ops); 1286 } 1287 1288 static int dpu_dev_remove(struct platform_device *pdev) 1289 { 1290 component_del(&pdev->dev, &dpu_ops); 1291 return 0; 1292 } 1293 1294 static int __maybe_unused dpu_runtime_suspend(struct device *dev) 1295 { 1296 int i, rc = -1; 1297 struct platform_device *pdev = to_platform_device(dev); 1298 struct dpu_kms *dpu_kms = platform_get_drvdata(pdev); 1299 struct dss_module_power *mp = &dpu_kms->mp; 1300 1301 /* Drop the performance state vote */ 1302 dev_pm_opp_set_rate(dev, 0); 1303 rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, false); 1304 if (rc) 1305 DPU_ERROR("clock disable failed rc:%d\n", rc); 1306 1307 for (i = 0; i < dpu_kms->num_paths; i++) 1308 icc_set_bw(dpu_kms->path[i], 0, 0); 1309 1310 return rc; 1311 } 1312 1313 static int __maybe_unused dpu_runtime_resume(struct device *dev) 1314 { 1315 int rc = -1; 1316 struct platform_device *pdev = to_platform_device(dev); 1317 struct dpu_kms *dpu_kms = platform_get_drvdata(pdev); 1318 struct drm_encoder *encoder; 1319 struct drm_device *ddev; 1320 struct dss_module_power *mp = &dpu_kms->mp; 1321 int i; 1322 1323 ddev = dpu_kms->dev; 1324 1325 WARN_ON(!(dpu_kms->num_paths)); 1326 /* Min vote of BW is required before turning on AXI clk */ 1327 for (i = 0; i < dpu_kms->num_paths; i++) 1328 icc_set_bw(dpu_kms->path[i], 0, Bps_to_icc(MIN_IB_BW)); 1329 1330 rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, true); 1331 if (rc) { 1332 DPU_ERROR("clock enable failed rc:%d\n", rc); 1333 return rc; 1334 } 1335 1336 dpu_vbif_init_memtypes(dpu_kms); 1337 1338 drm_for_each_encoder(encoder, ddev) 1339 dpu_encoder_virt_runtime_resume(encoder); 1340 1341 return rc; 1342 } 1343 1344 static const struct dev_pm_ops dpu_pm_ops = { 1345 SET_RUNTIME_PM_OPS(dpu_runtime_suspend, dpu_runtime_resume, NULL) 1346 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1347 pm_runtime_force_resume) 1348 }; 1349 1350 const struct of_device_id dpu_dt_match[] = { 1351 { .compatible = "qcom,sdm845-dpu", }, 1352 { .compatible = "qcom,sc7180-dpu", }, 1353 { .compatible = "qcom,sc7280-dpu", }, 1354 { .compatible = "qcom,sm8150-dpu", }, 1355 { .compatible = "qcom,sm8250-dpu", }, 1356 {} 1357 }; 1358 MODULE_DEVICE_TABLE(of, dpu_dt_match); 1359 1360 static struct platform_driver dpu_driver = { 1361 .probe = dpu_dev_probe, 1362 .remove = dpu_dev_remove, 1363 .driver = { 1364 .name = "msm_dpu", 1365 .of_match_table = dpu_dt_match, 1366 .pm = &dpu_pm_ops, 1367 }, 1368 }; 1369 1370 void __init msm_dpu_register(void) 1371 { 1372 platform_driver_register(&dpu_driver); 1373 } 1374 1375 void __exit msm_dpu_unregister(void) 1376 { 1377 platform_driver_unregister(&dpu_driver); 1378 } 1379