1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ 9 10 #include <linux/debugfs.h> 11 #include <linux/dma-buf.h> 12 #include <linux/of_irq.h> 13 14 #include <drm/drm_crtc.h> 15 #include <drm/drm_file.h> 16 17 #include "msm_drv.h" 18 #include "msm_mmu.h" 19 #include "msm_gem.h" 20 21 #include "dpu_kms.h" 22 #include "dpu_core_irq.h" 23 #include "dpu_formats.h" 24 #include "dpu_hw_vbif.h" 25 #include "dpu_vbif.h" 26 #include "dpu_encoder.h" 27 #include "dpu_plane.h" 28 #include "dpu_crtc.h" 29 30 #define CREATE_TRACE_POINTS 31 #include "dpu_trace.h" 32 33 /* 34 * To enable overall DRM driver logging 35 * # echo 0x2 > /sys/module/drm/parameters/debug 36 * 37 * To enable DRM driver h/w logging 38 * # echo <mask> > /sys/kernel/debug/dri/0/debug/hw_log_mask 39 * 40 * See dpu_hw_mdss.h for h/w logging mask definitions (search for DPU_DBG_MASK_) 41 */ 42 #define DPU_DEBUGFS_DIR "msm_dpu" 43 #define DPU_DEBUGFS_HWMASKNAME "hw_log_mask" 44 45 static int dpu_kms_hw_init(struct msm_kms *kms); 46 static void _dpu_kms_mmu_destroy(struct dpu_kms *dpu_kms); 47 48 static unsigned long dpu_iomap_size(struct platform_device *pdev, 49 const char *name) 50 { 51 struct resource *res; 52 53 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name); 54 if (!res) { 55 DRM_ERROR("failed to get memory resource: %s\n", name); 56 return 0; 57 } 58 59 return resource_size(res); 60 } 61 62 #ifdef CONFIG_DEBUG_FS 63 static int _dpu_danger_signal_status(struct seq_file *s, 64 bool danger_status) 65 { 66 struct dpu_kms *kms = (struct dpu_kms *)s->private; 67 struct dpu_danger_safe_status status; 68 int i; 69 70 if (!kms->hw_mdp) { 71 DPU_ERROR("invalid arg(s)\n"); 72 return 0; 73 } 74 75 memset(&status, 0, sizeof(struct dpu_danger_safe_status)); 76 77 pm_runtime_get_sync(&kms->pdev->dev); 78 if (danger_status) { 79 seq_puts(s, "\nDanger signal status:\n"); 80 if (kms->hw_mdp->ops.get_danger_status) 81 kms->hw_mdp->ops.get_danger_status(kms->hw_mdp, 82 &status); 83 } else { 84 seq_puts(s, "\nSafe signal status:\n"); 85 if (kms->hw_mdp->ops.get_danger_status) 86 kms->hw_mdp->ops.get_danger_status(kms->hw_mdp, 87 &status); 88 } 89 pm_runtime_put_sync(&kms->pdev->dev); 90 91 seq_printf(s, "MDP : 0x%x\n", status.mdp); 92 93 for (i = SSPP_VIG0; i < SSPP_MAX; i++) 94 seq_printf(s, "SSPP%d : 0x%x \t", i - SSPP_VIG0, 95 status.sspp[i]); 96 seq_puts(s, "\n"); 97 98 return 0; 99 } 100 101 #define DEFINE_DPU_DEBUGFS_SEQ_FOPS(__prefix) \ 102 static int __prefix ## _open(struct inode *inode, struct file *file) \ 103 { \ 104 return single_open(file, __prefix ## _show, inode->i_private); \ 105 } \ 106 static const struct file_operations __prefix ## _fops = { \ 107 .owner = THIS_MODULE, \ 108 .open = __prefix ## _open, \ 109 .release = single_release, \ 110 .read = seq_read, \ 111 .llseek = seq_lseek, \ 112 } 113 114 static int dpu_debugfs_danger_stats_show(struct seq_file *s, void *v) 115 { 116 return _dpu_danger_signal_status(s, true); 117 } 118 DEFINE_DPU_DEBUGFS_SEQ_FOPS(dpu_debugfs_danger_stats); 119 120 static int dpu_debugfs_safe_stats_show(struct seq_file *s, void *v) 121 { 122 return _dpu_danger_signal_status(s, false); 123 } 124 DEFINE_DPU_DEBUGFS_SEQ_FOPS(dpu_debugfs_safe_stats); 125 126 static void dpu_debugfs_danger_init(struct dpu_kms *dpu_kms, 127 struct dentry *parent) 128 { 129 struct dentry *entry = debugfs_create_dir("danger", parent); 130 131 debugfs_create_file("danger_status", 0600, entry, 132 dpu_kms, &dpu_debugfs_danger_stats_fops); 133 debugfs_create_file("safe_status", 0600, entry, 134 dpu_kms, &dpu_debugfs_safe_stats_fops); 135 } 136 137 static int _dpu_debugfs_show_regset32(struct seq_file *s, void *data) 138 { 139 struct dpu_debugfs_regset32 *regset = s->private; 140 struct dpu_kms *dpu_kms = regset->dpu_kms; 141 void __iomem *base; 142 uint32_t i, addr; 143 144 if (!dpu_kms->mmio) 145 return 0; 146 147 base = dpu_kms->mmio + regset->offset; 148 149 /* insert padding spaces, if needed */ 150 if (regset->offset & 0xF) { 151 seq_printf(s, "[%x]", regset->offset & ~0xF); 152 for (i = 0; i < (regset->offset & 0xF); i += 4) 153 seq_puts(s, " "); 154 } 155 156 pm_runtime_get_sync(&dpu_kms->pdev->dev); 157 158 /* main register output */ 159 for (i = 0; i < regset->blk_len; i += 4) { 160 addr = regset->offset + i; 161 if ((addr & 0xF) == 0x0) 162 seq_printf(s, i ? "\n[%x]" : "[%x]", addr); 163 seq_printf(s, " %08x", readl_relaxed(base + i)); 164 } 165 seq_puts(s, "\n"); 166 pm_runtime_put_sync(&dpu_kms->pdev->dev); 167 168 return 0; 169 } 170 171 static int dpu_debugfs_open_regset32(struct inode *inode, 172 struct file *file) 173 { 174 return single_open(file, _dpu_debugfs_show_regset32, inode->i_private); 175 } 176 177 static const struct file_operations dpu_fops_regset32 = { 178 .open = dpu_debugfs_open_regset32, 179 .read = seq_read, 180 .llseek = seq_lseek, 181 .release = single_release, 182 }; 183 184 void dpu_debugfs_setup_regset32(struct dpu_debugfs_regset32 *regset, 185 uint32_t offset, uint32_t length, struct dpu_kms *dpu_kms) 186 { 187 if (regset) { 188 regset->offset = offset; 189 regset->blk_len = length; 190 regset->dpu_kms = dpu_kms; 191 } 192 } 193 194 void dpu_debugfs_create_regset32(const char *name, umode_t mode, 195 void *parent, struct dpu_debugfs_regset32 *regset) 196 { 197 if (!name || !regset || !regset->dpu_kms || !regset->blk_len) 198 return; 199 200 /* make sure offset is a multiple of 4 */ 201 regset->offset = round_down(regset->offset, 4); 202 203 debugfs_create_file(name, mode, parent, regset, &dpu_fops_regset32); 204 } 205 206 static int dpu_kms_debugfs_init(struct msm_kms *kms, struct drm_minor *minor) 207 { 208 struct dpu_kms *dpu_kms = to_dpu_kms(kms); 209 void *p = dpu_hw_util_get_log_mask_ptr(); 210 struct dentry *entry; 211 212 if (!p) 213 return -EINVAL; 214 215 entry = debugfs_create_dir("debug", minor->debugfs_root); 216 217 debugfs_create_x32(DPU_DEBUGFS_HWMASKNAME, 0600, entry, p); 218 219 dpu_debugfs_danger_init(dpu_kms, entry); 220 dpu_debugfs_vbif_init(dpu_kms, entry); 221 dpu_debugfs_core_irq_init(dpu_kms, entry); 222 223 return dpu_core_perf_debugfs_init(dpu_kms, entry); 224 } 225 #endif 226 227 /* Global/shared object state funcs */ 228 229 /* 230 * This is a helper that returns the private state currently in operation. 231 * Note that this would return the "old_state" if called in the atomic check 232 * path, and the "new_state" after the atomic swap has been done. 233 */ 234 struct dpu_global_state * 235 dpu_kms_get_existing_global_state(struct dpu_kms *dpu_kms) 236 { 237 return to_dpu_global_state(dpu_kms->global_state.state); 238 } 239 240 /* 241 * This acquires the modeset lock set aside for global state, creates 242 * a new duplicated private object state. 243 */ 244 struct dpu_global_state *dpu_kms_get_global_state(struct drm_atomic_state *s) 245 { 246 struct msm_drm_private *priv = s->dev->dev_private; 247 struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms); 248 struct drm_private_state *priv_state; 249 int ret; 250 251 ret = drm_modeset_lock(&dpu_kms->global_state_lock, s->acquire_ctx); 252 if (ret) 253 return ERR_PTR(ret); 254 255 priv_state = drm_atomic_get_private_obj_state(s, 256 &dpu_kms->global_state); 257 if (IS_ERR(priv_state)) 258 return ERR_CAST(priv_state); 259 260 return to_dpu_global_state(priv_state); 261 } 262 263 static struct drm_private_state * 264 dpu_kms_global_duplicate_state(struct drm_private_obj *obj) 265 { 266 struct dpu_global_state *state; 267 268 state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL); 269 if (!state) 270 return NULL; 271 272 __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base); 273 274 return &state->base; 275 } 276 277 static void dpu_kms_global_destroy_state(struct drm_private_obj *obj, 278 struct drm_private_state *state) 279 { 280 struct dpu_global_state *dpu_state = to_dpu_global_state(state); 281 282 kfree(dpu_state); 283 } 284 285 static const struct drm_private_state_funcs dpu_kms_global_state_funcs = { 286 .atomic_duplicate_state = dpu_kms_global_duplicate_state, 287 .atomic_destroy_state = dpu_kms_global_destroy_state, 288 }; 289 290 static int dpu_kms_global_obj_init(struct dpu_kms *dpu_kms) 291 { 292 struct dpu_global_state *state; 293 294 drm_modeset_lock_init(&dpu_kms->global_state_lock); 295 296 state = kzalloc(sizeof(*state), GFP_KERNEL); 297 if (!state) 298 return -ENOMEM; 299 300 drm_atomic_private_obj_init(dpu_kms->dev, &dpu_kms->global_state, 301 &state->base, 302 &dpu_kms_global_state_funcs); 303 return 0; 304 } 305 306 static int dpu_kms_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc) 307 { 308 return dpu_crtc_vblank(crtc, true); 309 } 310 311 static void dpu_kms_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc) 312 { 313 dpu_crtc_vblank(crtc, false); 314 } 315 316 static void dpu_kms_enable_commit(struct msm_kms *kms) 317 { 318 struct dpu_kms *dpu_kms = to_dpu_kms(kms); 319 pm_runtime_get_sync(&dpu_kms->pdev->dev); 320 } 321 322 static void dpu_kms_disable_commit(struct msm_kms *kms) 323 { 324 struct dpu_kms *dpu_kms = to_dpu_kms(kms); 325 pm_runtime_put_sync(&dpu_kms->pdev->dev); 326 } 327 328 static ktime_t dpu_kms_vsync_time(struct msm_kms *kms, struct drm_crtc *crtc) 329 { 330 struct drm_encoder *encoder; 331 332 drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) { 333 ktime_t vsync_time; 334 335 if (dpu_encoder_vsync_time(encoder, &vsync_time) == 0) 336 return vsync_time; 337 } 338 339 return ktime_get(); 340 } 341 342 static void dpu_kms_prepare_commit(struct msm_kms *kms, 343 struct drm_atomic_state *state) 344 { 345 struct drm_crtc *crtc; 346 struct drm_crtc_state *crtc_state; 347 struct drm_encoder *encoder; 348 int i; 349 350 if (!kms) 351 return; 352 353 /* Call prepare_commit for all affected encoders */ 354 for_each_new_crtc_in_state(state, crtc, crtc_state, i) { 355 drm_for_each_encoder_mask(encoder, crtc->dev, 356 crtc_state->encoder_mask) { 357 dpu_encoder_prepare_commit(encoder); 358 } 359 } 360 } 361 362 static void dpu_kms_flush_commit(struct msm_kms *kms, unsigned crtc_mask) 363 { 364 struct dpu_kms *dpu_kms = to_dpu_kms(kms); 365 struct drm_crtc *crtc; 366 367 for_each_crtc_mask(dpu_kms->dev, crtc, crtc_mask) { 368 if (!crtc->state->active) 369 continue; 370 371 trace_dpu_kms_commit(DRMID(crtc)); 372 dpu_crtc_commit_kickoff(crtc); 373 } 374 } 375 376 /* 377 * Override the encoder enable since we need to setup the inline rotator and do 378 * some crtc magic before enabling any bridge that might be present. 379 */ 380 void dpu_kms_encoder_enable(struct drm_encoder *encoder) 381 { 382 const struct drm_encoder_helper_funcs *funcs = encoder->helper_private; 383 struct drm_device *dev = encoder->dev; 384 struct drm_crtc *crtc; 385 386 /* Forward this enable call to the commit hook */ 387 if (funcs && funcs->commit) 388 funcs->commit(encoder); 389 390 drm_for_each_crtc(crtc, dev) { 391 if (!(crtc->state->encoder_mask & drm_encoder_mask(encoder))) 392 continue; 393 394 trace_dpu_kms_enc_enable(DRMID(crtc)); 395 } 396 } 397 398 static void dpu_kms_complete_commit(struct msm_kms *kms, unsigned crtc_mask) 399 { 400 struct dpu_kms *dpu_kms = to_dpu_kms(kms); 401 struct drm_crtc *crtc; 402 403 DPU_ATRACE_BEGIN("kms_complete_commit"); 404 405 for_each_crtc_mask(dpu_kms->dev, crtc, crtc_mask) 406 dpu_crtc_complete_commit(crtc); 407 408 DPU_ATRACE_END("kms_complete_commit"); 409 } 410 411 static void dpu_kms_wait_for_commit_done(struct msm_kms *kms, 412 struct drm_crtc *crtc) 413 { 414 struct drm_encoder *encoder; 415 struct drm_device *dev; 416 int ret; 417 418 if (!kms || !crtc || !crtc->state) { 419 DPU_ERROR("invalid params\n"); 420 return; 421 } 422 423 dev = crtc->dev; 424 425 if (!crtc->state->enable) { 426 DPU_DEBUG("[crtc:%d] not enable\n", crtc->base.id); 427 return; 428 } 429 430 if (!crtc->state->active) { 431 DPU_DEBUG("[crtc:%d] not active\n", crtc->base.id); 432 return; 433 } 434 435 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 436 if (encoder->crtc != crtc) 437 continue; 438 /* 439 * Wait for post-flush if necessary to delay before 440 * plane_cleanup. For example, wait for vsync in case of video 441 * mode panels. This may be a no-op for command mode panels. 442 */ 443 trace_dpu_kms_wait_for_commit_done(DRMID(crtc)); 444 ret = dpu_encoder_wait_for_event(encoder, MSM_ENC_COMMIT_DONE); 445 if (ret && ret != -EWOULDBLOCK) { 446 DPU_ERROR("wait for commit done returned %d\n", ret); 447 break; 448 } 449 } 450 } 451 452 static void dpu_kms_wait_flush(struct msm_kms *kms, unsigned crtc_mask) 453 { 454 struct dpu_kms *dpu_kms = to_dpu_kms(kms); 455 struct drm_crtc *crtc; 456 457 for_each_crtc_mask(dpu_kms->dev, crtc, crtc_mask) 458 dpu_kms_wait_for_commit_done(kms, crtc); 459 } 460 461 static int _dpu_kms_initialize_dsi(struct drm_device *dev, 462 struct msm_drm_private *priv, 463 struct dpu_kms *dpu_kms) 464 { 465 struct drm_encoder *encoder = NULL; 466 int i, rc = 0; 467 468 if (!(priv->dsi[0] || priv->dsi[1])) 469 return rc; 470 471 /*TODO: Support two independent DSI connectors */ 472 encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_DSI); 473 if (IS_ERR(encoder)) { 474 DPU_ERROR("encoder init failed for dsi display\n"); 475 return PTR_ERR(encoder); 476 } 477 478 priv->encoders[priv->num_encoders++] = encoder; 479 480 for (i = 0; i < ARRAY_SIZE(priv->dsi); i++) { 481 if (!priv->dsi[i]) 482 continue; 483 484 rc = msm_dsi_modeset_init(priv->dsi[i], dev, encoder); 485 if (rc) { 486 DPU_ERROR("modeset_init failed for dsi[%d], rc = %d\n", 487 i, rc); 488 break; 489 } 490 } 491 492 return rc; 493 } 494 495 /** 496 * _dpu_kms_setup_displays - create encoders, bridges and connectors 497 * for underlying displays 498 * @dev: Pointer to drm device structure 499 * @priv: Pointer to private drm device data 500 * @dpu_kms: Pointer to dpu kms structure 501 * Returns: Zero on success 502 */ 503 static int _dpu_kms_setup_displays(struct drm_device *dev, 504 struct msm_drm_private *priv, 505 struct dpu_kms *dpu_kms) 506 { 507 /** 508 * Extend this function to initialize other 509 * types of displays 510 */ 511 512 return _dpu_kms_initialize_dsi(dev, priv, dpu_kms); 513 } 514 515 static void _dpu_kms_drm_obj_destroy(struct dpu_kms *dpu_kms) 516 { 517 struct msm_drm_private *priv; 518 int i; 519 520 priv = dpu_kms->dev->dev_private; 521 522 for (i = 0; i < priv->num_crtcs; i++) 523 priv->crtcs[i]->funcs->destroy(priv->crtcs[i]); 524 priv->num_crtcs = 0; 525 526 for (i = 0; i < priv->num_planes; i++) 527 priv->planes[i]->funcs->destroy(priv->planes[i]); 528 priv->num_planes = 0; 529 530 for (i = 0; i < priv->num_connectors; i++) 531 priv->connectors[i]->funcs->destroy(priv->connectors[i]); 532 priv->num_connectors = 0; 533 534 for (i = 0; i < priv->num_encoders; i++) 535 priv->encoders[i]->funcs->destroy(priv->encoders[i]); 536 priv->num_encoders = 0; 537 } 538 539 static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms) 540 { 541 struct drm_device *dev; 542 struct drm_plane *primary_planes[MAX_PLANES], *plane; 543 struct drm_plane *cursor_planes[MAX_PLANES] = { NULL }; 544 struct drm_crtc *crtc; 545 546 struct msm_drm_private *priv; 547 struct dpu_mdss_cfg *catalog; 548 549 int primary_planes_idx = 0, cursor_planes_idx = 0, i, ret; 550 int max_crtc_count; 551 dev = dpu_kms->dev; 552 priv = dev->dev_private; 553 catalog = dpu_kms->catalog; 554 555 /* 556 * Create encoder and query display drivers to create 557 * bridges and connectors 558 */ 559 ret = _dpu_kms_setup_displays(dev, priv, dpu_kms); 560 if (ret) 561 goto fail; 562 563 max_crtc_count = min(catalog->mixer_count, priv->num_encoders); 564 565 /* Create the planes, keeping track of one primary/cursor per crtc */ 566 for (i = 0; i < catalog->sspp_count; i++) { 567 enum drm_plane_type type; 568 569 if ((catalog->sspp[i].features & BIT(DPU_SSPP_CURSOR)) 570 && cursor_planes_idx < max_crtc_count) 571 type = DRM_PLANE_TYPE_CURSOR; 572 else if (primary_planes_idx < max_crtc_count) 573 type = DRM_PLANE_TYPE_PRIMARY; 574 else 575 type = DRM_PLANE_TYPE_OVERLAY; 576 577 DPU_DEBUG("Create plane type %d with features %lx (cur %lx)\n", 578 type, catalog->sspp[i].features, 579 catalog->sspp[i].features & BIT(DPU_SSPP_CURSOR)); 580 581 plane = dpu_plane_init(dev, catalog->sspp[i].id, type, 582 (1UL << max_crtc_count) - 1, 0); 583 if (IS_ERR(plane)) { 584 DPU_ERROR("dpu_plane_init failed\n"); 585 ret = PTR_ERR(plane); 586 goto fail; 587 } 588 priv->planes[priv->num_planes++] = plane; 589 590 if (type == DRM_PLANE_TYPE_CURSOR) 591 cursor_planes[cursor_planes_idx++] = plane; 592 else if (type == DRM_PLANE_TYPE_PRIMARY) 593 primary_planes[primary_planes_idx++] = plane; 594 } 595 596 max_crtc_count = min(max_crtc_count, primary_planes_idx); 597 598 /* Create one CRTC per encoder */ 599 for (i = 0; i < max_crtc_count; i++) { 600 crtc = dpu_crtc_init(dev, primary_planes[i], cursor_planes[i]); 601 if (IS_ERR(crtc)) { 602 ret = PTR_ERR(crtc); 603 goto fail; 604 } 605 priv->crtcs[priv->num_crtcs++] = crtc; 606 } 607 608 /* All CRTCs are compatible with all encoders */ 609 for (i = 0; i < priv->num_encoders; i++) 610 priv->encoders[i]->possible_crtcs = (1 << priv->num_crtcs) - 1; 611 612 return 0; 613 fail: 614 _dpu_kms_drm_obj_destroy(dpu_kms); 615 return ret; 616 } 617 618 static long dpu_kms_round_pixclk(struct msm_kms *kms, unsigned long rate, 619 struct drm_encoder *encoder) 620 { 621 return rate; 622 } 623 624 static void _dpu_kms_hw_destroy(struct dpu_kms *dpu_kms) 625 { 626 int i; 627 628 if (dpu_kms->hw_intr) 629 dpu_hw_intr_destroy(dpu_kms->hw_intr); 630 dpu_kms->hw_intr = NULL; 631 632 /* safe to call these more than once during shutdown */ 633 _dpu_kms_mmu_destroy(dpu_kms); 634 635 if (dpu_kms->catalog) { 636 for (i = 0; i < dpu_kms->catalog->vbif_count; i++) { 637 u32 vbif_idx = dpu_kms->catalog->vbif[i].id; 638 639 if ((vbif_idx < VBIF_MAX) && dpu_kms->hw_vbif[vbif_idx]) 640 dpu_hw_vbif_destroy(dpu_kms->hw_vbif[vbif_idx]); 641 } 642 } 643 644 if (dpu_kms->rm_init) 645 dpu_rm_destroy(&dpu_kms->rm); 646 dpu_kms->rm_init = false; 647 648 if (dpu_kms->catalog) 649 dpu_hw_catalog_deinit(dpu_kms->catalog); 650 dpu_kms->catalog = NULL; 651 652 if (dpu_kms->vbif[VBIF_NRT]) 653 devm_iounmap(&dpu_kms->pdev->dev, dpu_kms->vbif[VBIF_NRT]); 654 dpu_kms->vbif[VBIF_NRT] = NULL; 655 656 if (dpu_kms->vbif[VBIF_RT]) 657 devm_iounmap(&dpu_kms->pdev->dev, dpu_kms->vbif[VBIF_RT]); 658 dpu_kms->vbif[VBIF_RT] = NULL; 659 660 if (dpu_kms->hw_mdp) 661 dpu_hw_mdp_destroy(dpu_kms->hw_mdp); 662 dpu_kms->hw_mdp = NULL; 663 664 if (dpu_kms->mmio) 665 devm_iounmap(&dpu_kms->pdev->dev, dpu_kms->mmio); 666 dpu_kms->mmio = NULL; 667 } 668 669 static void dpu_kms_destroy(struct msm_kms *kms) 670 { 671 struct dpu_kms *dpu_kms; 672 673 if (!kms) { 674 DPU_ERROR("invalid kms\n"); 675 return; 676 } 677 678 dpu_kms = to_dpu_kms(kms); 679 680 _dpu_kms_hw_destroy(dpu_kms); 681 } 682 683 static void _dpu_kms_set_encoder_mode(struct msm_kms *kms, 684 struct drm_encoder *encoder, 685 bool cmd_mode) 686 { 687 struct msm_display_info info; 688 struct msm_drm_private *priv = encoder->dev->dev_private; 689 int i, rc = 0; 690 691 memset(&info, 0, sizeof(info)); 692 693 info.intf_type = encoder->encoder_type; 694 info.capabilities = cmd_mode ? MSM_DISPLAY_CAP_CMD_MODE : 695 MSM_DISPLAY_CAP_VID_MODE; 696 697 /* TODO: No support for DSI swap */ 698 for (i = 0; i < ARRAY_SIZE(priv->dsi); i++) { 699 if (priv->dsi[i]) { 700 info.h_tile_instance[info.num_of_h_tiles] = i; 701 info.num_of_h_tiles++; 702 } 703 } 704 705 rc = dpu_encoder_setup(encoder->dev, encoder, &info); 706 if (rc) 707 DPU_ERROR("failed to setup DPU encoder %d: rc:%d\n", 708 encoder->base.id, rc); 709 } 710 711 static irqreturn_t dpu_irq(struct msm_kms *kms) 712 { 713 struct dpu_kms *dpu_kms = to_dpu_kms(kms); 714 715 return dpu_core_irq(dpu_kms); 716 } 717 718 static void dpu_irq_preinstall(struct msm_kms *kms) 719 { 720 struct dpu_kms *dpu_kms = to_dpu_kms(kms); 721 722 dpu_core_irq_preinstall(dpu_kms); 723 } 724 725 static void dpu_irq_uninstall(struct msm_kms *kms) 726 { 727 struct dpu_kms *dpu_kms = to_dpu_kms(kms); 728 729 dpu_core_irq_uninstall(dpu_kms); 730 } 731 732 static const struct msm_kms_funcs kms_funcs = { 733 .hw_init = dpu_kms_hw_init, 734 .irq_preinstall = dpu_irq_preinstall, 735 .irq_uninstall = dpu_irq_uninstall, 736 .irq = dpu_irq, 737 .enable_commit = dpu_kms_enable_commit, 738 .disable_commit = dpu_kms_disable_commit, 739 .vsync_time = dpu_kms_vsync_time, 740 .prepare_commit = dpu_kms_prepare_commit, 741 .flush_commit = dpu_kms_flush_commit, 742 .wait_flush = dpu_kms_wait_flush, 743 .complete_commit = dpu_kms_complete_commit, 744 .enable_vblank = dpu_kms_enable_vblank, 745 .disable_vblank = dpu_kms_disable_vblank, 746 .check_modified_format = dpu_format_check_modified_format, 747 .get_format = dpu_get_msm_format, 748 .round_pixclk = dpu_kms_round_pixclk, 749 .destroy = dpu_kms_destroy, 750 .set_encoder_mode = _dpu_kms_set_encoder_mode, 751 #ifdef CONFIG_DEBUG_FS 752 .debugfs_init = dpu_kms_debugfs_init, 753 #endif 754 }; 755 756 static void _dpu_kms_mmu_destroy(struct dpu_kms *dpu_kms) 757 { 758 struct msm_mmu *mmu; 759 760 if (!dpu_kms->base.aspace) 761 return; 762 763 mmu = dpu_kms->base.aspace->mmu; 764 765 mmu->funcs->detach(mmu); 766 msm_gem_address_space_put(dpu_kms->base.aspace); 767 768 dpu_kms->base.aspace = NULL; 769 } 770 771 static int _dpu_kms_mmu_init(struct dpu_kms *dpu_kms) 772 { 773 struct iommu_domain *domain; 774 struct msm_gem_address_space *aspace; 775 struct msm_mmu *mmu; 776 777 domain = iommu_domain_alloc(&platform_bus_type); 778 if (!domain) 779 return 0; 780 781 mmu = msm_iommu_new(dpu_kms->dev->dev, domain); 782 aspace = msm_gem_address_space_create(mmu, "dpu1", 783 0x1000, 0xfffffff); 784 785 if (IS_ERR(aspace)) { 786 mmu->funcs->destroy(mmu); 787 return PTR_ERR(aspace); 788 } 789 790 dpu_kms->base.aspace = aspace; 791 return 0; 792 } 793 794 static struct dss_clk *_dpu_kms_get_clk(struct dpu_kms *dpu_kms, 795 char *clock_name) 796 { 797 struct dss_module_power *mp = &dpu_kms->mp; 798 int i; 799 800 for (i = 0; i < mp->num_clk; i++) { 801 if (!strcmp(mp->clk_config[i].clk_name, clock_name)) 802 return &mp->clk_config[i]; 803 } 804 805 return NULL; 806 } 807 808 u64 dpu_kms_get_clk_rate(struct dpu_kms *dpu_kms, char *clock_name) 809 { 810 struct dss_clk *clk; 811 812 clk = _dpu_kms_get_clk(dpu_kms, clock_name); 813 if (!clk) 814 return -EINVAL; 815 816 return clk_get_rate(clk->clk); 817 } 818 819 static int dpu_kms_hw_init(struct msm_kms *kms) 820 { 821 struct dpu_kms *dpu_kms; 822 struct drm_device *dev; 823 int i, rc = -EINVAL; 824 825 if (!kms) { 826 DPU_ERROR("invalid kms\n"); 827 return rc; 828 } 829 830 dpu_kms = to_dpu_kms(kms); 831 dev = dpu_kms->dev; 832 833 rc = dpu_kms_global_obj_init(dpu_kms); 834 if (rc) 835 return rc; 836 837 atomic_set(&dpu_kms->bandwidth_ref, 0); 838 839 dpu_kms->mmio = msm_ioremap(dpu_kms->pdev, "mdp", "mdp"); 840 if (IS_ERR(dpu_kms->mmio)) { 841 rc = PTR_ERR(dpu_kms->mmio); 842 DPU_ERROR("mdp register memory map failed: %d\n", rc); 843 dpu_kms->mmio = NULL; 844 goto error; 845 } 846 DRM_DEBUG("mapped dpu address space @%pK\n", dpu_kms->mmio); 847 dpu_kms->mmio_len = dpu_iomap_size(dpu_kms->pdev, "mdp"); 848 849 dpu_kms->vbif[VBIF_RT] = msm_ioremap(dpu_kms->pdev, "vbif", "vbif"); 850 if (IS_ERR(dpu_kms->vbif[VBIF_RT])) { 851 rc = PTR_ERR(dpu_kms->vbif[VBIF_RT]); 852 DPU_ERROR("vbif register memory map failed: %d\n", rc); 853 dpu_kms->vbif[VBIF_RT] = NULL; 854 goto error; 855 } 856 dpu_kms->vbif_len[VBIF_RT] = dpu_iomap_size(dpu_kms->pdev, "vbif"); 857 dpu_kms->vbif[VBIF_NRT] = msm_ioremap(dpu_kms->pdev, "vbif_nrt", "vbif_nrt"); 858 if (IS_ERR(dpu_kms->vbif[VBIF_NRT])) { 859 dpu_kms->vbif[VBIF_NRT] = NULL; 860 DPU_DEBUG("VBIF NRT is not defined"); 861 } else { 862 dpu_kms->vbif_len[VBIF_NRT] = dpu_iomap_size(dpu_kms->pdev, 863 "vbif_nrt"); 864 } 865 866 dpu_kms->reg_dma = msm_ioremap(dpu_kms->pdev, "regdma", "regdma"); 867 if (IS_ERR(dpu_kms->reg_dma)) { 868 dpu_kms->reg_dma = NULL; 869 DPU_DEBUG("REG_DMA is not defined"); 870 } else { 871 dpu_kms->reg_dma_len = dpu_iomap_size(dpu_kms->pdev, "regdma"); 872 } 873 874 pm_runtime_get_sync(&dpu_kms->pdev->dev); 875 876 dpu_kms->core_rev = readl_relaxed(dpu_kms->mmio + 0x0); 877 878 pr_info("dpu hardware revision:0x%x\n", dpu_kms->core_rev); 879 880 dpu_kms->catalog = dpu_hw_catalog_init(dpu_kms->core_rev); 881 if (IS_ERR_OR_NULL(dpu_kms->catalog)) { 882 rc = PTR_ERR(dpu_kms->catalog); 883 if (!dpu_kms->catalog) 884 rc = -EINVAL; 885 DPU_ERROR("catalog init failed: %d\n", rc); 886 dpu_kms->catalog = NULL; 887 goto power_error; 888 } 889 890 /* 891 * Now we need to read the HW catalog and initialize resources such as 892 * clocks, regulators, GDSC/MMAGIC, ioremap the register ranges etc 893 */ 894 rc = _dpu_kms_mmu_init(dpu_kms); 895 if (rc) { 896 DPU_ERROR("dpu_kms_mmu_init failed: %d\n", rc); 897 goto power_error; 898 } 899 900 rc = dpu_rm_init(&dpu_kms->rm, dpu_kms->catalog, dpu_kms->mmio); 901 if (rc) { 902 DPU_ERROR("rm init failed: %d\n", rc); 903 goto power_error; 904 } 905 906 dpu_kms->rm_init = true; 907 908 dpu_kms->hw_mdp = dpu_hw_mdptop_init(MDP_TOP, dpu_kms->mmio, 909 dpu_kms->catalog); 910 if (IS_ERR(dpu_kms->hw_mdp)) { 911 rc = PTR_ERR(dpu_kms->hw_mdp); 912 DPU_ERROR("failed to get hw_mdp: %d\n", rc); 913 dpu_kms->hw_mdp = NULL; 914 goto power_error; 915 } 916 917 for (i = 0; i < dpu_kms->catalog->vbif_count; i++) { 918 u32 vbif_idx = dpu_kms->catalog->vbif[i].id; 919 920 dpu_kms->hw_vbif[i] = dpu_hw_vbif_init(vbif_idx, 921 dpu_kms->vbif[vbif_idx], dpu_kms->catalog); 922 if (IS_ERR_OR_NULL(dpu_kms->hw_vbif[vbif_idx])) { 923 rc = PTR_ERR(dpu_kms->hw_vbif[vbif_idx]); 924 if (!dpu_kms->hw_vbif[vbif_idx]) 925 rc = -EINVAL; 926 DPU_ERROR("failed to init vbif %d: %d\n", vbif_idx, rc); 927 dpu_kms->hw_vbif[vbif_idx] = NULL; 928 goto power_error; 929 } 930 } 931 932 rc = dpu_core_perf_init(&dpu_kms->perf, dev, dpu_kms->catalog, 933 _dpu_kms_get_clk(dpu_kms, "core")); 934 if (rc) { 935 DPU_ERROR("failed to init perf %d\n", rc); 936 goto perf_err; 937 } 938 939 dpu_kms->hw_intr = dpu_hw_intr_init(dpu_kms->mmio, dpu_kms->catalog); 940 if (IS_ERR_OR_NULL(dpu_kms->hw_intr)) { 941 rc = PTR_ERR(dpu_kms->hw_intr); 942 DPU_ERROR("hw_intr init failed: %d\n", rc); 943 dpu_kms->hw_intr = NULL; 944 goto hw_intr_init_err; 945 } 946 947 dev->mode_config.min_width = 0; 948 dev->mode_config.min_height = 0; 949 950 /* 951 * max crtc width is equal to the max mixer width * 2 and max height is 952 * is 4K 953 */ 954 dev->mode_config.max_width = 955 dpu_kms->catalog->caps->max_mixer_width * 2; 956 dev->mode_config.max_height = 4096; 957 958 /* 959 * Support format modifiers for compression etc. 960 */ 961 dev->mode_config.allow_fb_modifiers = true; 962 963 /* 964 * _dpu_kms_drm_obj_init should create the DRM related objects 965 * i.e. CRTCs, planes, encoders, connectors and so forth 966 */ 967 rc = _dpu_kms_drm_obj_init(dpu_kms); 968 if (rc) { 969 DPU_ERROR("modeset init failed: %d\n", rc); 970 goto drm_obj_init_err; 971 } 972 973 dpu_vbif_init_memtypes(dpu_kms); 974 975 pm_runtime_put_sync(&dpu_kms->pdev->dev); 976 977 return 0; 978 979 drm_obj_init_err: 980 dpu_core_perf_destroy(&dpu_kms->perf); 981 hw_intr_init_err: 982 perf_err: 983 power_error: 984 pm_runtime_put_sync(&dpu_kms->pdev->dev); 985 error: 986 _dpu_kms_hw_destroy(dpu_kms); 987 988 return rc; 989 } 990 991 struct msm_kms *dpu_kms_init(struct drm_device *dev) 992 { 993 struct msm_drm_private *priv; 994 struct dpu_kms *dpu_kms; 995 int irq; 996 997 if (!dev) { 998 DPU_ERROR("drm device node invalid\n"); 999 return ERR_PTR(-EINVAL); 1000 } 1001 1002 priv = dev->dev_private; 1003 dpu_kms = to_dpu_kms(priv->kms); 1004 1005 irq = irq_of_parse_and_map(dpu_kms->pdev->dev.of_node, 0); 1006 if (irq < 0) { 1007 DPU_ERROR("failed to get irq: %d\n", irq); 1008 return ERR_PTR(irq); 1009 } 1010 dpu_kms->base.irq = irq; 1011 1012 return &dpu_kms->base; 1013 } 1014 1015 static int dpu_bind(struct device *dev, struct device *master, void *data) 1016 { 1017 struct drm_device *ddev = dev_get_drvdata(master); 1018 struct platform_device *pdev = to_platform_device(dev); 1019 struct msm_drm_private *priv = ddev->dev_private; 1020 struct dpu_kms *dpu_kms; 1021 struct dss_module_power *mp; 1022 int ret = 0; 1023 1024 dpu_kms = devm_kzalloc(&pdev->dev, sizeof(*dpu_kms), GFP_KERNEL); 1025 if (!dpu_kms) 1026 return -ENOMEM; 1027 1028 mp = &dpu_kms->mp; 1029 ret = msm_dss_parse_clock(pdev, mp); 1030 if (ret) { 1031 DPU_ERROR("failed to parse clocks, ret=%d\n", ret); 1032 return ret; 1033 } 1034 1035 platform_set_drvdata(pdev, dpu_kms); 1036 1037 msm_kms_init(&dpu_kms->base, &kms_funcs); 1038 dpu_kms->dev = ddev; 1039 dpu_kms->pdev = pdev; 1040 1041 pm_runtime_enable(&pdev->dev); 1042 dpu_kms->rpm_enabled = true; 1043 1044 priv->kms = &dpu_kms->base; 1045 return ret; 1046 } 1047 1048 static void dpu_unbind(struct device *dev, struct device *master, void *data) 1049 { 1050 struct platform_device *pdev = to_platform_device(dev); 1051 struct dpu_kms *dpu_kms = platform_get_drvdata(pdev); 1052 struct dss_module_power *mp = &dpu_kms->mp; 1053 1054 msm_dss_put_clk(mp->clk_config, mp->num_clk); 1055 devm_kfree(&pdev->dev, mp->clk_config); 1056 mp->num_clk = 0; 1057 1058 if (dpu_kms->rpm_enabled) 1059 pm_runtime_disable(&pdev->dev); 1060 } 1061 1062 static const struct component_ops dpu_ops = { 1063 .bind = dpu_bind, 1064 .unbind = dpu_unbind, 1065 }; 1066 1067 static int dpu_dev_probe(struct platform_device *pdev) 1068 { 1069 return component_add(&pdev->dev, &dpu_ops); 1070 } 1071 1072 static int dpu_dev_remove(struct platform_device *pdev) 1073 { 1074 component_del(&pdev->dev, &dpu_ops); 1075 return 0; 1076 } 1077 1078 static int __maybe_unused dpu_runtime_suspend(struct device *dev) 1079 { 1080 int rc = -1; 1081 struct platform_device *pdev = to_platform_device(dev); 1082 struct dpu_kms *dpu_kms = platform_get_drvdata(pdev); 1083 struct dss_module_power *mp = &dpu_kms->mp; 1084 1085 rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, false); 1086 if (rc) 1087 DPU_ERROR("clock disable failed rc:%d\n", rc); 1088 1089 return rc; 1090 } 1091 1092 static int __maybe_unused dpu_runtime_resume(struct device *dev) 1093 { 1094 int rc = -1; 1095 struct platform_device *pdev = to_platform_device(dev); 1096 struct dpu_kms *dpu_kms = platform_get_drvdata(pdev); 1097 struct drm_encoder *encoder; 1098 struct drm_device *ddev; 1099 struct dss_module_power *mp = &dpu_kms->mp; 1100 1101 ddev = dpu_kms->dev; 1102 rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, true); 1103 if (rc) { 1104 DPU_ERROR("clock enable failed rc:%d\n", rc); 1105 return rc; 1106 } 1107 1108 dpu_vbif_init_memtypes(dpu_kms); 1109 1110 drm_for_each_encoder(encoder, ddev) 1111 dpu_encoder_virt_runtime_resume(encoder); 1112 1113 return rc; 1114 } 1115 1116 static const struct dev_pm_ops dpu_pm_ops = { 1117 SET_RUNTIME_PM_OPS(dpu_runtime_suspend, dpu_runtime_resume, NULL) 1118 }; 1119 1120 static const struct of_device_id dpu_dt_match[] = { 1121 { .compatible = "qcom,sdm845-dpu", }, 1122 { .compatible = "qcom,sc7180-dpu", }, 1123 {} 1124 }; 1125 MODULE_DEVICE_TABLE(of, dpu_dt_match); 1126 1127 static struct platform_driver dpu_driver = { 1128 .probe = dpu_dev_probe, 1129 .remove = dpu_dev_remove, 1130 .driver = { 1131 .name = "msm_dpu", 1132 .of_match_table = dpu_dt_match, 1133 .pm = &dpu_pm_ops, 1134 }, 1135 }; 1136 1137 void __init msm_dpu_register(void) 1138 { 1139 platform_driver_register(&dpu_driver); 1140 } 1141 1142 void __exit msm_dpu_unregister(void) 1143 { 1144 platform_driver_unregister(&dpu_driver); 1145 } 1146