1 /* 2 * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved. 3 * Copyright (C) 2013 Red Hat 4 * Author: Rob Clark <robdclark@gmail.com> 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published by 8 * the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ 20 21 #include <drm/drm_crtc.h> 22 #include <linux/debugfs.h> 23 #include <linux/of_irq.h> 24 #include <linux/dma-buf.h> 25 26 #include "msm_drv.h" 27 #include "msm_mmu.h" 28 #include "msm_gem.h" 29 30 #include "dpu_kms.h" 31 #include "dpu_core_irq.h" 32 #include "dpu_formats.h" 33 #include "dpu_hw_vbif.h" 34 #include "dpu_vbif.h" 35 #include "dpu_encoder.h" 36 #include "dpu_plane.h" 37 #include "dpu_crtc.h" 38 39 #define CREATE_TRACE_POINTS 40 #include "dpu_trace.h" 41 42 static const char * const iommu_ports[] = { 43 "mdp_0", 44 }; 45 46 /* 47 * To enable overall DRM driver logging 48 * # echo 0x2 > /sys/module/drm/parameters/debug 49 * 50 * To enable DRM driver h/w logging 51 * # echo <mask> > /sys/kernel/debug/dri/0/debug/hw_log_mask 52 * 53 * See dpu_hw_mdss.h for h/w logging mask definitions (search for DPU_DBG_MASK_) 54 */ 55 #define DPU_DEBUGFS_DIR "msm_dpu" 56 #define DPU_DEBUGFS_HWMASKNAME "hw_log_mask" 57 58 static int dpu_kms_hw_init(struct msm_kms *kms); 59 static int _dpu_kms_mmu_destroy(struct dpu_kms *dpu_kms); 60 61 static unsigned long dpu_iomap_size(struct platform_device *pdev, 62 const char *name) 63 { 64 struct resource *res; 65 66 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name); 67 if (!res) { 68 DRM_ERROR("failed to get memory resource: %s\n", name); 69 return 0; 70 } 71 72 return resource_size(res); 73 } 74 75 #ifdef CONFIG_DEBUG_FS 76 static int _dpu_danger_signal_status(struct seq_file *s, 77 bool danger_status) 78 { 79 struct dpu_kms *kms = (struct dpu_kms *)s->private; 80 struct msm_drm_private *priv; 81 struct dpu_danger_safe_status status; 82 int i; 83 84 if (!kms->dev || !kms->dev->dev_private || !kms->hw_mdp) { 85 DPU_ERROR("invalid arg(s)\n"); 86 return 0; 87 } 88 89 priv = kms->dev->dev_private; 90 memset(&status, 0, sizeof(struct dpu_danger_safe_status)); 91 92 pm_runtime_get_sync(&kms->pdev->dev); 93 if (danger_status) { 94 seq_puts(s, "\nDanger signal status:\n"); 95 if (kms->hw_mdp->ops.get_danger_status) 96 kms->hw_mdp->ops.get_danger_status(kms->hw_mdp, 97 &status); 98 } else { 99 seq_puts(s, "\nSafe signal status:\n"); 100 if (kms->hw_mdp->ops.get_danger_status) 101 kms->hw_mdp->ops.get_danger_status(kms->hw_mdp, 102 &status); 103 } 104 pm_runtime_put_sync(&kms->pdev->dev); 105 106 seq_printf(s, "MDP : 0x%x\n", status.mdp); 107 108 for (i = SSPP_VIG0; i < SSPP_MAX; i++) 109 seq_printf(s, "SSPP%d : 0x%x \t", i - SSPP_VIG0, 110 status.sspp[i]); 111 seq_puts(s, "\n"); 112 113 return 0; 114 } 115 116 #define DEFINE_DPU_DEBUGFS_SEQ_FOPS(__prefix) \ 117 static int __prefix ## _open(struct inode *inode, struct file *file) \ 118 { \ 119 return single_open(file, __prefix ## _show, inode->i_private); \ 120 } \ 121 static const struct file_operations __prefix ## _fops = { \ 122 .owner = THIS_MODULE, \ 123 .open = __prefix ## _open, \ 124 .release = single_release, \ 125 .read = seq_read, \ 126 .llseek = seq_lseek, \ 127 } 128 129 static int dpu_debugfs_danger_stats_show(struct seq_file *s, void *v) 130 { 131 return _dpu_danger_signal_status(s, true); 132 } 133 DEFINE_DPU_DEBUGFS_SEQ_FOPS(dpu_debugfs_danger_stats); 134 135 static int dpu_debugfs_safe_stats_show(struct seq_file *s, void *v) 136 { 137 return _dpu_danger_signal_status(s, false); 138 } 139 DEFINE_DPU_DEBUGFS_SEQ_FOPS(dpu_debugfs_safe_stats); 140 141 static void dpu_debugfs_danger_init(struct dpu_kms *dpu_kms, 142 struct dentry *parent) 143 { 144 struct dentry *entry = debugfs_create_dir("danger", parent); 145 if (IS_ERR_OR_NULL(entry)) 146 return; 147 148 debugfs_create_file("danger_status", 0600, entry, 149 dpu_kms, &dpu_debugfs_danger_stats_fops); 150 debugfs_create_file("safe_status", 0600, entry, 151 dpu_kms, &dpu_debugfs_safe_stats_fops); 152 } 153 154 static int _dpu_debugfs_show_regset32(struct seq_file *s, void *data) 155 { 156 struct dpu_debugfs_regset32 *regset = s->private; 157 struct dpu_kms *dpu_kms = regset->dpu_kms; 158 struct drm_device *dev; 159 struct msm_drm_private *priv; 160 void __iomem *base; 161 uint32_t i, addr; 162 163 if (!dpu_kms->mmio) 164 return 0; 165 166 dev = dpu_kms->dev; 167 if (!dev) 168 return 0; 169 170 priv = dev->dev_private; 171 if (!priv) 172 return 0; 173 174 base = dpu_kms->mmio + regset->offset; 175 176 /* insert padding spaces, if needed */ 177 if (regset->offset & 0xF) { 178 seq_printf(s, "[%x]", regset->offset & ~0xF); 179 for (i = 0; i < (regset->offset & 0xF); i += 4) 180 seq_puts(s, " "); 181 } 182 183 pm_runtime_get_sync(&dpu_kms->pdev->dev); 184 185 /* main register output */ 186 for (i = 0; i < regset->blk_len; i += 4) { 187 addr = regset->offset + i; 188 if ((addr & 0xF) == 0x0) 189 seq_printf(s, i ? "\n[%x]" : "[%x]", addr); 190 seq_printf(s, " %08x", readl_relaxed(base + i)); 191 } 192 seq_puts(s, "\n"); 193 pm_runtime_put_sync(&dpu_kms->pdev->dev); 194 195 return 0; 196 } 197 198 static int dpu_debugfs_open_regset32(struct inode *inode, 199 struct file *file) 200 { 201 return single_open(file, _dpu_debugfs_show_regset32, inode->i_private); 202 } 203 204 static const struct file_operations dpu_fops_regset32 = { 205 .open = dpu_debugfs_open_regset32, 206 .read = seq_read, 207 .llseek = seq_lseek, 208 .release = single_release, 209 }; 210 211 void dpu_debugfs_setup_regset32(struct dpu_debugfs_regset32 *regset, 212 uint32_t offset, uint32_t length, struct dpu_kms *dpu_kms) 213 { 214 if (regset) { 215 regset->offset = offset; 216 regset->blk_len = length; 217 regset->dpu_kms = dpu_kms; 218 } 219 } 220 221 void *dpu_debugfs_create_regset32(const char *name, umode_t mode, 222 void *parent, struct dpu_debugfs_regset32 *regset) 223 { 224 if (!name || !regset || !regset->dpu_kms || !regset->blk_len) 225 return NULL; 226 227 /* make sure offset is a multiple of 4 */ 228 regset->offset = round_down(regset->offset, 4); 229 230 return debugfs_create_file(name, mode, parent, 231 regset, &dpu_fops_regset32); 232 } 233 234 static int _dpu_debugfs_init(struct dpu_kms *dpu_kms) 235 { 236 void *p = dpu_hw_util_get_log_mask_ptr(); 237 struct dentry *entry; 238 239 if (!p) 240 return -EINVAL; 241 242 entry = debugfs_create_dir("debug", dpu_kms->dev->primary->debugfs_root); 243 if (IS_ERR_OR_NULL(entry)) 244 return -ENODEV; 245 246 /* allow root to be NULL */ 247 debugfs_create_x32(DPU_DEBUGFS_HWMASKNAME, 0600, entry, p); 248 249 dpu_debugfs_danger_init(dpu_kms, entry); 250 dpu_debugfs_vbif_init(dpu_kms, entry); 251 dpu_debugfs_core_irq_init(dpu_kms, entry); 252 253 return dpu_core_perf_debugfs_init(dpu_kms, entry); 254 } 255 #endif 256 257 static int dpu_kms_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc) 258 { 259 return dpu_crtc_vblank(crtc, true); 260 } 261 262 static void dpu_kms_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc) 263 { 264 dpu_crtc_vblank(crtc, false); 265 } 266 267 static void dpu_kms_prepare_commit(struct msm_kms *kms, 268 struct drm_atomic_state *state) 269 { 270 struct dpu_kms *dpu_kms; 271 struct msm_drm_private *priv; 272 struct drm_device *dev; 273 struct drm_crtc *crtc; 274 struct drm_crtc_state *crtc_state; 275 struct drm_encoder *encoder; 276 int i; 277 278 if (!kms) 279 return; 280 dpu_kms = to_dpu_kms(kms); 281 dev = dpu_kms->dev; 282 283 if (!dev || !dev->dev_private) 284 return; 285 priv = dev->dev_private; 286 pm_runtime_get_sync(&dpu_kms->pdev->dev); 287 288 /* Call prepare_commit for all affected encoders */ 289 for_each_new_crtc_in_state(state, crtc, crtc_state, i) { 290 drm_for_each_encoder_mask(encoder, crtc->dev, 291 crtc_state->encoder_mask) { 292 dpu_encoder_prepare_commit(encoder); 293 } 294 } 295 } 296 297 /* 298 * Override the encoder enable since we need to setup the inline rotator and do 299 * some crtc magic before enabling any bridge that might be present. 300 */ 301 void dpu_kms_encoder_enable(struct drm_encoder *encoder) 302 { 303 const struct drm_encoder_helper_funcs *funcs = encoder->helper_private; 304 struct drm_device *dev = encoder->dev; 305 struct drm_crtc *crtc; 306 307 /* Forward this enable call to the commit hook */ 308 if (funcs && funcs->commit) 309 funcs->commit(encoder); 310 311 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); 312 drm_for_each_crtc(crtc, dev) { 313 if (!(crtc->state->encoder_mask & drm_encoder_mask(encoder))) 314 continue; 315 316 trace_dpu_kms_enc_enable(DRMID(crtc)); 317 dpu_crtc_commit_kickoff(crtc, false); 318 } 319 } 320 321 static void dpu_kms_commit(struct msm_kms *kms, struct drm_atomic_state *state) 322 { 323 struct drm_crtc *crtc; 324 struct drm_crtc_state *crtc_state; 325 int i; 326 327 for_each_new_crtc_in_state(state, crtc, crtc_state, i) { 328 /* If modeset is required, kickoff is run in encoder_enable */ 329 if (drm_atomic_crtc_needs_modeset(crtc_state)) 330 continue; 331 332 if (crtc->state->active) { 333 trace_dpu_kms_commit(DRMID(crtc)); 334 dpu_crtc_commit_kickoff(crtc, 335 state->legacy_cursor_update); 336 } 337 } 338 } 339 340 static void dpu_kms_complete_commit(struct msm_kms *kms, 341 struct drm_atomic_state *old_state) 342 { 343 struct dpu_kms *dpu_kms; 344 struct msm_drm_private *priv; 345 struct drm_crtc *crtc; 346 struct drm_crtc_state *old_crtc_state; 347 int i; 348 349 if (!kms || !old_state) 350 return; 351 dpu_kms = to_dpu_kms(kms); 352 353 if (!dpu_kms->dev || !dpu_kms->dev->dev_private) 354 return; 355 priv = dpu_kms->dev->dev_private; 356 357 DPU_ATRACE_BEGIN("kms_complete_commit"); 358 359 for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) 360 dpu_crtc_complete_commit(crtc, old_crtc_state); 361 362 pm_runtime_put_sync(&dpu_kms->pdev->dev); 363 364 DPU_ATRACE_END("kms_complete_commit"); 365 } 366 367 static void dpu_kms_wait_for_commit_done(struct msm_kms *kms, 368 struct drm_crtc *crtc) 369 { 370 struct drm_encoder *encoder; 371 struct drm_device *dev; 372 int ret; 373 374 if (!kms || !crtc || !crtc->state) { 375 DPU_ERROR("invalid params\n"); 376 return; 377 } 378 379 dev = crtc->dev; 380 381 if (!crtc->state->enable) { 382 DPU_DEBUG("[crtc:%d] not enable\n", crtc->base.id); 383 return; 384 } 385 386 if (!crtc->state->active) { 387 DPU_DEBUG("[crtc:%d] not active\n", crtc->base.id); 388 return; 389 } 390 391 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 392 if (encoder->crtc != crtc) 393 continue; 394 /* 395 * Wait for post-flush if necessary to delay before 396 * plane_cleanup. For example, wait for vsync in case of video 397 * mode panels. This may be a no-op for command mode panels. 398 */ 399 trace_dpu_kms_wait_for_commit_done(DRMID(crtc)); 400 ret = dpu_encoder_wait_for_event(encoder, MSM_ENC_COMMIT_DONE); 401 if (ret && ret != -EWOULDBLOCK) { 402 DPU_ERROR("wait for commit done returned %d\n", ret); 403 break; 404 } 405 } 406 } 407 408 static int _dpu_kms_initialize_dsi(struct drm_device *dev, 409 struct msm_drm_private *priv, 410 struct dpu_kms *dpu_kms) 411 { 412 struct drm_encoder *encoder = NULL; 413 int i, rc = 0; 414 415 if (!(priv->dsi[0] || priv->dsi[1])) 416 return rc; 417 418 /*TODO: Support two independent DSI connectors */ 419 encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_DSI); 420 if (IS_ERR(encoder)) { 421 DPU_ERROR("encoder init failed for dsi display\n"); 422 return PTR_ERR(encoder); 423 } 424 425 priv->encoders[priv->num_encoders++] = encoder; 426 427 for (i = 0; i < ARRAY_SIZE(priv->dsi); i++) { 428 if (!priv->dsi[i]) 429 continue; 430 431 rc = msm_dsi_modeset_init(priv->dsi[i], dev, encoder); 432 if (rc) { 433 DPU_ERROR("modeset_init failed for dsi[%d], rc = %d\n", 434 i, rc); 435 break; 436 } 437 } 438 439 return rc; 440 } 441 442 /** 443 * _dpu_kms_setup_displays - create encoders, bridges and connectors 444 * for underlying displays 445 * @dev: Pointer to drm device structure 446 * @priv: Pointer to private drm device data 447 * @dpu_kms: Pointer to dpu kms structure 448 * Returns: Zero on success 449 */ 450 static int _dpu_kms_setup_displays(struct drm_device *dev, 451 struct msm_drm_private *priv, 452 struct dpu_kms *dpu_kms) 453 { 454 /** 455 * Extend this function to initialize other 456 * types of displays 457 */ 458 459 return _dpu_kms_initialize_dsi(dev, priv, dpu_kms); 460 } 461 462 static void _dpu_kms_drm_obj_destroy(struct dpu_kms *dpu_kms) 463 { 464 struct msm_drm_private *priv; 465 int i; 466 467 if (!dpu_kms) { 468 DPU_ERROR("invalid dpu_kms\n"); 469 return; 470 } else if (!dpu_kms->dev) { 471 DPU_ERROR("invalid dev\n"); 472 return; 473 } else if (!dpu_kms->dev->dev_private) { 474 DPU_ERROR("invalid dev_private\n"); 475 return; 476 } 477 priv = dpu_kms->dev->dev_private; 478 479 for (i = 0; i < priv->num_crtcs; i++) 480 priv->crtcs[i]->funcs->destroy(priv->crtcs[i]); 481 priv->num_crtcs = 0; 482 483 for (i = 0; i < priv->num_planes; i++) 484 priv->planes[i]->funcs->destroy(priv->planes[i]); 485 priv->num_planes = 0; 486 487 for (i = 0; i < priv->num_connectors; i++) 488 priv->connectors[i]->funcs->destroy(priv->connectors[i]); 489 priv->num_connectors = 0; 490 491 for (i = 0; i < priv->num_encoders; i++) 492 priv->encoders[i]->funcs->destroy(priv->encoders[i]); 493 priv->num_encoders = 0; 494 } 495 496 static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms) 497 { 498 struct drm_device *dev; 499 struct drm_plane *primary_planes[MAX_PLANES], *plane; 500 struct drm_plane *cursor_planes[MAX_PLANES] = { NULL }; 501 struct drm_crtc *crtc; 502 503 struct msm_drm_private *priv; 504 struct dpu_mdss_cfg *catalog; 505 506 int primary_planes_idx = 0, cursor_planes_idx = 0, i, ret; 507 int max_crtc_count; 508 509 if (!dpu_kms || !dpu_kms->dev || !dpu_kms->dev->dev) { 510 DPU_ERROR("invalid dpu_kms\n"); 511 return -EINVAL; 512 } 513 514 dev = dpu_kms->dev; 515 priv = dev->dev_private; 516 catalog = dpu_kms->catalog; 517 518 /* 519 * Create encoder and query display drivers to create 520 * bridges and connectors 521 */ 522 ret = _dpu_kms_setup_displays(dev, priv, dpu_kms); 523 if (ret) 524 goto fail; 525 526 max_crtc_count = min(catalog->mixer_count, priv->num_encoders); 527 528 /* Create the planes, keeping track of one primary/cursor per crtc */ 529 for (i = 0; i < catalog->sspp_count; i++) { 530 enum drm_plane_type type; 531 532 if ((catalog->sspp[i].features & BIT(DPU_SSPP_CURSOR)) 533 && cursor_planes_idx < max_crtc_count) 534 type = DRM_PLANE_TYPE_CURSOR; 535 else if (primary_planes_idx < max_crtc_count) 536 type = DRM_PLANE_TYPE_PRIMARY; 537 else 538 type = DRM_PLANE_TYPE_OVERLAY; 539 540 DPU_DEBUG("Create plane type %d with features %lx (cur %lx)\n", 541 type, catalog->sspp[i].features, 542 catalog->sspp[i].features & BIT(DPU_SSPP_CURSOR)); 543 544 plane = dpu_plane_init(dev, catalog->sspp[i].id, type, 545 (1UL << max_crtc_count) - 1, 0); 546 if (IS_ERR(plane)) { 547 DPU_ERROR("dpu_plane_init failed\n"); 548 ret = PTR_ERR(plane); 549 goto fail; 550 } 551 priv->planes[priv->num_planes++] = plane; 552 553 if (type == DRM_PLANE_TYPE_CURSOR) 554 cursor_planes[cursor_planes_idx++] = plane; 555 else if (type == DRM_PLANE_TYPE_PRIMARY) 556 primary_planes[primary_planes_idx++] = plane; 557 } 558 559 max_crtc_count = min(max_crtc_count, primary_planes_idx); 560 561 /* Create one CRTC per encoder */ 562 for (i = 0; i < max_crtc_count; i++) { 563 crtc = dpu_crtc_init(dev, primary_planes[i], cursor_planes[i]); 564 if (IS_ERR(crtc)) { 565 ret = PTR_ERR(crtc); 566 goto fail; 567 } 568 priv->crtcs[priv->num_crtcs++] = crtc; 569 } 570 571 /* All CRTCs are compatible with all encoders */ 572 for (i = 0; i < priv->num_encoders; i++) 573 priv->encoders[i]->possible_crtcs = (1 << priv->num_crtcs) - 1; 574 575 return 0; 576 fail: 577 _dpu_kms_drm_obj_destroy(dpu_kms); 578 return ret; 579 } 580 581 #ifdef CONFIG_DEBUG_FS 582 static int dpu_kms_debugfs_init(struct msm_kms *kms, struct drm_minor *minor) 583 { 584 return _dpu_debugfs_init(to_dpu_kms(kms)); 585 } 586 #endif 587 588 static long dpu_kms_round_pixclk(struct msm_kms *kms, unsigned long rate, 589 struct drm_encoder *encoder) 590 { 591 return rate; 592 } 593 594 static void _dpu_kms_hw_destroy(struct dpu_kms *dpu_kms) 595 { 596 struct drm_device *dev; 597 int i; 598 599 dev = dpu_kms->dev; 600 if (!dev) 601 return; 602 603 if (dpu_kms->hw_intr) 604 dpu_hw_intr_destroy(dpu_kms->hw_intr); 605 dpu_kms->hw_intr = NULL; 606 607 /* safe to call these more than once during shutdown */ 608 _dpu_kms_mmu_destroy(dpu_kms); 609 610 if (dpu_kms->catalog) { 611 for (i = 0; i < dpu_kms->catalog->vbif_count; i++) { 612 u32 vbif_idx = dpu_kms->catalog->vbif[i].id; 613 614 if ((vbif_idx < VBIF_MAX) && dpu_kms->hw_vbif[vbif_idx]) 615 dpu_hw_vbif_destroy(dpu_kms->hw_vbif[vbif_idx]); 616 } 617 } 618 619 if (dpu_kms->rm_init) 620 dpu_rm_destroy(&dpu_kms->rm); 621 dpu_kms->rm_init = false; 622 623 if (dpu_kms->catalog) 624 dpu_hw_catalog_deinit(dpu_kms->catalog); 625 dpu_kms->catalog = NULL; 626 627 if (dpu_kms->vbif[VBIF_NRT]) 628 devm_iounmap(&dpu_kms->pdev->dev, dpu_kms->vbif[VBIF_NRT]); 629 dpu_kms->vbif[VBIF_NRT] = NULL; 630 631 if (dpu_kms->vbif[VBIF_RT]) 632 devm_iounmap(&dpu_kms->pdev->dev, dpu_kms->vbif[VBIF_RT]); 633 dpu_kms->vbif[VBIF_RT] = NULL; 634 635 if (dpu_kms->hw_mdp) 636 dpu_hw_mdp_destroy(dpu_kms->hw_mdp); 637 dpu_kms->hw_mdp = NULL; 638 639 if (dpu_kms->mmio) 640 devm_iounmap(&dpu_kms->pdev->dev, dpu_kms->mmio); 641 dpu_kms->mmio = NULL; 642 } 643 644 static void dpu_kms_destroy(struct msm_kms *kms) 645 { 646 struct dpu_kms *dpu_kms; 647 648 if (!kms) { 649 DPU_ERROR("invalid kms\n"); 650 return; 651 } 652 653 dpu_kms = to_dpu_kms(kms); 654 655 _dpu_kms_hw_destroy(dpu_kms); 656 } 657 658 static void _dpu_kms_set_encoder_mode(struct msm_kms *kms, 659 struct drm_encoder *encoder, 660 bool cmd_mode) 661 { 662 struct msm_display_info info; 663 struct msm_drm_private *priv = encoder->dev->dev_private; 664 int i, rc = 0; 665 666 memset(&info, 0, sizeof(info)); 667 668 info.intf_type = encoder->encoder_type; 669 info.capabilities = cmd_mode ? MSM_DISPLAY_CAP_CMD_MODE : 670 MSM_DISPLAY_CAP_VID_MODE; 671 672 /* TODO: No support for DSI swap */ 673 for (i = 0; i < ARRAY_SIZE(priv->dsi); i++) { 674 if (priv->dsi[i]) { 675 info.h_tile_instance[info.num_of_h_tiles] = i; 676 info.num_of_h_tiles++; 677 } 678 } 679 680 rc = dpu_encoder_setup(encoder->dev, encoder, &info); 681 if (rc) 682 DPU_ERROR("failed to setup DPU encoder %d: rc:%d\n", 683 encoder->base.id, rc); 684 } 685 686 static irqreturn_t dpu_irq(struct msm_kms *kms) 687 { 688 struct dpu_kms *dpu_kms = to_dpu_kms(kms); 689 690 return dpu_core_irq(dpu_kms); 691 } 692 693 static void dpu_irq_preinstall(struct msm_kms *kms) 694 { 695 struct dpu_kms *dpu_kms = to_dpu_kms(kms); 696 697 dpu_core_irq_preinstall(dpu_kms); 698 } 699 700 static void dpu_irq_uninstall(struct msm_kms *kms) 701 { 702 struct dpu_kms *dpu_kms = to_dpu_kms(kms); 703 704 dpu_core_irq_uninstall(dpu_kms); 705 } 706 707 static const struct msm_kms_funcs kms_funcs = { 708 .hw_init = dpu_kms_hw_init, 709 .irq_preinstall = dpu_irq_preinstall, 710 .irq_uninstall = dpu_irq_uninstall, 711 .irq = dpu_irq, 712 .prepare_commit = dpu_kms_prepare_commit, 713 .commit = dpu_kms_commit, 714 .complete_commit = dpu_kms_complete_commit, 715 .wait_for_crtc_commit_done = dpu_kms_wait_for_commit_done, 716 .enable_vblank = dpu_kms_enable_vblank, 717 .disable_vblank = dpu_kms_disable_vblank, 718 .check_modified_format = dpu_format_check_modified_format, 719 .get_format = dpu_get_msm_format, 720 .round_pixclk = dpu_kms_round_pixclk, 721 .destroy = dpu_kms_destroy, 722 .set_encoder_mode = _dpu_kms_set_encoder_mode, 723 #ifdef CONFIG_DEBUG_FS 724 .debugfs_init = dpu_kms_debugfs_init, 725 #endif 726 }; 727 728 static int _dpu_kms_mmu_destroy(struct dpu_kms *dpu_kms) 729 { 730 struct msm_mmu *mmu; 731 732 mmu = dpu_kms->base.aspace->mmu; 733 734 mmu->funcs->detach(mmu, (const char **)iommu_ports, 735 ARRAY_SIZE(iommu_ports)); 736 msm_gem_address_space_put(dpu_kms->base.aspace); 737 738 return 0; 739 } 740 741 static int _dpu_kms_mmu_init(struct dpu_kms *dpu_kms) 742 { 743 struct iommu_domain *domain; 744 struct msm_gem_address_space *aspace; 745 int ret; 746 747 domain = iommu_domain_alloc(&platform_bus_type); 748 if (!domain) 749 return 0; 750 751 domain->geometry.aperture_start = 0x1000; 752 domain->geometry.aperture_end = 0xffffffff; 753 754 aspace = msm_gem_address_space_create(dpu_kms->dev->dev, 755 domain, "dpu1"); 756 if (IS_ERR(aspace)) { 757 ret = PTR_ERR(aspace); 758 goto fail; 759 } 760 761 dpu_kms->base.aspace = aspace; 762 763 ret = aspace->mmu->funcs->attach(aspace->mmu, iommu_ports, 764 ARRAY_SIZE(iommu_ports)); 765 if (ret) { 766 DPU_ERROR("failed to attach iommu %d\n", ret); 767 msm_gem_address_space_put(aspace); 768 goto fail; 769 } 770 771 return 0; 772 fail: 773 _dpu_kms_mmu_destroy(dpu_kms); 774 775 return ret; 776 } 777 778 static struct dss_clk *_dpu_kms_get_clk(struct dpu_kms *dpu_kms, 779 char *clock_name) 780 { 781 struct dss_module_power *mp = &dpu_kms->mp; 782 int i; 783 784 for (i = 0; i < mp->num_clk; i++) { 785 if (!strcmp(mp->clk_config[i].clk_name, clock_name)) 786 return &mp->clk_config[i]; 787 } 788 789 return NULL; 790 } 791 792 u64 dpu_kms_get_clk_rate(struct dpu_kms *dpu_kms, char *clock_name) 793 { 794 struct dss_clk *clk; 795 796 clk = _dpu_kms_get_clk(dpu_kms, clock_name); 797 if (!clk) 798 return -EINVAL; 799 800 return clk_get_rate(clk->clk); 801 } 802 803 static int dpu_kms_hw_init(struct msm_kms *kms) 804 { 805 struct dpu_kms *dpu_kms; 806 struct drm_device *dev; 807 struct msm_drm_private *priv; 808 int i, rc = -EINVAL; 809 810 if (!kms) { 811 DPU_ERROR("invalid kms\n"); 812 return rc; 813 } 814 815 dpu_kms = to_dpu_kms(kms); 816 dev = dpu_kms->dev; 817 if (!dev) { 818 DPU_ERROR("invalid device\n"); 819 return rc; 820 } 821 822 priv = dev->dev_private; 823 if (!priv) { 824 DPU_ERROR("invalid private data\n"); 825 return rc; 826 } 827 828 dpu_kms->mmio = msm_ioremap(dpu_kms->pdev, "mdp", "mdp"); 829 if (IS_ERR(dpu_kms->mmio)) { 830 rc = PTR_ERR(dpu_kms->mmio); 831 DPU_ERROR("mdp register memory map failed: %d\n", rc); 832 dpu_kms->mmio = NULL; 833 goto error; 834 } 835 DRM_DEBUG("mapped dpu address space @%pK\n", dpu_kms->mmio); 836 dpu_kms->mmio_len = dpu_iomap_size(dpu_kms->pdev, "mdp"); 837 838 dpu_kms->vbif[VBIF_RT] = msm_ioremap(dpu_kms->pdev, "vbif", "vbif"); 839 if (IS_ERR(dpu_kms->vbif[VBIF_RT])) { 840 rc = PTR_ERR(dpu_kms->vbif[VBIF_RT]); 841 DPU_ERROR("vbif register memory map failed: %d\n", rc); 842 dpu_kms->vbif[VBIF_RT] = NULL; 843 goto error; 844 } 845 dpu_kms->vbif_len[VBIF_RT] = dpu_iomap_size(dpu_kms->pdev, "vbif"); 846 dpu_kms->vbif[VBIF_NRT] = msm_ioremap(dpu_kms->pdev, "vbif_nrt", "vbif_nrt"); 847 if (IS_ERR(dpu_kms->vbif[VBIF_NRT])) { 848 dpu_kms->vbif[VBIF_NRT] = NULL; 849 DPU_DEBUG("VBIF NRT is not defined"); 850 } else { 851 dpu_kms->vbif_len[VBIF_NRT] = dpu_iomap_size(dpu_kms->pdev, 852 "vbif_nrt"); 853 } 854 855 dpu_kms->reg_dma = msm_ioremap(dpu_kms->pdev, "regdma", "regdma"); 856 if (IS_ERR(dpu_kms->reg_dma)) { 857 dpu_kms->reg_dma = NULL; 858 DPU_DEBUG("REG_DMA is not defined"); 859 } else { 860 dpu_kms->reg_dma_len = dpu_iomap_size(dpu_kms->pdev, "regdma"); 861 } 862 863 pm_runtime_get_sync(&dpu_kms->pdev->dev); 864 865 dpu_kms->core_rev = readl_relaxed(dpu_kms->mmio + 0x0); 866 867 pr_info("dpu hardware revision:0x%x\n", dpu_kms->core_rev); 868 869 dpu_kms->catalog = dpu_hw_catalog_init(dpu_kms->core_rev); 870 if (IS_ERR_OR_NULL(dpu_kms->catalog)) { 871 rc = PTR_ERR(dpu_kms->catalog); 872 if (!dpu_kms->catalog) 873 rc = -EINVAL; 874 DPU_ERROR("catalog init failed: %d\n", rc); 875 dpu_kms->catalog = NULL; 876 goto power_error; 877 } 878 879 /* 880 * Now we need to read the HW catalog and initialize resources such as 881 * clocks, regulators, GDSC/MMAGIC, ioremap the register ranges etc 882 */ 883 rc = _dpu_kms_mmu_init(dpu_kms); 884 if (rc) { 885 DPU_ERROR("dpu_kms_mmu_init failed: %d\n", rc); 886 goto power_error; 887 } 888 889 rc = dpu_rm_init(&dpu_kms->rm, dpu_kms->catalog, dpu_kms->mmio); 890 if (rc) { 891 DPU_ERROR("rm init failed: %d\n", rc); 892 goto power_error; 893 } 894 895 dpu_kms->rm_init = true; 896 897 dpu_kms->hw_mdp = dpu_hw_mdptop_init(MDP_TOP, dpu_kms->mmio, 898 dpu_kms->catalog); 899 if (IS_ERR(dpu_kms->hw_mdp)) { 900 rc = PTR_ERR(dpu_kms->hw_mdp); 901 DPU_ERROR("failed to get hw_mdp: %d\n", rc); 902 dpu_kms->hw_mdp = NULL; 903 goto power_error; 904 } 905 906 for (i = 0; i < dpu_kms->catalog->vbif_count; i++) { 907 u32 vbif_idx = dpu_kms->catalog->vbif[i].id; 908 909 dpu_kms->hw_vbif[i] = dpu_hw_vbif_init(vbif_idx, 910 dpu_kms->vbif[vbif_idx], dpu_kms->catalog); 911 if (IS_ERR_OR_NULL(dpu_kms->hw_vbif[vbif_idx])) { 912 rc = PTR_ERR(dpu_kms->hw_vbif[vbif_idx]); 913 if (!dpu_kms->hw_vbif[vbif_idx]) 914 rc = -EINVAL; 915 DPU_ERROR("failed to init vbif %d: %d\n", vbif_idx, rc); 916 dpu_kms->hw_vbif[vbif_idx] = NULL; 917 goto power_error; 918 } 919 } 920 921 rc = dpu_core_perf_init(&dpu_kms->perf, dev, dpu_kms->catalog, 922 _dpu_kms_get_clk(dpu_kms, "core")); 923 if (rc) { 924 DPU_ERROR("failed to init perf %d\n", rc); 925 goto perf_err; 926 } 927 928 dpu_kms->hw_intr = dpu_hw_intr_init(dpu_kms->mmio, dpu_kms->catalog); 929 if (IS_ERR_OR_NULL(dpu_kms->hw_intr)) { 930 rc = PTR_ERR(dpu_kms->hw_intr); 931 DPU_ERROR("hw_intr init failed: %d\n", rc); 932 dpu_kms->hw_intr = NULL; 933 goto hw_intr_init_err; 934 } 935 936 dev->mode_config.min_width = 0; 937 dev->mode_config.min_height = 0; 938 939 /* 940 * max crtc width is equal to the max mixer width * 2 and max height is 941 * is 4K 942 */ 943 dev->mode_config.max_width = 944 dpu_kms->catalog->caps->max_mixer_width * 2; 945 dev->mode_config.max_height = 4096; 946 947 /* 948 * Support format modifiers for compression etc. 949 */ 950 dev->mode_config.allow_fb_modifiers = true; 951 952 /* 953 * _dpu_kms_drm_obj_init should create the DRM related objects 954 * i.e. CRTCs, planes, encoders, connectors and so forth 955 */ 956 rc = _dpu_kms_drm_obj_init(dpu_kms); 957 if (rc) { 958 DPU_ERROR("modeset init failed: %d\n", rc); 959 goto drm_obj_init_err; 960 } 961 962 dpu_vbif_init_memtypes(dpu_kms); 963 964 pm_runtime_put_sync(&dpu_kms->pdev->dev); 965 966 return 0; 967 968 drm_obj_init_err: 969 dpu_core_perf_destroy(&dpu_kms->perf); 970 hw_intr_init_err: 971 perf_err: 972 power_error: 973 pm_runtime_put_sync(&dpu_kms->pdev->dev); 974 error: 975 _dpu_kms_hw_destroy(dpu_kms); 976 977 return rc; 978 } 979 980 struct msm_kms *dpu_kms_init(struct drm_device *dev) 981 { 982 struct msm_drm_private *priv; 983 struct dpu_kms *dpu_kms; 984 int irq; 985 986 if (!dev || !dev->dev_private) { 987 DPU_ERROR("drm device node invalid\n"); 988 return ERR_PTR(-EINVAL); 989 } 990 991 priv = dev->dev_private; 992 dpu_kms = to_dpu_kms(priv->kms); 993 994 irq = irq_of_parse_and_map(dpu_kms->pdev->dev.of_node, 0); 995 if (irq < 0) { 996 DPU_ERROR("failed to get irq: %d\n", irq); 997 return ERR_PTR(irq); 998 } 999 dpu_kms->base.irq = irq; 1000 1001 return &dpu_kms->base; 1002 } 1003 1004 static int dpu_bind(struct device *dev, struct device *master, void *data) 1005 { 1006 struct drm_device *ddev = dev_get_drvdata(master); 1007 struct platform_device *pdev = to_platform_device(dev); 1008 struct msm_drm_private *priv = ddev->dev_private; 1009 struct dpu_kms *dpu_kms; 1010 struct dss_module_power *mp; 1011 int ret = 0; 1012 1013 dpu_kms = devm_kzalloc(&pdev->dev, sizeof(*dpu_kms), GFP_KERNEL); 1014 if (!dpu_kms) 1015 return -ENOMEM; 1016 1017 mp = &dpu_kms->mp; 1018 ret = msm_dss_parse_clock(pdev, mp); 1019 if (ret) { 1020 DPU_ERROR("failed to parse clocks, ret=%d\n", ret); 1021 return ret; 1022 } 1023 1024 platform_set_drvdata(pdev, dpu_kms); 1025 1026 msm_kms_init(&dpu_kms->base, &kms_funcs); 1027 dpu_kms->dev = ddev; 1028 dpu_kms->pdev = pdev; 1029 1030 pm_runtime_enable(&pdev->dev); 1031 dpu_kms->rpm_enabled = true; 1032 1033 priv->kms = &dpu_kms->base; 1034 return ret; 1035 } 1036 1037 static void dpu_unbind(struct device *dev, struct device *master, void *data) 1038 { 1039 struct platform_device *pdev = to_platform_device(dev); 1040 struct dpu_kms *dpu_kms = platform_get_drvdata(pdev); 1041 struct dss_module_power *mp = &dpu_kms->mp; 1042 1043 msm_dss_put_clk(mp->clk_config, mp->num_clk); 1044 devm_kfree(&pdev->dev, mp->clk_config); 1045 mp->num_clk = 0; 1046 1047 if (dpu_kms->rpm_enabled) 1048 pm_runtime_disable(&pdev->dev); 1049 } 1050 1051 static const struct component_ops dpu_ops = { 1052 .bind = dpu_bind, 1053 .unbind = dpu_unbind, 1054 }; 1055 1056 static int dpu_dev_probe(struct platform_device *pdev) 1057 { 1058 return component_add(&pdev->dev, &dpu_ops); 1059 } 1060 1061 static int dpu_dev_remove(struct platform_device *pdev) 1062 { 1063 component_del(&pdev->dev, &dpu_ops); 1064 return 0; 1065 } 1066 1067 static int __maybe_unused dpu_runtime_suspend(struct device *dev) 1068 { 1069 int rc = -1; 1070 struct platform_device *pdev = to_platform_device(dev); 1071 struct dpu_kms *dpu_kms = platform_get_drvdata(pdev); 1072 struct drm_device *ddev; 1073 struct dss_module_power *mp = &dpu_kms->mp; 1074 1075 ddev = dpu_kms->dev; 1076 if (!ddev) { 1077 DPU_ERROR("invalid drm_device\n"); 1078 return rc; 1079 } 1080 1081 rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, false); 1082 if (rc) 1083 DPU_ERROR("clock disable failed rc:%d\n", rc); 1084 1085 return rc; 1086 } 1087 1088 static int __maybe_unused dpu_runtime_resume(struct device *dev) 1089 { 1090 int rc = -1; 1091 struct platform_device *pdev = to_platform_device(dev); 1092 struct dpu_kms *dpu_kms = platform_get_drvdata(pdev); 1093 struct drm_encoder *encoder; 1094 struct drm_device *ddev; 1095 struct dss_module_power *mp = &dpu_kms->mp; 1096 1097 ddev = dpu_kms->dev; 1098 if (!ddev) { 1099 DPU_ERROR("invalid drm_device\n"); 1100 return rc; 1101 } 1102 1103 rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, true); 1104 if (rc) { 1105 DPU_ERROR("clock enable failed rc:%d\n", rc); 1106 return rc; 1107 } 1108 1109 dpu_vbif_init_memtypes(dpu_kms); 1110 1111 drm_for_each_encoder(encoder, ddev) 1112 dpu_encoder_virt_runtime_resume(encoder); 1113 1114 return rc; 1115 } 1116 1117 static const struct dev_pm_ops dpu_pm_ops = { 1118 SET_RUNTIME_PM_OPS(dpu_runtime_suspend, dpu_runtime_resume, NULL) 1119 }; 1120 1121 static const struct of_device_id dpu_dt_match[] = { 1122 { .compatible = "qcom,sdm845-dpu", }, 1123 {} 1124 }; 1125 MODULE_DEVICE_TABLE(of, dpu_dt_match); 1126 1127 static struct platform_driver dpu_driver = { 1128 .probe = dpu_dev_probe, 1129 .remove = dpu_dev_remove, 1130 .driver = { 1131 .name = "msm_dpu", 1132 .of_match_table = dpu_dt_match, 1133 .pm = &dpu_pm_ops, 1134 }, 1135 }; 1136 1137 void __init msm_dpu_register(void) 1138 { 1139 platform_driver_register(&dpu_driver); 1140 } 1141 1142 void __exit msm_dpu_unregister(void) 1143 { 1144 platform_driver_unregister(&dpu_driver); 1145 } 1146