1 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 2 * 3 * This program is free software; you can redistribute it and/or modify 4 * it under the terms of the GNU General Public License version 2 and 5 * only version 2 as published by the Free Software Foundation. 6 * 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 */ 12 13 #ifndef _DPU_HW_UTIL_H 14 #define _DPU_HW_UTIL_H 15 16 #include <linux/io.h> 17 #include <linux/slab.h> 18 #include "dpu_hw_mdss.h" 19 20 #define REG_MASK(n) ((BIT(n)) - 1) 21 struct dpu_format_extended; 22 23 /* 24 * This is the common struct maintained by each sub block 25 * for mapping the register offsets in this block to the 26 * absoulute IO address 27 * @base_off: mdp register mapped offset 28 * @blk_off: pipe offset relative to mdss offset 29 * @length length of register block offset 30 * @xin_id xin id 31 * @hwversion mdss hw version number 32 */ 33 struct dpu_hw_blk_reg_map { 34 void __iomem *base_off; 35 u32 blk_off; 36 u32 length; 37 u32 xin_id; 38 u32 hwversion; 39 u32 log_mask; 40 }; 41 42 /** 43 * struct dpu_hw_scaler3_de_cfg : QSEEDv3 detail enhancer configuration 44 * @enable: detail enhancer enable/disable 45 * @sharpen_level1: sharpening strength for noise 46 * @sharpen_level2: sharpening strength for signal 47 * @ clip: clip shift 48 * @ limit: limit value 49 * @ thr_quiet: quiet threshold 50 * @ thr_dieout: dieout threshold 51 * @ thr_high: low threshold 52 * @ thr_high: high threshold 53 * @ prec_shift: precision shift 54 * @ adjust_a: A-coefficients for mapping curve 55 * @ adjust_b: B-coefficients for mapping curve 56 * @ adjust_c: C-coefficients for mapping curve 57 */ 58 struct dpu_hw_scaler3_de_cfg { 59 u32 enable; 60 int16_t sharpen_level1; 61 int16_t sharpen_level2; 62 uint16_t clip; 63 uint16_t limit; 64 uint16_t thr_quiet; 65 uint16_t thr_dieout; 66 uint16_t thr_low; 67 uint16_t thr_high; 68 uint16_t prec_shift; 69 int16_t adjust_a[DPU_MAX_DE_CURVES]; 70 int16_t adjust_b[DPU_MAX_DE_CURVES]; 71 int16_t adjust_c[DPU_MAX_DE_CURVES]; 72 }; 73 74 75 /** 76 * struct dpu_hw_scaler3_cfg : QSEEDv3 configuration 77 * @enable: scaler enable 78 * @dir_en: direction detection block enable 79 * @ init_phase_x: horizontal initial phase 80 * @ phase_step_x: horizontal phase step 81 * @ init_phase_y: vertical initial phase 82 * @ phase_step_y: vertical phase step 83 * @ preload_x: horizontal preload value 84 * @ preload_y: vertical preload value 85 * @ src_width: source width 86 * @ src_height: source height 87 * @ dst_width: destination width 88 * @ dst_height: destination height 89 * @ y_rgb_filter_cfg: y/rgb plane filter configuration 90 * @ uv_filter_cfg: uv plane filter configuration 91 * @ alpha_filter_cfg: alpha filter configuration 92 * @ blend_cfg: blend coefficients configuration 93 * @ lut_flag: scaler LUT update flags 94 * 0x1 swap LUT bank 95 * 0x2 update 2D filter LUT 96 * 0x4 update y circular filter LUT 97 * 0x8 update uv circular filter LUT 98 * 0x10 update y separable filter LUT 99 * 0x20 update uv separable filter LUT 100 * @ dir_lut_idx: 2D filter LUT index 101 * @ y_rgb_cir_lut_idx: y circular filter LUT index 102 * @ uv_cir_lut_idx: uv circular filter LUT index 103 * @ y_rgb_sep_lut_idx: y circular filter LUT index 104 * @ uv_sep_lut_idx: uv separable filter LUT index 105 * @ dir_lut: pointer to 2D LUT 106 * @ cir_lut: pointer to circular filter LUT 107 * @ sep_lut: pointer to separable filter LUT 108 * @ de: detail enhancer configuration 109 */ 110 struct dpu_hw_scaler3_cfg { 111 u32 enable; 112 u32 dir_en; 113 int32_t init_phase_x[DPU_MAX_PLANES]; 114 int32_t phase_step_x[DPU_MAX_PLANES]; 115 int32_t init_phase_y[DPU_MAX_PLANES]; 116 int32_t phase_step_y[DPU_MAX_PLANES]; 117 118 u32 preload_x[DPU_MAX_PLANES]; 119 u32 preload_y[DPU_MAX_PLANES]; 120 u32 src_width[DPU_MAX_PLANES]; 121 u32 src_height[DPU_MAX_PLANES]; 122 123 u32 dst_width; 124 u32 dst_height; 125 126 u32 y_rgb_filter_cfg; 127 u32 uv_filter_cfg; 128 u32 alpha_filter_cfg; 129 u32 blend_cfg; 130 131 u32 lut_flag; 132 u32 dir_lut_idx; 133 134 u32 y_rgb_cir_lut_idx; 135 u32 uv_cir_lut_idx; 136 u32 y_rgb_sep_lut_idx; 137 u32 uv_sep_lut_idx; 138 u32 *dir_lut; 139 size_t dir_len; 140 u32 *cir_lut; 141 size_t cir_len; 142 u32 *sep_lut; 143 size_t sep_len; 144 145 /* 146 * Detail enhancer settings 147 */ 148 struct dpu_hw_scaler3_de_cfg de; 149 }; 150 151 /** 152 * struct dpu_drm_pix_ext_v1 - version 1 of pixel ext structure 153 * @num_ext_pxls_lr: Number of total horizontal pixels 154 * @num_ext_pxls_tb: Number of total vertical lines 155 * @left_ftch: Number of extra pixels to overfetch from left 156 * @right_ftch: Number of extra pixels to overfetch from right 157 * @top_ftch: Number of extra lines to overfetch from top 158 * @btm_ftch: Number of extra lines to overfetch from bottom 159 * @left_rpt: Number of extra pixels to repeat from left 160 * @right_rpt: Number of extra pixels to repeat from right 161 * @top_rpt: Number of extra lines to repeat from top 162 * @btm_rpt: Number of extra lines to repeat from bottom 163 */ 164 struct dpu_drm_pix_ext_v1 { 165 /* 166 * Number of pixels ext in left, right, top and bottom direction 167 * for all color components. 168 */ 169 int32_t num_ext_pxls_lr[DPU_MAX_PLANES]; 170 int32_t num_ext_pxls_tb[DPU_MAX_PLANES]; 171 172 /* 173 * Number of pixels needs to be overfetched in left, right, top 174 * and bottom directions from source image for scaling. 175 */ 176 int32_t left_ftch[DPU_MAX_PLANES]; 177 int32_t right_ftch[DPU_MAX_PLANES]; 178 int32_t top_ftch[DPU_MAX_PLANES]; 179 int32_t btm_ftch[DPU_MAX_PLANES]; 180 /* 181 * Number of pixels needs to be repeated in left, right, top and 182 * bottom directions for scaling. 183 */ 184 int32_t left_rpt[DPU_MAX_PLANES]; 185 int32_t right_rpt[DPU_MAX_PLANES]; 186 int32_t top_rpt[DPU_MAX_PLANES]; 187 int32_t btm_rpt[DPU_MAX_PLANES]; 188 189 }; 190 191 /** 192 * struct dpu_drm_de_v1 - version 1 of detail enhancer structure 193 * @enable: Enables/disables detail enhancer 194 * @sharpen_level1: Sharpening strength for noise 195 * @sharpen_level2: Sharpening strength for context 196 * @clip: Clip coefficient 197 * @limit: Detail enhancer limit factor 198 * @thr_quiet: Quite zone threshold 199 * @thr_dieout: Die-out zone threshold 200 * @thr_low: Linear zone left threshold 201 * @thr_high: Linear zone right threshold 202 * @prec_shift: Detail enhancer precision 203 * @adjust_a: Mapping curves A coefficients 204 * @adjust_b: Mapping curves B coefficients 205 * @adjust_c: Mapping curves C coefficients 206 */ 207 struct dpu_drm_de_v1 { 208 uint32_t enable; 209 int16_t sharpen_level1; 210 int16_t sharpen_level2; 211 uint16_t clip; 212 uint16_t limit; 213 uint16_t thr_quiet; 214 uint16_t thr_dieout; 215 uint16_t thr_low; 216 uint16_t thr_high; 217 uint16_t prec_shift; 218 int16_t adjust_a[DPU_MAX_DE_CURVES]; 219 int16_t adjust_b[DPU_MAX_DE_CURVES]; 220 int16_t adjust_c[DPU_MAX_DE_CURVES]; 221 }; 222 223 /** 224 * struct dpu_drm_scaler_v2 - version 2 of struct dpu_drm_scaler 225 * @enable: Scaler enable 226 * @dir_en: Detail enhancer enable 227 * @pe: Pixel extension settings 228 * @horz_decimate: Horizontal decimation factor 229 * @vert_decimate: Vertical decimation factor 230 * @init_phase_x: Initial scaler phase values for x 231 * @phase_step_x: Phase step values for x 232 * @init_phase_y: Initial scaler phase values for y 233 * @phase_step_y: Phase step values for y 234 * @preload_x: Horizontal preload value 235 * @preload_y: Vertical preload value 236 * @src_width: Source width 237 * @src_height: Source height 238 * @dst_width: Destination width 239 * @dst_height: Destination height 240 * @y_rgb_filter_cfg: Y/RGB plane filter configuration 241 * @uv_filter_cfg: UV plane filter configuration 242 * @alpha_filter_cfg: Alpha filter configuration 243 * @blend_cfg: Selection of blend coefficients 244 * @lut_flag: LUT configuration flags 245 * @dir_lut_idx: 2d 4x4 LUT index 246 * @y_rgb_cir_lut_idx: Y/RGB circular LUT index 247 * @uv_cir_lut_idx: UV circular LUT index 248 * @y_rgb_sep_lut_idx: Y/RGB separable LUT index 249 * @uv_sep_lut_idx: UV separable LUT index 250 * @de: Detail enhancer settings 251 */ 252 struct dpu_drm_scaler_v2 { 253 /* 254 * General definitions 255 */ 256 uint32_t enable; 257 uint32_t dir_en; 258 259 /* 260 * Pix ext settings 261 */ 262 struct dpu_drm_pix_ext_v1 pe; 263 264 /* 265 * Decimation settings 266 */ 267 uint32_t horz_decimate; 268 uint32_t vert_decimate; 269 270 /* 271 * Phase settings 272 */ 273 int32_t init_phase_x[DPU_MAX_PLANES]; 274 int32_t phase_step_x[DPU_MAX_PLANES]; 275 int32_t init_phase_y[DPU_MAX_PLANES]; 276 int32_t phase_step_y[DPU_MAX_PLANES]; 277 278 uint32_t preload_x[DPU_MAX_PLANES]; 279 uint32_t preload_y[DPU_MAX_PLANES]; 280 uint32_t src_width[DPU_MAX_PLANES]; 281 uint32_t src_height[DPU_MAX_PLANES]; 282 283 uint32_t dst_width; 284 uint32_t dst_height; 285 286 uint32_t y_rgb_filter_cfg; 287 uint32_t uv_filter_cfg; 288 uint32_t alpha_filter_cfg; 289 uint32_t blend_cfg; 290 291 uint32_t lut_flag; 292 uint32_t dir_lut_idx; 293 294 /* for Y(RGB) and UV planes*/ 295 uint32_t y_rgb_cir_lut_idx; 296 uint32_t uv_cir_lut_idx; 297 uint32_t y_rgb_sep_lut_idx; 298 uint32_t uv_sep_lut_idx; 299 300 /* 301 * Detail enhancer settings 302 */ 303 struct dpu_drm_de_v1 de; 304 }; 305 306 307 u32 *dpu_hw_util_get_log_mask_ptr(void); 308 309 void dpu_reg_write(struct dpu_hw_blk_reg_map *c, 310 u32 reg_off, 311 u32 val, 312 const char *name); 313 int dpu_reg_read(struct dpu_hw_blk_reg_map *c, u32 reg_off); 314 315 #define DPU_REG_WRITE(c, off, val) dpu_reg_write(c, off, val, #off) 316 #define DPU_REG_READ(c, off) dpu_reg_read(c, off) 317 318 void *dpu_hw_util_get_dir(void); 319 320 void dpu_hw_setup_scaler3(struct dpu_hw_blk_reg_map *c, 321 struct dpu_hw_scaler3_cfg *scaler3_cfg, 322 u32 scaler_offset, u32 scaler_version, 323 const struct dpu_format *format); 324 325 u32 dpu_hw_get_scaler3_ver(struct dpu_hw_blk_reg_map *c, 326 u32 scaler_offset); 327 328 void dpu_hw_csc_setup(struct dpu_hw_blk_reg_map *c, 329 u32 csc_reg_off, 330 struct dpu_csc_cfg *data, bool csc10); 331 332 #endif /* _DPU_HW_UTIL_H */ 333