1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef _DPU_HW_UTIL_H 7 #define _DPU_HW_UTIL_H 8 9 #include <linux/io.h> 10 #include <linux/slab.h> 11 #include "dpu_hw_mdss.h" 12 #include "dpu_hw_catalog.h" 13 14 #define REG_MASK(n) ((BIT(n)) - 1) 15 16 /* 17 * This is the common struct maintained by each sub block 18 * for mapping the register offsets in this block to the 19 * absoulute IO address 20 * @base_off: mdp register mapped offset 21 * @blk_off: pipe offset relative to mdss offset 22 * @length length of register block offset 23 * @xin_id xin id 24 * @hwversion mdss hw version number 25 */ 26 struct dpu_hw_blk_reg_map { 27 void __iomem *base_off; 28 u32 blk_off; 29 u32 length; 30 u32 xin_id; 31 u32 hwversion; 32 u32 log_mask; 33 }; 34 35 /** 36 * struct dpu_hw_scaler3_de_cfg : QSEEDv3 detail enhancer configuration 37 * @enable: detail enhancer enable/disable 38 * @sharpen_level1: sharpening strength for noise 39 * @sharpen_level2: sharpening strength for signal 40 * @ clip: clip shift 41 * @ limit: limit value 42 * @ thr_quiet: quiet threshold 43 * @ thr_dieout: dieout threshold 44 * @ thr_high: low threshold 45 * @ thr_high: high threshold 46 * @ prec_shift: precision shift 47 * @ adjust_a: A-coefficients for mapping curve 48 * @ adjust_b: B-coefficients for mapping curve 49 * @ adjust_c: C-coefficients for mapping curve 50 */ 51 struct dpu_hw_scaler3_de_cfg { 52 u32 enable; 53 int16_t sharpen_level1; 54 int16_t sharpen_level2; 55 uint16_t clip; 56 uint16_t limit; 57 uint16_t thr_quiet; 58 uint16_t thr_dieout; 59 uint16_t thr_low; 60 uint16_t thr_high; 61 uint16_t prec_shift; 62 int16_t adjust_a[DPU_MAX_DE_CURVES]; 63 int16_t adjust_b[DPU_MAX_DE_CURVES]; 64 int16_t adjust_c[DPU_MAX_DE_CURVES]; 65 }; 66 67 68 /** 69 * struct dpu_hw_scaler3_cfg : QSEEDv3 configuration 70 * @enable: scaler enable 71 * @dir_en: direction detection block enable 72 * @ init_phase_x: horizontal initial phase 73 * @ phase_step_x: horizontal phase step 74 * @ init_phase_y: vertical initial phase 75 * @ phase_step_y: vertical phase step 76 * @ preload_x: horizontal preload value 77 * @ preload_y: vertical preload value 78 * @ src_width: source width 79 * @ src_height: source height 80 * @ dst_width: destination width 81 * @ dst_height: destination height 82 * @ y_rgb_filter_cfg: y/rgb plane filter configuration 83 * @ uv_filter_cfg: uv plane filter configuration 84 * @ alpha_filter_cfg: alpha filter configuration 85 * @ blend_cfg: blend coefficients configuration 86 * @ lut_flag: scaler LUT update flags 87 * 0x1 swap LUT bank 88 * 0x2 update 2D filter LUT 89 * 0x4 update y circular filter LUT 90 * 0x8 update uv circular filter LUT 91 * 0x10 update y separable filter LUT 92 * 0x20 update uv separable filter LUT 93 * @ dir_lut_idx: 2D filter LUT index 94 * @ y_rgb_cir_lut_idx: y circular filter LUT index 95 * @ uv_cir_lut_idx: uv circular filter LUT index 96 * @ y_rgb_sep_lut_idx: y circular filter LUT index 97 * @ uv_sep_lut_idx: uv separable filter LUT index 98 * @ dir_lut: pointer to 2D LUT 99 * @ cir_lut: pointer to circular filter LUT 100 * @ sep_lut: pointer to separable filter LUT 101 * @ de: detail enhancer configuration 102 * @ dir_weight: Directional weight 103 */ 104 struct dpu_hw_scaler3_cfg { 105 u32 enable; 106 u32 dir_en; 107 int32_t init_phase_x[DPU_MAX_PLANES]; 108 int32_t phase_step_x[DPU_MAX_PLANES]; 109 int32_t init_phase_y[DPU_MAX_PLANES]; 110 int32_t phase_step_y[DPU_MAX_PLANES]; 111 112 u32 preload_x[DPU_MAX_PLANES]; 113 u32 preload_y[DPU_MAX_PLANES]; 114 u32 src_width[DPU_MAX_PLANES]; 115 u32 src_height[DPU_MAX_PLANES]; 116 117 u32 dst_width; 118 u32 dst_height; 119 120 u32 y_rgb_filter_cfg; 121 u32 uv_filter_cfg; 122 u32 alpha_filter_cfg; 123 u32 blend_cfg; 124 125 u32 lut_flag; 126 u32 dir_lut_idx; 127 128 u32 y_rgb_cir_lut_idx; 129 u32 uv_cir_lut_idx; 130 u32 y_rgb_sep_lut_idx; 131 u32 uv_sep_lut_idx; 132 u32 *dir_lut; 133 size_t dir_len; 134 u32 *cir_lut; 135 size_t cir_len; 136 u32 *sep_lut; 137 size_t sep_len; 138 139 /* 140 * Detail enhancer settings 141 */ 142 struct dpu_hw_scaler3_de_cfg de; 143 144 u32 dir_weight; 145 }; 146 147 /** 148 * struct dpu_drm_pix_ext_v1 - version 1 of pixel ext structure 149 * @num_ext_pxls_lr: Number of total horizontal pixels 150 * @num_ext_pxls_tb: Number of total vertical lines 151 * @left_ftch: Number of extra pixels to overfetch from left 152 * @right_ftch: Number of extra pixels to overfetch from right 153 * @top_ftch: Number of extra lines to overfetch from top 154 * @btm_ftch: Number of extra lines to overfetch from bottom 155 * @left_rpt: Number of extra pixels to repeat from left 156 * @right_rpt: Number of extra pixels to repeat from right 157 * @top_rpt: Number of extra lines to repeat from top 158 * @btm_rpt: Number of extra lines to repeat from bottom 159 */ 160 struct dpu_drm_pix_ext_v1 { 161 /* 162 * Number of pixels ext in left, right, top and bottom direction 163 * for all color components. 164 */ 165 int32_t num_ext_pxls_lr[DPU_MAX_PLANES]; 166 int32_t num_ext_pxls_tb[DPU_MAX_PLANES]; 167 168 /* 169 * Number of pixels needs to be overfetched in left, right, top 170 * and bottom directions from source image for scaling. 171 */ 172 int32_t left_ftch[DPU_MAX_PLANES]; 173 int32_t right_ftch[DPU_MAX_PLANES]; 174 int32_t top_ftch[DPU_MAX_PLANES]; 175 int32_t btm_ftch[DPU_MAX_PLANES]; 176 /* 177 * Number of pixels needs to be repeated in left, right, top and 178 * bottom directions for scaling. 179 */ 180 int32_t left_rpt[DPU_MAX_PLANES]; 181 int32_t right_rpt[DPU_MAX_PLANES]; 182 int32_t top_rpt[DPU_MAX_PLANES]; 183 int32_t btm_rpt[DPU_MAX_PLANES]; 184 185 }; 186 187 /** 188 * struct dpu_drm_de_v1 - version 1 of detail enhancer structure 189 * @enable: Enables/disables detail enhancer 190 * @sharpen_level1: Sharpening strength for noise 191 * @sharpen_level2: Sharpening strength for context 192 * @clip: Clip coefficient 193 * @limit: Detail enhancer limit factor 194 * @thr_quiet: Quite zone threshold 195 * @thr_dieout: Die-out zone threshold 196 * @thr_low: Linear zone left threshold 197 * @thr_high: Linear zone right threshold 198 * @prec_shift: Detail enhancer precision 199 * @adjust_a: Mapping curves A coefficients 200 * @adjust_b: Mapping curves B coefficients 201 * @adjust_c: Mapping curves C coefficients 202 */ 203 struct dpu_drm_de_v1 { 204 uint32_t enable; 205 int16_t sharpen_level1; 206 int16_t sharpen_level2; 207 uint16_t clip; 208 uint16_t limit; 209 uint16_t thr_quiet; 210 uint16_t thr_dieout; 211 uint16_t thr_low; 212 uint16_t thr_high; 213 uint16_t prec_shift; 214 int16_t adjust_a[DPU_MAX_DE_CURVES]; 215 int16_t adjust_b[DPU_MAX_DE_CURVES]; 216 int16_t adjust_c[DPU_MAX_DE_CURVES]; 217 }; 218 219 /** 220 * struct dpu_drm_scaler_v2 - version 2 of struct dpu_drm_scaler 221 * @enable: Scaler enable 222 * @dir_en: Detail enhancer enable 223 * @pe: Pixel extension settings 224 * @horz_decimate: Horizontal decimation factor 225 * @vert_decimate: Vertical decimation factor 226 * @init_phase_x: Initial scaler phase values for x 227 * @phase_step_x: Phase step values for x 228 * @init_phase_y: Initial scaler phase values for y 229 * @phase_step_y: Phase step values for y 230 * @preload_x: Horizontal preload value 231 * @preload_y: Vertical preload value 232 * @src_width: Source width 233 * @src_height: Source height 234 * @dst_width: Destination width 235 * @dst_height: Destination height 236 * @y_rgb_filter_cfg: Y/RGB plane filter configuration 237 * @uv_filter_cfg: UV plane filter configuration 238 * @alpha_filter_cfg: Alpha filter configuration 239 * @blend_cfg: Selection of blend coefficients 240 * @lut_flag: LUT configuration flags 241 * @dir_lut_idx: 2d 4x4 LUT index 242 * @y_rgb_cir_lut_idx: Y/RGB circular LUT index 243 * @uv_cir_lut_idx: UV circular LUT index 244 * @y_rgb_sep_lut_idx: Y/RGB separable LUT index 245 * @uv_sep_lut_idx: UV separable LUT index 246 * @de: Detail enhancer settings 247 */ 248 struct dpu_drm_scaler_v2 { 249 /* 250 * General definitions 251 */ 252 uint32_t enable; 253 uint32_t dir_en; 254 255 /* 256 * Pix ext settings 257 */ 258 struct dpu_drm_pix_ext_v1 pe; 259 260 /* 261 * Decimation settings 262 */ 263 uint32_t horz_decimate; 264 uint32_t vert_decimate; 265 266 /* 267 * Phase settings 268 */ 269 int32_t init_phase_x[DPU_MAX_PLANES]; 270 int32_t phase_step_x[DPU_MAX_PLANES]; 271 int32_t init_phase_y[DPU_MAX_PLANES]; 272 int32_t phase_step_y[DPU_MAX_PLANES]; 273 274 uint32_t preload_x[DPU_MAX_PLANES]; 275 uint32_t preload_y[DPU_MAX_PLANES]; 276 uint32_t src_width[DPU_MAX_PLANES]; 277 uint32_t src_height[DPU_MAX_PLANES]; 278 279 uint32_t dst_width; 280 uint32_t dst_height; 281 282 uint32_t y_rgb_filter_cfg; 283 uint32_t uv_filter_cfg; 284 uint32_t alpha_filter_cfg; 285 uint32_t blend_cfg; 286 287 uint32_t lut_flag; 288 uint32_t dir_lut_idx; 289 290 /* for Y(RGB) and UV planes*/ 291 uint32_t y_rgb_cir_lut_idx; 292 uint32_t uv_cir_lut_idx; 293 uint32_t y_rgb_sep_lut_idx; 294 uint32_t uv_sep_lut_idx; 295 296 /* 297 * Detail enhancer settings 298 */ 299 struct dpu_drm_de_v1 de; 300 }; 301 302 /** 303 * struct dpu_hw_cdp_cfg : CDP configuration 304 * @enable: true to enable CDP 305 * @ubwc_meta_enable: true to enable ubwc metadata preload 306 * @tile_amortize_enable: true to enable amortization control for tile format 307 * @preload_ahead: number of request to preload ahead 308 * DPU_*_CDP_PRELOAD_AHEAD_32, 309 * DPU_*_CDP_PRELOAD_AHEAD_64 310 */ 311 struct dpu_hw_cdp_cfg { 312 bool enable; 313 bool ubwc_meta_enable; 314 bool tile_amortize_enable; 315 u32 preload_ahead; 316 }; 317 318 u32 *dpu_hw_util_get_log_mask_ptr(void); 319 320 void dpu_reg_write(struct dpu_hw_blk_reg_map *c, 321 u32 reg_off, 322 u32 val, 323 const char *name); 324 int dpu_reg_read(struct dpu_hw_blk_reg_map *c, u32 reg_off); 325 326 #define DPU_REG_WRITE(c, off, val) dpu_reg_write(c, off, val, #off) 327 #define DPU_REG_READ(c, off) dpu_reg_read(c, off) 328 329 void *dpu_hw_util_get_dir(void); 330 331 void dpu_hw_setup_scaler3(struct dpu_hw_blk_reg_map *c, 332 struct dpu_hw_scaler3_cfg *scaler3_cfg, 333 u32 scaler_offset, u32 scaler_version, 334 const struct dpu_format *format); 335 336 u32 dpu_hw_get_scaler3_ver(struct dpu_hw_blk_reg_map *c, 337 u32 scaler_offset); 338 339 void dpu_hw_csc_setup(struct dpu_hw_blk_reg_map *c, 340 u32 csc_reg_off, 341 const struct dpu_csc_cfg *data, bool csc10); 342 343 u64 _dpu_hw_get_qos_lut(const struct dpu_qos_lut_tbl *tbl, 344 u32 total_fl); 345 346 #endif /* _DPU_HW_UTIL_H */ 347