1 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 2 * 3 * This program is free software; you can redistribute it and/or modify 4 * it under the terms of the GNU General Public License version 2 and 5 * only version 2 as published by the Free Software Foundation. 6 * 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 */ 12 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ 13 14 #include "msm_drv.h" 15 #include "dpu_kms.h" 16 #include "dpu_hw_mdss.h" 17 #include "dpu_hw_util.h" 18 19 /* using a file static variables for debugfs access */ 20 static u32 dpu_hw_util_log_mask = DPU_DBG_MASK_NONE; 21 22 /* DPU_SCALER_QSEED3 */ 23 #define QSEED3_HW_VERSION 0x00 24 #define QSEED3_OP_MODE 0x04 25 #define QSEED3_RGB2Y_COEFF 0x08 26 #define QSEED3_PHASE_INIT 0x0C 27 #define QSEED3_PHASE_STEP_Y_H 0x10 28 #define QSEED3_PHASE_STEP_Y_V 0x14 29 #define QSEED3_PHASE_STEP_UV_H 0x18 30 #define QSEED3_PHASE_STEP_UV_V 0x1C 31 #define QSEED3_PRELOAD 0x20 32 #define QSEED3_DE_SHARPEN 0x24 33 #define QSEED3_DE_SHARPEN_CTL 0x28 34 #define QSEED3_DE_SHAPE_CTL 0x2C 35 #define QSEED3_DE_THRESHOLD 0x30 36 #define QSEED3_DE_ADJUST_DATA_0 0x34 37 #define QSEED3_DE_ADJUST_DATA_1 0x38 38 #define QSEED3_DE_ADJUST_DATA_2 0x3C 39 #define QSEED3_SRC_SIZE_Y_RGB_A 0x40 40 #define QSEED3_SRC_SIZE_UV 0x44 41 #define QSEED3_DST_SIZE 0x48 42 #define QSEED3_COEF_LUT_CTRL 0x4C 43 #define QSEED3_COEF_LUT_SWAP_BIT 0 44 #define QSEED3_COEF_LUT_DIR_BIT 1 45 #define QSEED3_COEF_LUT_Y_CIR_BIT 2 46 #define QSEED3_COEF_LUT_UV_CIR_BIT 3 47 #define QSEED3_COEF_LUT_Y_SEP_BIT 4 48 #define QSEED3_COEF_LUT_UV_SEP_BIT 5 49 #define QSEED3_BUFFER_CTRL 0x50 50 #define QSEED3_CLK_CTRL0 0x54 51 #define QSEED3_CLK_CTRL1 0x58 52 #define QSEED3_CLK_STATUS 0x5C 53 #define QSEED3_MISR_CTRL 0x70 54 #define QSEED3_MISR_SIGNATURE_0 0x74 55 #define QSEED3_MISR_SIGNATURE_1 0x78 56 #define QSEED3_PHASE_INIT_Y_H 0x90 57 #define QSEED3_PHASE_INIT_Y_V 0x94 58 #define QSEED3_PHASE_INIT_UV_H 0x98 59 #define QSEED3_PHASE_INIT_UV_V 0x9C 60 #define QSEED3_COEF_LUT 0x100 61 #define QSEED3_FILTERS 5 62 #define QSEED3_LUT_REGIONS 4 63 #define QSEED3_CIRCULAR_LUTS 9 64 #define QSEED3_SEPARABLE_LUTS 10 65 #define QSEED3_LUT_SIZE 60 66 #define QSEED3_ENABLE 2 67 #define QSEED3_DIR_LUT_SIZE (200 * sizeof(u32)) 68 #define QSEED3_CIR_LUT_SIZE \ 69 (QSEED3_LUT_SIZE * QSEED3_CIRCULAR_LUTS * sizeof(u32)) 70 #define QSEED3_SEP_LUT_SIZE \ 71 (QSEED3_LUT_SIZE * QSEED3_SEPARABLE_LUTS * sizeof(u32)) 72 73 void dpu_reg_write(struct dpu_hw_blk_reg_map *c, 74 u32 reg_off, 75 u32 val, 76 const char *name) 77 { 78 /* don't need to mutex protect this */ 79 if (c->log_mask & dpu_hw_util_log_mask) 80 DPU_DEBUG_DRIVER("[%s:0x%X] <= 0x%X\n", 81 name, c->blk_off + reg_off, val); 82 writel_relaxed(val, c->base_off + c->blk_off + reg_off); 83 } 84 85 int dpu_reg_read(struct dpu_hw_blk_reg_map *c, u32 reg_off) 86 { 87 return readl_relaxed(c->base_off + c->blk_off + reg_off); 88 } 89 90 u32 *dpu_hw_util_get_log_mask_ptr(void) 91 { 92 return &dpu_hw_util_log_mask; 93 } 94 95 void dpu_set_scaler_v2(struct dpu_hw_scaler3_cfg *cfg, 96 const struct dpu_drm_scaler_v2 *scale_v2) 97 { 98 int i; 99 100 cfg->enable = scale_v2->enable; 101 cfg->dir_en = scale_v2->dir_en; 102 103 for (i = 0; i < DPU_MAX_PLANES; i++) { 104 cfg->init_phase_x[i] = scale_v2->init_phase_x[i]; 105 cfg->phase_step_x[i] = scale_v2->phase_step_x[i]; 106 cfg->init_phase_y[i] = scale_v2->init_phase_y[i]; 107 cfg->phase_step_y[i] = scale_v2->phase_step_y[i]; 108 109 cfg->preload_x[i] = scale_v2->preload_x[i]; 110 cfg->preload_y[i] = scale_v2->preload_y[i]; 111 cfg->src_width[i] = scale_v2->src_width[i]; 112 cfg->src_height[i] = scale_v2->src_height[i]; 113 } 114 115 cfg->dst_width = scale_v2->dst_width; 116 cfg->dst_height = scale_v2->dst_height; 117 118 cfg->y_rgb_filter_cfg = scale_v2->y_rgb_filter_cfg; 119 cfg->uv_filter_cfg = scale_v2->uv_filter_cfg; 120 cfg->alpha_filter_cfg = scale_v2->alpha_filter_cfg; 121 cfg->blend_cfg = scale_v2->blend_cfg; 122 123 cfg->lut_flag = scale_v2->lut_flag; 124 cfg->dir_lut_idx = scale_v2->dir_lut_idx; 125 cfg->y_rgb_cir_lut_idx = scale_v2->y_rgb_cir_lut_idx; 126 cfg->uv_cir_lut_idx = scale_v2->uv_cir_lut_idx; 127 cfg->y_rgb_sep_lut_idx = scale_v2->y_rgb_sep_lut_idx; 128 cfg->uv_sep_lut_idx = scale_v2->uv_sep_lut_idx; 129 130 cfg->de.enable = scale_v2->de.enable; 131 cfg->de.sharpen_level1 = scale_v2->de.sharpen_level1; 132 cfg->de.sharpen_level2 = scale_v2->de.sharpen_level2; 133 cfg->de.clip = scale_v2->de.clip; 134 cfg->de.limit = scale_v2->de.limit; 135 cfg->de.thr_quiet = scale_v2->de.thr_quiet; 136 cfg->de.thr_dieout = scale_v2->de.thr_dieout; 137 cfg->de.thr_low = scale_v2->de.thr_low; 138 cfg->de.thr_high = scale_v2->de.thr_high; 139 cfg->de.prec_shift = scale_v2->de.prec_shift; 140 141 for (i = 0; i < DPU_MAX_DE_CURVES; i++) { 142 cfg->de.adjust_a[i] = scale_v2->de.adjust_a[i]; 143 cfg->de.adjust_b[i] = scale_v2->de.adjust_b[i]; 144 cfg->de.adjust_c[i] = scale_v2->de.adjust_c[i]; 145 } 146 } 147 148 static void _dpu_hw_setup_scaler3_lut(struct dpu_hw_blk_reg_map *c, 149 struct dpu_hw_scaler3_cfg *scaler3_cfg, u32 offset) 150 { 151 int i, j, filter; 152 int config_lut = 0x0; 153 unsigned long lut_flags; 154 u32 lut_addr, lut_offset, lut_len; 155 u32 *lut[QSEED3_FILTERS] = {NULL, NULL, NULL, NULL, NULL}; 156 static const uint32_t off_tbl[QSEED3_FILTERS][QSEED3_LUT_REGIONS][2] = { 157 {{18, 0x000}, {12, 0x120}, {12, 0x1E0}, {8, 0x2A0} }, 158 {{6, 0x320}, {3, 0x3E0}, {3, 0x440}, {3, 0x4A0} }, 159 {{6, 0x500}, {3, 0x5c0}, {3, 0x620}, {3, 0x680} }, 160 {{6, 0x380}, {3, 0x410}, {3, 0x470}, {3, 0x4d0} }, 161 {{6, 0x560}, {3, 0x5f0}, {3, 0x650}, {3, 0x6b0} }, 162 }; 163 164 lut_flags = (unsigned long) scaler3_cfg->lut_flag; 165 if (test_bit(QSEED3_COEF_LUT_DIR_BIT, &lut_flags) && 166 (scaler3_cfg->dir_len == QSEED3_DIR_LUT_SIZE)) { 167 lut[0] = scaler3_cfg->dir_lut; 168 config_lut = 1; 169 } 170 if (test_bit(QSEED3_COEF_LUT_Y_CIR_BIT, &lut_flags) && 171 (scaler3_cfg->y_rgb_cir_lut_idx < QSEED3_CIRCULAR_LUTS) && 172 (scaler3_cfg->cir_len == QSEED3_CIR_LUT_SIZE)) { 173 lut[1] = scaler3_cfg->cir_lut + 174 scaler3_cfg->y_rgb_cir_lut_idx * QSEED3_LUT_SIZE; 175 config_lut = 1; 176 } 177 if (test_bit(QSEED3_COEF_LUT_UV_CIR_BIT, &lut_flags) && 178 (scaler3_cfg->uv_cir_lut_idx < QSEED3_CIRCULAR_LUTS) && 179 (scaler3_cfg->cir_len == QSEED3_CIR_LUT_SIZE)) { 180 lut[2] = scaler3_cfg->cir_lut + 181 scaler3_cfg->uv_cir_lut_idx * QSEED3_LUT_SIZE; 182 config_lut = 1; 183 } 184 if (test_bit(QSEED3_COEF_LUT_Y_SEP_BIT, &lut_flags) && 185 (scaler3_cfg->y_rgb_sep_lut_idx < QSEED3_SEPARABLE_LUTS) && 186 (scaler3_cfg->sep_len == QSEED3_SEP_LUT_SIZE)) { 187 lut[3] = scaler3_cfg->sep_lut + 188 scaler3_cfg->y_rgb_sep_lut_idx * QSEED3_LUT_SIZE; 189 config_lut = 1; 190 } 191 if (test_bit(QSEED3_COEF_LUT_UV_SEP_BIT, &lut_flags) && 192 (scaler3_cfg->uv_sep_lut_idx < QSEED3_SEPARABLE_LUTS) && 193 (scaler3_cfg->sep_len == QSEED3_SEP_LUT_SIZE)) { 194 lut[4] = scaler3_cfg->sep_lut + 195 scaler3_cfg->uv_sep_lut_idx * QSEED3_LUT_SIZE; 196 config_lut = 1; 197 } 198 199 if (config_lut) { 200 for (filter = 0; filter < QSEED3_FILTERS; filter++) { 201 if (!lut[filter]) 202 continue; 203 lut_offset = 0; 204 for (i = 0; i < QSEED3_LUT_REGIONS; i++) { 205 lut_addr = QSEED3_COEF_LUT + offset 206 + off_tbl[filter][i][1]; 207 lut_len = off_tbl[filter][i][0] << 2; 208 for (j = 0; j < lut_len; j++) { 209 DPU_REG_WRITE(c, 210 lut_addr, 211 (lut[filter])[lut_offset++]); 212 lut_addr += 4; 213 } 214 } 215 } 216 } 217 218 if (test_bit(QSEED3_COEF_LUT_SWAP_BIT, &lut_flags)) 219 DPU_REG_WRITE(c, QSEED3_COEF_LUT_CTRL + offset, BIT(0)); 220 221 } 222 223 static void _dpu_hw_setup_scaler3_de(struct dpu_hw_blk_reg_map *c, 224 struct dpu_hw_scaler3_de_cfg *de_cfg, u32 offset) 225 { 226 u32 sharp_lvl, sharp_ctl, shape_ctl, de_thr; 227 u32 adjust_a, adjust_b, adjust_c; 228 229 if (!de_cfg->enable) 230 return; 231 232 sharp_lvl = (de_cfg->sharpen_level1 & 0x1FF) | 233 ((de_cfg->sharpen_level2 & 0x1FF) << 16); 234 235 sharp_ctl = ((de_cfg->limit & 0xF) << 9) | 236 ((de_cfg->prec_shift & 0x7) << 13) | 237 ((de_cfg->clip & 0x7) << 16); 238 239 shape_ctl = (de_cfg->thr_quiet & 0xFF) | 240 ((de_cfg->thr_dieout & 0x3FF) << 16); 241 242 de_thr = (de_cfg->thr_low & 0x3FF) | 243 ((de_cfg->thr_high & 0x3FF) << 16); 244 245 adjust_a = (de_cfg->adjust_a[0] & 0x3FF) | 246 ((de_cfg->adjust_a[1] & 0x3FF) << 10) | 247 ((de_cfg->adjust_a[2] & 0x3FF) << 20); 248 249 adjust_b = (de_cfg->adjust_b[0] & 0x3FF) | 250 ((de_cfg->adjust_b[1] & 0x3FF) << 10) | 251 ((de_cfg->adjust_b[2] & 0x3FF) << 20); 252 253 adjust_c = (de_cfg->adjust_c[0] & 0x3FF) | 254 ((de_cfg->adjust_c[1] & 0x3FF) << 10) | 255 ((de_cfg->adjust_c[2] & 0x3FF) << 20); 256 257 DPU_REG_WRITE(c, QSEED3_DE_SHARPEN + offset, sharp_lvl); 258 DPU_REG_WRITE(c, QSEED3_DE_SHARPEN_CTL + offset, sharp_ctl); 259 DPU_REG_WRITE(c, QSEED3_DE_SHAPE_CTL + offset, shape_ctl); 260 DPU_REG_WRITE(c, QSEED3_DE_THRESHOLD + offset, de_thr); 261 DPU_REG_WRITE(c, QSEED3_DE_ADJUST_DATA_0 + offset, adjust_a); 262 DPU_REG_WRITE(c, QSEED3_DE_ADJUST_DATA_1 + offset, adjust_b); 263 DPU_REG_WRITE(c, QSEED3_DE_ADJUST_DATA_2 + offset, adjust_c); 264 265 } 266 267 void dpu_hw_setup_scaler3(struct dpu_hw_blk_reg_map *c, 268 struct dpu_hw_scaler3_cfg *scaler3_cfg, 269 u32 scaler_offset, u32 scaler_version, 270 const struct dpu_format *format) 271 { 272 u32 op_mode = 0; 273 u32 phase_init, preload, src_y_rgb, src_uv, dst; 274 275 if (!scaler3_cfg->enable) 276 goto end; 277 278 op_mode |= BIT(0); 279 op_mode |= (scaler3_cfg->y_rgb_filter_cfg & 0x3) << 16; 280 281 if (format && DPU_FORMAT_IS_YUV(format)) { 282 op_mode |= BIT(12); 283 op_mode |= (scaler3_cfg->uv_filter_cfg & 0x3) << 24; 284 } 285 286 op_mode |= (scaler3_cfg->blend_cfg & 1) << 31; 287 op_mode |= (scaler3_cfg->dir_en) ? BIT(4) : 0; 288 289 preload = 290 ((scaler3_cfg->preload_x[0] & 0x7F) << 0) | 291 ((scaler3_cfg->preload_y[0] & 0x7F) << 8) | 292 ((scaler3_cfg->preload_x[1] & 0x7F) << 16) | 293 ((scaler3_cfg->preload_y[1] & 0x7F) << 24); 294 295 src_y_rgb = (scaler3_cfg->src_width[0] & 0x1FFFF) | 296 ((scaler3_cfg->src_height[0] & 0x1FFFF) << 16); 297 298 src_uv = (scaler3_cfg->src_width[1] & 0x1FFFF) | 299 ((scaler3_cfg->src_height[1] & 0x1FFFF) << 16); 300 301 dst = (scaler3_cfg->dst_width & 0x1FFFF) | 302 ((scaler3_cfg->dst_height & 0x1FFFF) << 16); 303 304 if (scaler3_cfg->de.enable) { 305 _dpu_hw_setup_scaler3_de(c, &scaler3_cfg->de, scaler_offset); 306 op_mode |= BIT(8); 307 } 308 309 if (scaler3_cfg->lut_flag) 310 _dpu_hw_setup_scaler3_lut(c, scaler3_cfg, 311 scaler_offset); 312 313 if (scaler_version == 0x1002) { 314 phase_init = 315 ((scaler3_cfg->init_phase_x[0] & 0x3F) << 0) | 316 ((scaler3_cfg->init_phase_y[0] & 0x3F) << 8) | 317 ((scaler3_cfg->init_phase_x[1] & 0x3F) << 16) | 318 ((scaler3_cfg->init_phase_y[1] & 0x3F) << 24); 319 DPU_REG_WRITE(c, QSEED3_PHASE_INIT + scaler_offset, phase_init); 320 } else { 321 DPU_REG_WRITE(c, QSEED3_PHASE_INIT_Y_H + scaler_offset, 322 scaler3_cfg->init_phase_x[0] & 0x1FFFFF); 323 DPU_REG_WRITE(c, QSEED3_PHASE_INIT_Y_V + scaler_offset, 324 scaler3_cfg->init_phase_y[0] & 0x1FFFFF); 325 DPU_REG_WRITE(c, QSEED3_PHASE_INIT_UV_H + scaler_offset, 326 scaler3_cfg->init_phase_x[1] & 0x1FFFFF); 327 DPU_REG_WRITE(c, QSEED3_PHASE_INIT_UV_V + scaler_offset, 328 scaler3_cfg->init_phase_y[1] & 0x1FFFFF); 329 } 330 331 DPU_REG_WRITE(c, QSEED3_PHASE_STEP_Y_H + scaler_offset, 332 scaler3_cfg->phase_step_x[0] & 0xFFFFFF); 333 334 DPU_REG_WRITE(c, QSEED3_PHASE_STEP_Y_V + scaler_offset, 335 scaler3_cfg->phase_step_y[0] & 0xFFFFFF); 336 337 DPU_REG_WRITE(c, QSEED3_PHASE_STEP_UV_H + scaler_offset, 338 scaler3_cfg->phase_step_x[1] & 0xFFFFFF); 339 340 DPU_REG_WRITE(c, QSEED3_PHASE_STEP_UV_V + scaler_offset, 341 scaler3_cfg->phase_step_y[1] & 0xFFFFFF); 342 343 DPU_REG_WRITE(c, QSEED3_PRELOAD + scaler_offset, preload); 344 345 DPU_REG_WRITE(c, QSEED3_SRC_SIZE_Y_RGB_A + scaler_offset, src_y_rgb); 346 347 DPU_REG_WRITE(c, QSEED3_SRC_SIZE_UV + scaler_offset, src_uv); 348 349 DPU_REG_WRITE(c, QSEED3_DST_SIZE + scaler_offset, dst); 350 351 end: 352 if (format && !DPU_FORMAT_IS_DX(format)) 353 op_mode |= BIT(14); 354 355 if (format && format->alpha_enable) { 356 op_mode |= BIT(10); 357 if (scaler_version == 0x1002) 358 op_mode |= (scaler3_cfg->alpha_filter_cfg & 0x1) << 30; 359 else 360 op_mode |= (scaler3_cfg->alpha_filter_cfg & 0x3) << 29; 361 } 362 363 DPU_REG_WRITE(c, QSEED3_OP_MODE + scaler_offset, op_mode); 364 } 365 366 u32 dpu_hw_get_scaler3_ver(struct dpu_hw_blk_reg_map *c, 367 u32 scaler_offset) 368 { 369 return DPU_REG_READ(c, QSEED3_HW_VERSION + scaler_offset); 370 } 371 372 void dpu_hw_csc_setup(struct dpu_hw_blk_reg_map *c, 373 u32 csc_reg_off, 374 struct dpu_csc_cfg *data, bool csc10) 375 { 376 static const u32 matrix_shift = 7; 377 u32 clamp_shift = csc10 ? 16 : 8; 378 u32 val; 379 380 /* matrix coeff - convert S15.16 to S4.9 */ 381 val = ((data->csc_mv[0] >> matrix_shift) & 0x1FFF) | 382 (((data->csc_mv[1] >> matrix_shift) & 0x1FFF) << 16); 383 DPU_REG_WRITE(c, csc_reg_off, val); 384 val = ((data->csc_mv[2] >> matrix_shift) & 0x1FFF) | 385 (((data->csc_mv[3] >> matrix_shift) & 0x1FFF) << 16); 386 DPU_REG_WRITE(c, csc_reg_off + 0x4, val); 387 val = ((data->csc_mv[4] >> matrix_shift) & 0x1FFF) | 388 (((data->csc_mv[5] >> matrix_shift) & 0x1FFF) << 16); 389 DPU_REG_WRITE(c, csc_reg_off + 0x8, val); 390 val = ((data->csc_mv[6] >> matrix_shift) & 0x1FFF) | 391 (((data->csc_mv[7] >> matrix_shift) & 0x1FFF) << 16); 392 DPU_REG_WRITE(c, csc_reg_off + 0xc, val); 393 val = (data->csc_mv[8] >> matrix_shift) & 0x1FFF; 394 DPU_REG_WRITE(c, csc_reg_off + 0x10, val); 395 396 /* Pre clamp */ 397 val = (data->csc_pre_lv[0] << clamp_shift) | data->csc_pre_lv[1]; 398 DPU_REG_WRITE(c, csc_reg_off + 0x14, val); 399 val = (data->csc_pre_lv[2] << clamp_shift) | data->csc_pre_lv[3]; 400 DPU_REG_WRITE(c, csc_reg_off + 0x18, val); 401 val = (data->csc_pre_lv[4] << clamp_shift) | data->csc_pre_lv[5]; 402 DPU_REG_WRITE(c, csc_reg_off + 0x1c, val); 403 404 /* Post clamp */ 405 val = (data->csc_post_lv[0] << clamp_shift) | data->csc_post_lv[1]; 406 DPU_REG_WRITE(c, csc_reg_off + 0x20, val); 407 val = (data->csc_post_lv[2] << clamp_shift) | data->csc_post_lv[3]; 408 DPU_REG_WRITE(c, csc_reg_off + 0x24, val); 409 val = (data->csc_post_lv[4] << clamp_shift) | data->csc_post_lv[5]; 410 DPU_REG_WRITE(c, csc_reg_off + 0x28, val); 411 412 /* Pre-Bias */ 413 DPU_REG_WRITE(c, csc_reg_off + 0x2c, data->csc_pre_bv[0]); 414 DPU_REG_WRITE(c, csc_reg_off + 0x30, data->csc_pre_bv[1]); 415 DPU_REG_WRITE(c, csc_reg_off + 0x34, data->csc_pre_bv[2]); 416 417 /* Post-Bias */ 418 DPU_REG_WRITE(c, csc_reg_off + 0x38, data->csc_post_bv[0]); 419 DPU_REG_WRITE(c, csc_reg_off + 0x3c, data->csc_post_bv[1]); 420 DPU_REG_WRITE(c, csc_reg_off + 0x40, data->csc_post_bv[2]); 421 } 422 423 /** 424 * _dpu_copy_formats - copy formats from src_list to dst_list 425 * @dst_list: pointer to destination list where to copy formats 426 * @dst_list_size: size of destination list 427 * @dst_list_pos: starting position on the list where to copy formats 428 * @src_list: pointer to source list where to copy formats from 429 * @src_list_size: size of source list 430 * Return: number of elements populated 431 */ 432 uint32_t dpu_copy_formats( 433 struct dpu_format_extended *dst_list, 434 uint32_t dst_list_size, 435 uint32_t dst_list_pos, 436 const struct dpu_format_extended *src_list, 437 uint32_t src_list_size) 438 { 439 uint32_t cur_pos, i; 440 441 if (!dst_list || !src_list || (dst_list_pos >= (dst_list_size - 1))) 442 return 0; 443 444 for (i = 0, cur_pos = dst_list_pos; 445 (cur_pos < (dst_list_size - 1)) && (i < src_list_size) 446 && src_list[i].fourcc_format; ++i, ++cur_pos) 447 dst_list[cur_pos] = src_list[i]; 448 449 dst_list[cur_pos].fourcc_format = 0; 450 451 return i; 452 } 453