1 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 2 * 3 * This program is free software; you can redistribute it and/or modify 4 * it under the terms of the GNU General Public License version 2 and 5 * only version 2 as published by the Free Software Foundation. 6 * 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 */ 12 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ 13 14 #include "msm_drv.h" 15 #include "dpu_kms.h" 16 #include "dpu_hw_mdss.h" 17 #include "dpu_hw_util.h" 18 19 /* using a file static variables for debugfs access */ 20 static u32 dpu_hw_util_log_mask = DPU_DBG_MASK_NONE; 21 22 /* DPU_SCALER_QSEED3 */ 23 #define QSEED3_HW_VERSION 0x00 24 #define QSEED3_OP_MODE 0x04 25 #define QSEED3_RGB2Y_COEFF 0x08 26 #define QSEED3_PHASE_INIT 0x0C 27 #define QSEED3_PHASE_STEP_Y_H 0x10 28 #define QSEED3_PHASE_STEP_Y_V 0x14 29 #define QSEED3_PHASE_STEP_UV_H 0x18 30 #define QSEED3_PHASE_STEP_UV_V 0x1C 31 #define QSEED3_PRELOAD 0x20 32 #define QSEED3_DE_SHARPEN 0x24 33 #define QSEED3_DE_SHARPEN_CTL 0x28 34 #define QSEED3_DE_SHAPE_CTL 0x2C 35 #define QSEED3_DE_THRESHOLD 0x30 36 #define QSEED3_DE_ADJUST_DATA_0 0x34 37 #define QSEED3_DE_ADJUST_DATA_1 0x38 38 #define QSEED3_DE_ADJUST_DATA_2 0x3C 39 #define QSEED3_SRC_SIZE_Y_RGB_A 0x40 40 #define QSEED3_SRC_SIZE_UV 0x44 41 #define QSEED3_DST_SIZE 0x48 42 #define QSEED3_COEF_LUT_CTRL 0x4C 43 #define QSEED3_COEF_LUT_SWAP_BIT 0 44 #define QSEED3_COEF_LUT_DIR_BIT 1 45 #define QSEED3_COEF_LUT_Y_CIR_BIT 2 46 #define QSEED3_COEF_LUT_UV_CIR_BIT 3 47 #define QSEED3_COEF_LUT_Y_SEP_BIT 4 48 #define QSEED3_COEF_LUT_UV_SEP_BIT 5 49 #define QSEED3_BUFFER_CTRL 0x50 50 #define QSEED3_CLK_CTRL0 0x54 51 #define QSEED3_CLK_CTRL1 0x58 52 #define QSEED3_CLK_STATUS 0x5C 53 #define QSEED3_PHASE_INIT_Y_H 0x90 54 #define QSEED3_PHASE_INIT_Y_V 0x94 55 #define QSEED3_PHASE_INIT_UV_H 0x98 56 #define QSEED3_PHASE_INIT_UV_V 0x9C 57 #define QSEED3_COEF_LUT 0x100 58 #define QSEED3_FILTERS 5 59 #define QSEED3_LUT_REGIONS 4 60 #define QSEED3_CIRCULAR_LUTS 9 61 #define QSEED3_SEPARABLE_LUTS 10 62 #define QSEED3_LUT_SIZE 60 63 #define QSEED3_ENABLE 2 64 #define QSEED3_DIR_LUT_SIZE (200 * sizeof(u32)) 65 #define QSEED3_CIR_LUT_SIZE \ 66 (QSEED3_LUT_SIZE * QSEED3_CIRCULAR_LUTS * sizeof(u32)) 67 #define QSEED3_SEP_LUT_SIZE \ 68 (QSEED3_LUT_SIZE * QSEED3_SEPARABLE_LUTS * sizeof(u32)) 69 70 void dpu_reg_write(struct dpu_hw_blk_reg_map *c, 71 u32 reg_off, 72 u32 val, 73 const char *name) 74 { 75 /* don't need to mutex protect this */ 76 if (c->log_mask & dpu_hw_util_log_mask) 77 DPU_DEBUG_DRIVER("[%s:0x%X] <= 0x%X\n", 78 name, c->blk_off + reg_off, val); 79 writel_relaxed(val, c->base_off + c->blk_off + reg_off); 80 } 81 82 int dpu_reg_read(struct dpu_hw_blk_reg_map *c, u32 reg_off) 83 { 84 return readl_relaxed(c->base_off + c->blk_off + reg_off); 85 } 86 87 u32 *dpu_hw_util_get_log_mask_ptr(void) 88 { 89 return &dpu_hw_util_log_mask; 90 } 91 92 static void _dpu_hw_setup_scaler3_lut(struct dpu_hw_blk_reg_map *c, 93 struct dpu_hw_scaler3_cfg *scaler3_cfg, u32 offset) 94 { 95 int i, j, filter; 96 int config_lut = 0x0; 97 unsigned long lut_flags; 98 u32 lut_addr, lut_offset, lut_len; 99 u32 *lut[QSEED3_FILTERS] = {NULL, NULL, NULL, NULL, NULL}; 100 static const uint32_t off_tbl[QSEED3_FILTERS][QSEED3_LUT_REGIONS][2] = { 101 {{18, 0x000}, {12, 0x120}, {12, 0x1E0}, {8, 0x2A0} }, 102 {{6, 0x320}, {3, 0x3E0}, {3, 0x440}, {3, 0x4A0} }, 103 {{6, 0x500}, {3, 0x5c0}, {3, 0x620}, {3, 0x680} }, 104 {{6, 0x380}, {3, 0x410}, {3, 0x470}, {3, 0x4d0} }, 105 {{6, 0x560}, {3, 0x5f0}, {3, 0x650}, {3, 0x6b0} }, 106 }; 107 108 lut_flags = (unsigned long) scaler3_cfg->lut_flag; 109 if (test_bit(QSEED3_COEF_LUT_DIR_BIT, &lut_flags) && 110 (scaler3_cfg->dir_len == QSEED3_DIR_LUT_SIZE)) { 111 lut[0] = scaler3_cfg->dir_lut; 112 config_lut = 1; 113 } 114 if (test_bit(QSEED3_COEF_LUT_Y_CIR_BIT, &lut_flags) && 115 (scaler3_cfg->y_rgb_cir_lut_idx < QSEED3_CIRCULAR_LUTS) && 116 (scaler3_cfg->cir_len == QSEED3_CIR_LUT_SIZE)) { 117 lut[1] = scaler3_cfg->cir_lut + 118 scaler3_cfg->y_rgb_cir_lut_idx * QSEED3_LUT_SIZE; 119 config_lut = 1; 120 } 121 if (test_bit(QSEED3_COEF_LUT_UV_CIR_BIT, &lut_flags) && 122 (scaler3_cfg->uv_cir_lut_idx < QSEED3_CIRCULAR_LUTS) && 123 (scaler3_cfg->cir_len == QSEED3_CIR_LUT_SIZE)) { 124 lut[2] = scaler3_cfg->cir_lut + 125 scaler3_cfg->uv_cir_lut_idx * QSEED3_LUT_SIZE; 126 config_lut = 1; 127 } 128 if (test_bit(QSEED3_COEF_LUT_Y_SEP_BIT, &lut_flags) && 129 (scaler3_cfg->y_rgb_sep_lut_idx < QSEED3_SEPARABLE_LUTS) && 130 (scaler3_cfg->sep_len == QSEED3_SEP_LUT_SIZE)) { 131 lut[3] = scaler3_cfg->sep_lut + 132 scaler3_cfg->y_rgb_sep_lut_idx * QSEED3_LUT_SIZE; 133 config_lut = 1; 134 } 135 if (test_bit(QSEED3_COEF_LUT_UV_SEP_BIT, &lut_flags) && 136 (scaler3_cfg->uv_sep_lut_idx < QSEED3_SEPARABLE_LUTS) && 137 (scaler3_cfg->sep_len == QSEED3_SEP_LUT_SIZE)) { 138 lut[4] = scaler3_cfg->sep_lut + 139 scaler3_cfg->uv_sep_lut_idx * QSEED3_LUT_SIZE; 140 config_lut = 1; 141 } 142 143 if (config_lut) { 144 for (filter = 0; filter < QSEED3_FILTERS; filter++) { 145 if (!lut[filter]) 146 continue; 147 lut_offset = 0; 148 for (i = 0; i < QSEED3_LUT_REGIONS; i++) { 149 lut_addr = QSEED3_COEF_LUT + offset 150 + off_tbl[filter][i][1]; 151 lut_len = off_tbl[filter][i][0] << 2; 152 for (j = 0; j < lut_len; j++) { 153 DPU_REG_WRITE(c, 154 lut_addr, 155 (lut[filter])[lut_offset++]); 156 lut_addr += 4; 157 } 158 } 159 } 160 } 161 162 if (test_bit(QSEED3_COEF_LUT_SWAP_BIT, &lut_flags)) 163 DPU_REG_WRITE(c, QSEED3_COEF_LUT_CTRL + offset, BIT(0)); 164 165 } 166 167 static void _dpu_hw_setup_scaler3_de(struct dpu_hw_blk_reg_map *c, 168 struct dpu_hw_scaler3_de_cfg *de_cfg, u32 offset) 169 { 170 u32 sharp_lvl, sharp_ctl, shape_ctl, de_thr; 171 u32 adjust_a, adjust_b, adjust_c; 172 173 if (!de_cfg->enable) 174 return; 175 176 sharp_lvl = (de_cfg->sharpen_level1 & 0x1FF) | 177 ((de_cfg->sharpen_level2 & 0x1FF) << 16); 178 179 sharp_ctl = ((de_cfg->limit & 0xF) << 9) | 180 ((de_cfg->prec_shift & 0x7) << 13) | 181 ((de_cfg->clip & 0x7) << 16); 182 183 shape_ctl = (de_cfg->thr_quiet & 0xFF) | 184 ((de_cfg->thr_dieout & 0x3FF) << 16); 185 186 de_thr = (de_cfg->thr_low & 0x3FF) | 187 ((de_cfg->thr_high & 0x3FF) << 16); 188 189 adjust_a = (de_cfg->adjust_a[0] & 0x3FF) | 190 ((de_cfg->adjust_a[1] & 0x3FF) << 10) | 191 ((de_cfg->adjust_a[2] & 0x3FF) << 20); 192 193 adjust_b = (de_cfg->adjust_b[0] & 0x3FF) | 194 ((de_cfg->adjust_b[1] & 0x3FF) << 10) | 195 ((de_cfg->adjust_b[2] & 0x3FF) << 20); 196 197 adjust_c = (de_cfg->adjust_c[0] & 0x3FF) | 198 ((de_cfg->adjust_c[1] & 0x3FF) << 10) | 199 ((de_cfg->adjust_c[2] & 0x3FF) << 20); 200 201 DPU_REG_WRITE(c, QSEED3_DE_SHARPEN + offset, sharp_lvl); 202 DPU_REG_WRITE(c, QSEED3_DE_SHARPEN_CTL + offset, sharp_ctl); 203 DPU_REG_WRITE(c, QSEED3_DE_SHAPE_CTL + offset, shape_ctl); 204 DPU_REG_WRITE(c, QSEED3_DE_THRESHOLD + offset, de_thr); 205 DPU_REG_WRITE(c, QSEED3_DE_ADJUST_DATA_0 + offset, adjust_a); 206 DPU_REG_WRITE(c, QSEED3_DE_ADJUST_DATA_1 + offset, adjust_b); 207 DPU_REG_WRITE(c, QSEED3_DE_ADJUST_DATA_2 + offset, adjust_c); 208 209 } 210 211 void dpu_hw_setup_scaler3(struct dpu_hw_blk_reg_map *c, 212 struct dpu_hw_scaler3_cfg *scaler3_cfg, 213 u32 scaler_offset, u32 scaler_version, 214 const struct dpu_format *format) 215 { 216 u32 op_mode = 0; 217 u32 phase_init, preload, src_y_rgb, src_uv, dst; 218 219 if (!scaler3_cfg->enable) 220 goto end; 221 222 op_mode |= BIT(0); 223 op_mode |= (scaler3_cfg->y_rgb_filter_cfg & 0x3) << 16; 224 225 if (format && DPU_FORMAT_IS_YUV(format)) { 226 op_mode |= BIT(12); 227 op_mode |= (scaler3_cfg->uv_filter_cfg & 0x3) << 24; 228 } 229 230 op_mode |= (scaler3_cfg->blend_cfg & 1) << 31; 231 op_mode |= (scaler3_cfg->dir_en) ? BIT(4) : 0; 232 233 preload = 234 ((scaler3_cfg->preload_x[0] & 0x7F) << 0) | 235 ((scaler3_cfg->preload_y[0] & 0x7F) << 8) | 236 ((scaler3_cfg->preload_x[1] & 0x7F) << 16) | 237 ((scaler3_cfg->preload_y[1] & 0x7F) << 24); 238 239 src_y_rgb = (scaler3_cfg->src_width[0] & 0x1FFFF) | 240 ((scaler3_cfg->src_height[0] & 0x1FFFF) << 16); 241 242 src_uv = (scaler3_cfg->src_width[1] & 0x1FFFF) | 243 ((scaler3_cfg->src_height[1] & 0x1FFFF) << 16); 244 245 dst = (scaler3_cfg->dst_width & 0x1FFFF) | 246 ((scaler3_cfg->dst_height & 0x1FFFF) << 16); 247 248 if (scaler3_cfg->de.enable) { 249 _dpu_hw_setup_scaler3_de(c, &scaler3_cfg->de, scaler_offset); 250 op_mode |= BIT(8); 251 } 252 253 if (scaler3_cfg->lut_flag) 254 _dpu_hw_setup_scaler3_lut(c, scaler3_cfg, 255 scaler_offset); 256 257 if (scaler_version == 0x1002) { 258 phase_init = 259 ((scaler3_cfg->init_phase_x[0] & 0x3F) << 0) | 260 ((scaler3_cfg->init_phase_y[0] & 0x3F) << 8) | 261 ((scaler3_cfg->init_phase_x[1] & 0x3F) << 16) | 262 ((scaler3_cfg->init_phase_y[1] & 0x3F) << 24); 263 DPU_REG_WRITE(c, QSEED3_PHASE_INIT + scaler_offset, phase_init); 264 } else { 265 DPU_REG_WRITE(c, QSEED3_PHASE_INIT_Y_H + scaler_offset, 266 scaler3_cfg->init_phase_x[0] & 0x1FFFFF); 267 DPU_REG_WRITE(c, QSEED3_PHASE_INIT_Y_V + scaler_offset, 268 scaler3_cfg->init_phase_y[0] & 0x1FFFFF); 269 DPU_REG_WRITE(c, QSEED3_PHASE_INIT_UV_H + scaler_offset, 270 scaler3_cfg->init_phase_x[1] & 0x1FFFFF); 271 DPU_REG_WRITE(c, QSEED3_PHASE_INIT_UV_V + scaler_offset, 272 scaler3_cfg->init_phase_y[1] & 0x1FFFFF); 273 } 274 275 DPU_REG_WRITE(c, QSEED3_PHASE_STEP_Y_H + scaler_offset, 276 scaler3_cfg->phase_step_x[0] & 0xFFFFFF); 277 278 DPU_REG_WRITE(c, QSEED3_PHASE_STEP_Y_V + scaler_offset, 279 scaler3_cfg->phase_step_y[0] & 0xFFFFFF); 280 281 DPU_REG_WRITE(c, QSEED3_PHASE_STEP_UV_H + scaler_offset, 282 scaler3_cfg->phase_step_x[1] & 0xFFFFFF); 283 284 DPU_REG_WRITE(c, QSEED3_PHASE_STEP_UV_V + scaler_offset, 285 scaler3_cfg->phase_step_y[1] & 0xFFFFFF); 286 287 DPU_REG_WRITE(c, QSEED3_PRELOAD + scaler_offset, preload); 288 289 DPU_REG_WRITE(c, QSEED3_SRC_SIZE_Y_RGB_A + scaler_offset, src_y_rgb); 290 291 DPU_REG_WRITE(c, QSEED3_SRC_SIZE_UV + scaler_offset, src_uv); 292 293 DPU_REG_WRITE(c, QSEED3_DST_SIZE + scaler_offset, dst); 294 295 end: 296 if (format && !DPU_FORMAT_IS_DX(format)) 297 op_mode |= BIT(14); 298 299 if (format && format->alpha_enable) { 300 op_mode |= BIT(10); 301 if (scaler_version == 0x1002) 302 op_mode |= (scaler3_cfg->alpha_filter_cfg & 0x1) << 30; 303 else 304 op_mode |= (scaler3_cfg->alpha_filter_cfg & 0x3) << 29; 305 } 306 307 DPU_REG_WRITE(c, QSEED3_OP_MODE + scaler_offset, op_mode); 308 } 309 310 u32 dpu_hw_get_scaler3_ver(struct dpu_hw_blk_reg_map *c, 311 u32 scaler_offset) 312 { 313 return DPU_REG_READ(c, QSEED3_HW_VERSION + scaler_offset); 314 } 315 316 void dpu_hw_csc_setup(struct dpu_hw_blk_reg_map *c, 317 u32 csc_reg_off, 318 struct dpu_csc_cfg *data, bool csc10) 319 { 320 static const u32 matrix_shift = 7; 321 u32 clamp_shift = csc10 ? 16 : 8; 322 u32 val; 323 324 /* matrix coeff - convert S15.16 to S4.9 */ 325 val = ((data->csc_mv[0] >> matrix_shift) & 0x1FFF) | 326 (((data->csc_mv[1] >> matrix_shift) & 0x1FFF) << 16); 327 DPU_REG_WRITE(c, csc_reg_off, val); 328 val = ((data->csc_mv[2] >> matrix_shift) & 0x1FFF) | 329 (((data->csc_mv[3] >> matrix_shift) & 0x1FFF) << 16); 330 DPU_REG_WRITE(c, csc_reg_off + 0x4, val); 331 val = ((data->csc_mv[4] >> matrix_shift) & 0x1FFF) | 332 (((data->csc_mv[5] >> matrix_shift) & 0x1FFF) << 16); 333 DPU_REG_WRITE(c, csc_reg_off + 0x8, val); 334 val = ((data->csc_mv[6] >> matrix_shift) & 0x1FFF) | 335 (((data->csc_mv[7] >> matrix_shift) & 0x1FFF) << 16); 336 DPU_REG_WRITE(c, csc_reg_off + 0xc, val); 337 val = (data->csc_mv[8] >> matrix_shift) & 0x1FFF; 338 DPU_REG_WRITE(c, csc_reg_off + 0x10, val); 339 340 /* Pre clamp */ 341 val = (data->csc_pre_lv[0] << clamp_shift) | data->csc_pre_lv[1]; 342 DPU_REG_WRITE(c, csc_reg_off + 0x14, val); 343 val = (data->csc_pre_lv[2] << clamp_shift) | data->csc_pre_lv[3]; 344 DPU_REG_WRITE(c, csc_reg_off + 0x18, val); 345 val = (data->csc_pre_lv[4] << clamp_shift) | data->csc_pre_lv[5]; 346 DPU_REG_WRITE(c, csc_reg_off + 0x1c, val); 347 348 /* Post clamp */ 349 val = (data->csc_post_lv[0] << clamp_shift) | data->csc_post_lv[1]; 350 DPU_REG_WRITE(c, csc_reg_off + 0x20, val); 351 val = (data->csc_post_lv[2] << clamp_shift) | data->csc_post_lv[3]; 352 DPU_REG_WRITE(c, csc_reg_off + 0x24, val); 353 val = (data->csc_post_lv[4] << clamp_shift) | data->csc_post_lv[5]; 354 DPU_REG_WRITE(c, csc_reg_off + 0x28, val); 355 356 /* Pre-Bias */ 357 DPU_REG_WRITE(c, csc_reg_off + 0x2c, data->csc_pre_bv[0]); 358 DPU_REG_WRITE(c, csc_reg_off + 0x30, data->csc_pre_bv[1]); 359 DPU_REG_WRITE(c, csc_reg_off + 0x34, data->csc_pre_bv[2]); 360 361 /* Post-Bias */ 362 DPU_REG_WRITE(c, csc_reg_off + 0x38, data->csc_post_bv[0]); 363 DPU_REG_WRITE(c, csc_reg_off + 0x3c, data->csc_post_bv[1]); 364 DPU_REG_WRITE(c, csc_reg_off + 0x40, data->csc_post_bv[2]); 365 } 366