1 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 2 * 3 * This program is free software; you can redistribute it and/or modify 4 * it under the terms of the GNU General Public License version 2 and 5 * only version 2 as published by the Free Software Foundation. 6 * 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 */ 12 13 #ifndef _DPU_HW_TOP_H 14 #define _DPU_HW_TOP_H 15 16 #include "dpu_hw_catalog.h" 17 #include "dpu_hw_mdss.h" 18 #include "dpu_hw_util.h" 19 #include "dpu_hw_blk.h" 20 21 struct dpu_hw_mdp; 22 23 /** 24 * struct traffic_shaper_cfg: traffic shaper configuration 25 * @en : enable/disable traffic shaper 26 * @rd_client : true if read client; false if write client 27 * @client_id : client identifier 28 * @bpc_denom : denominator of byte per clk 29 * @bpc_numer : numerator of byte per clk 30 */ 31 struct traffic_shaper_cfg { 32 bool en; 33 bool rd_client; 34 u32 client_id; 35 u32 bpc_denom; 36 u64 bpc_numer; 37 }; 38 39 /** 40 * struct split_pipe_cfg - pipe configuration for dual display panels 41 * @en : Enable/disable dual pipe confguration 42 * @mode : Panel interface mode 43 * @intf : Interface id for main control path 44 * @split_flush_en: Allows both the paths to be flushed when master path is 45 * flushed 46 */ 47 struct split_pipe_cfg { 48 bool en; 49 enum dpu_intf_mode mode; 50 enum dpu_intf intf; 51 bool split_flush_en; 52 }; 53 54 /** 55 * struct cdm_output_cfg: output configuration for cdm 56 * @intf_en : enable/disable interface output 57 */ 58 struct cdm_output_cfg { 59 bool intf_en; 60 }; 61 62 /** 63 * struct dpu_danger_safe_status: danger and safe status signals 64 * @mdp: top level status 65 * @sspp: source pipe status 66 */ 67 struct dpu_danger_safe_status { 68 u8 mdp; 69 u8 sspp[SSPP_MAX]; 70 }; 71 72 /** 73 * struct dpu_vsync_source_cfg - configure vsync source and configure the 74 * watchdog timers if required. 75 * @pp_count: number of ping pongs active 76 * @frame_rate: Display frame rate 77 * @ppnumber: ping pong index array 78 * @vsync_source: vsync source selection 79 */ 80 struct dpu_vsync_source_cfg { 81 u32 pp_count; 82 u32 frame_rate; 83 u32 ppnumber[PINGPONG_MAX]; 84 u32 vsync_source; 85 }; 86 87 /** 88 * struct dpu_hw_mdp_ops - interface to the MDP TOP Hw driver functions 89 * Assumption is these functions will be called after clocks are enabled. 90 * @setup_split_pipe : Programs the pipe control registers 91 * @setup_pp_split : Programs the pp split control registers 92 * @setup_cdm_output : programs cdm control 93 * @setup_traffic_shaper : programs traffic shaper control 94 */ 95 struct dpu_hw_mdp_ops { 96 /** setup_split_pipe() : Regsiters are not double buffered, thisk 97 * function should be called before timing control enable 98 * @mdp : mdp top context driver 99 * @cfg : upper and lower part of pipe configuration 100 */ 101 void (*setup_split_pipe)(struct dpu_hw_mdp *mdp, 102 struct split_pipe_cfg *p); 103 104 /** 105 * setup_cdm_output() : Setup selection control of the cdm data path 106 * @mdp : mdp top context driver 107 * @cfg : cdm output configuration 108 */ 109 void (*setup_cdm_output)(struct dpu_hw_mdp *mdp, 110 struct cdm_output_cfg *cfg); 111 112 /** 113 * setup_traffic_shaper() : Setup traffic shaper control 114 * @mdp : mdp top context driver 115 * @cfg : traffic shaper configuration 116 */ 117 void (*setup_traffic_shaper)(struct dpu_hw_mdp *mdp, 118 struct traffic_shaper_cfg *cfg); 119 120 /** 121 * setup_clk_force_ctrl - set clock force control 122 * @mdp: mdp top context driver 123 * @clk_ctrl: clock to be controlled 124 * @enable: force on enable 125 * @return: if the clock is forced-on by this function 126 */ 127 bool (*setup_clk_force_ctrl)(struct dpu_hw_mdp *mdp, 128 enum dpu_clk_ctrl_type clk_ctrl, bool enable); 129 130 /** 131 * get_danger_status - get danger status 132 * @mdp: mdp top context driver 133 * @status: Pointer to danger safe status 134 */ 135 void (*get_danger_status)(struct dpu_hw_mdp *mdp, 136 struct dpu_danger_safe_status *status); 137 138 /** 139 * setup_vsync_source - setup vsync source configuration details 140 * @mdp: mdp top context driver 141 * @cfg: vsync source selection configuration 142 */ 143 void (*setup_vsync_source)(struct dpu_hw_mdp *mdp, 144 struct dpu_vsync_source_cfg *cfg); 145 146 /** 147 * get_safe_status - get safe status 148 * @mdp: mdp top context driver 149 * @status: Pointer to danger safe status 150 */ 151 void (*get_safe_status)(struct dpu_hw_mdp *mdp, 152 struct dpu_danger_safe_status *status); 153 154 /** 155 * reset_ubwc - reset top level UBWC configuration 156 * @mdp: mdp top context driver 157 * @m: pointer to mdss catalog data 158 */ 159 void (*reset_ubwc)(struct dpu_hw_mdp *mdp, struct dpu_mdss_cfg *m); 160 161 /** 162 * intf_audio_select - select the external interface for audio 163 * @mdp: mdp top context driver 164 */ 165 void (*intf_audio_select)(struct dpu_hw_mdp *mdp); 166 }; 167 168 struct dpu_hw_mdp { 169 struct dpu_hw_blk base; 170 struct dpu_hw_blk_reg_map hw; 171 172 /* top */ 173 enum dpu_mdp idx; 174 const struct dpu_mdp_cfg *caps; 175 176 /* ops */ 177 struct dpu_hw_mdp_ops ops; 178 }; 179 180 /** 181 * to_dpu_hw_mdp - convert base object dpu_hw_base to container 182 * @hw: Pointer to base hardware block 183 * return: Pointer to hardware block container 184 */ 185 static inline struct dpu_hw_mdp *to_dpu_hw_mdp(struct dpu_hw_blk *hw) 186 { 187 return container_of(hw, struct dpu_hw_mdp, base); 188 } 189 190 /** 191 * dpu_hw_mdptop_init - initializes the top driver for the passed idx 192 * @idx: Interface index for which driver object is required 193 * @addr: Mapped register io address of MDP 194 * @m: Pointer to mdss catalog data 195 */ 196 struct dpu_hw_mdp *dpu_hw_mdptop_init(enum dpu_mdp idx, 197 void __iomem *addr, 198 const struct dpu_mdss_cfg *m); 199 200 void dpu_hw_mdp_destroy(struct dpu_hw_mdp *mdp); 201 202 #endif /*_DPU_HW_TOP_H */ 203