1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 3 */ 4 5 #include "dpu_hwio.h" 6 #include "dpu_hw_catalog.h" 7 #include "dpu_hw_top.h" 8 #include "dpu_kms.h" 9 10 #define FLD_SPLIT_DISPLAY_CMD BIT(1) 11 #define FLD_SMART_PANEL_FREE_RUN BIT(2) 12 #define FLD_INTF_1_SW_TRG_MUX BIT(4) 13 #define FLD_INTF_2_SW_TRG_MUX BIT(8) 14 #define FLD_TE_LINE_INTER_WATERLEVEL_MASK 0xFFFF 15 16 #define TRAFFIC_SHAPER_EN BIT(31) 17 #define TRAFFIC_SHAPER_RD_CLIENT(num) (0x030 + (num * 4)) 18 #define TRAFFIC_SHAPER_WR_CLIENT(num) (0x060 + (num * 4)) 19 #define TRAFFIC_SHAPER_FIXPOINT_FACTOR 4 20 21 #define MDP_TICK_COUNT 16 22 #define XO_CLK_RATE 19200 23 #define MS_TICKS_IN_SEC 1000 24 25 #define CALCULATE_WD_LOAD_VALUE(fps) \ 26 ((uint32_t)((MS_TICKS_IN_SEC * XO_CLK_RATE)/(MDP_TICK_COUNT * fps))) 27 28 static void dpu_hw_setup_split_pipe(struct dpu_hw_mdp *mdp, 29 struct split_pipe_cfg *cfg) 30 { 31 struct dpu_hw_blk_reg_map *c; 32 u32 upper_pipe = 0; 33 u32 lower_pipe = 0; 34 35 if (!mdp || !cfg) 36 return; 37 38 c = &mdp->hw; 39 40 if (cfg->en) { 41 if (cfg->mode == INTF_MODE_CMD) { 42 lower_pipe = FLD_SPLIT_DISPLAY_CMD; 43 /* interface controlling sw trigger */ 44 if (cfg->intf == INTF_2) 45 lower_pipe |= FLD_INTF_1_SW_TRG_MUX; 46 else 47 lower_pipe |= FLD_INTF_2_SW_TRG_MUX; 48 upper_pipe = lower_pipe; 49 } else { 50 if (cfg->intf == INTF_2) { 51 lower_pipe = FLD_INTF_1_SW_TRG_MUX; 52 upper_pipe = FLD_INTF_2_SW_TRG_MUX; 53 } else { 54 lower_pipe = FLD_INTF_2_SW_TRG_MUX; 55 upper_pipe = FLD_INTF_1_SW_TRG_MUX; 56 } 57 } 58 } 59 60 DPU_REG_WRITE(c, SSPP_SPARE, cfg->split_flush_en ? 0x1 : 0x0); 61 DPU_REG_WRITE(c, SPLIT_DISPLAY_LOWER_PIPE_CTRL, lower_pipe); 62 DPU_REG_WRITE(c, SPLIT_DISPLAY_UPPER_PIPE_CTRL, upper_pipe); 63 DPU_REG_WRITE(c, SPLIT_DISPLAY_EN, cfg->en & 0x1); 64 } 65 66 static bool dpu_hw_setup_clk_force_ctrl(struct dpu_hw_mdp *mdp, 67 enum dpu_clk_ctrl_type clk_ctrl, bool enable) 68 { 69 struct dpu_hw_blk_reg_map *c; 70 u32 reg_off, bit_off; 71 u32 reg_val, new_val; 72 bool clk_forced_on; 73 74 if (!mdp) 75 return false; 76 77 c = &mdp->hw; 78 79 if (clk_ctrl <= DPU_CLK_CTRL_NONE || clk_ctrl >= DPU_CLK_CTRL_MAX) 80 return false; 81 82 reg_off = mdp->caps->clk_ctrls[clk_ctrl].reg_off; 83 bit_off = mdp->caps->clk_ctrls[clk_ctrl].bit_off; 84 85 reg_val = DPU_REG_READ(c, reg_off); 86 87 if (enable) 88 new_val = reg_val | BIT(bit_off); 89 else 90 new_val = reg_val & ~BIT(bit_off); 91 92 DPU_REG_WRITE(c, reg_off, new_val); 93 94 clk_forced_on = !(reg_val & BIT(bit_off)); 95 96 return clk_forced_on; 97 } 98 99 100 static void dpu_hw_get_danger_status(struct dpu_hw_mdp *mdp, 101 struct dpu_danger_safe_status *status) 102 { 103 struct dpu_hw_blk_reg_map *c; 104 u32 value; 105 106 if (!mdp || !status) 107 return; 108 109 c = &mdp->hw; 110 111 value = DPU_REG_READ(c, DANGER_STATUS); 112 status->mdp = (value >> 0) & 0x3; 113 status->sspp[SSPP_VIG0] = (value >> 4) & 0x3; 114 status->sspp[SSPP_VIG1] = (value >> 6) & 0x3; 115 status->sspp[SSPP_VIG2] = (value >> 8) & 0x3; 116 status->sspp[SSPP_VIG3] = (value >> 10) & 0x3; 117 status->sspp[SSPP_RGB0] = (value >> 12) & 0x3; 118 status->sspp[SSPP_RGB1] = (value >> 14) & 0x3; 119 status->sspp[SSPP_RGB2] = (value >> 16) & 0x3; 120 status->sspp[SSPP_RGB3] = (value >> 18) & 0x3; 121 status->sspp[SSPP_DMA0] = (value >> 20) & 0x3; 122 status->sspp[SSPP_DMA1] = (value >> 22) & 0x3; 123 status->sspp[SSPP_DMA2] = (value >> 28) & 0x3; 124 status->sspp[SSPP_DMA3] = (value >> 30) & 0x3; 125 status->sspp[SSPP_CURSOR0] = (value >> 24) & 0x3; 126 status->sspp[SSPP_CURSOR1] = (value >> 26) & 0x3; 127 } 128 129 static void dpu_hw_setup_vsync_source(struct dpu_hw_mdp *mdp, 130 struct dpu_vsync_source_cfg *cfg) 131 { 132 struct dpu_hw_blk_reg_map *c; 133 u32 reg, wd_load_value, wd_ctl, wd_ctl2, i; 134 static const u32 pp_offset[PINGPONG_MAX] = {0xC, 0x8, 0x4, 0x13, 0x18}; 135 136 if (!mdp || !cfg || (cfg->pp_count > ARRAY_SIZE(cfg->ppnumber))) 137 return; 138 139 c = &mdp->hw; 140 reg = DPU_REG_READ(c, MDP_VSYNC_SEL); 141 for (i = 0; i < cfg->pp_count; i++) { 142 int pp_idx = cfg->ppnumber[i] - PINGPONG_0; 143 144 if (pp_idx >= ARRAY_SIZE(pp_offset)) 145 continue; 146 147 reg &= ~(0xf << pp_offset[pp_idx]); 148 reg |= (cfg->vsync_source & 0xf) << pp_offset[pp_idx]; 149 } 150 DPU_REG_WRITE(c, MDP_VSYNC_SEL, reg); 151 152 if (cfg->vsync_source >= DPU_VSYNC_SOURCE_WD_TIMER_4 && 153 cfg->vsync_source <= DPU_VSYNC_SOURCE_WD_TIMER_0) { 154 switch (cfg->vsync_source) { 155 case DPU_VSYNC_SOURCE_WD_TIMER_4: 156 wd_load_value = MDP_WD_TIMER_4_LOAD_VALUE; 157 wd_ctl = MDP_WD_TIMER_4_CTL; 158 wd_ctl2 = MDP_WD_TIMER_4_CTL2; 159 break; 160 case DPU_VSYNC_SOURCE_WD_TIMER_3: 161 wd_load_value = MDP_WD_TIMER_3_LOAD_VALUE; 162 wd_ctl = MDP_WD_TIMER_3_CTL; 163 wd_ctl2 = MDP_WD_TIMER_3_CTL2; 164 break; 165 case DPU_VSYNC_SOURCE_WD_TIMER_2: 166 wd_load_value = MDP_WD_TIMER_2_LOAD_VALUE; 167 wd_ctl = MDP_WD_TIMER_2_CTL; 168 wd_ctl2 = MDP_WD_TIMER_2_CTL2; 169 break; 170 case DPU_VSYNC_SOURCE_WD_TIMER_1: 171 wd_load_value = MDP_WD_TIMER_1_LOAD_VALUE; 172 wd_ctl = MDP_WD_TIMER_1_CTL; 173 wd_ctl2 = MDP_WD_TIMER_1_CTL2; 174 break; 175 case DPU_VSYNC_SOURCE_WD_TIMER_0: 176 default: 177 wd_load_value = MDP_WD_TIMER_0_LOAD_VALUE; 178 wd_ctl = MDP_WD_TIMER_0_CTL; 179 wd_ctl2 = MDP_WD_TIMER_0_CTL2; 180 break; 181 } 182 183 DPU_REG_WRITE(c, wd_load_value, 184 CALCULATE_WD_LOAD_VALUE(cfg->frame_rate)); 185 186 DPU_REG_WRITE(c, wd_ctl, BIT(0)); /* clear timer */ 187 reg = DPU_REG_READ(c, wd_ctl2); 188 reg |= BIT(8); /* enable heartbeat timer */ 189 reg |= BIT(0); /* enable WD timer */ 190 DPU_REG_WRITE(c, wd_ctl2, reg); 191 192 /* make sure that timers are enabled/disabled for vsync state */ 193 wmb(); 194 } 195 } 196 197 static void dpu_hw_get_safe_status(struct dpu_hw_mdp *mdp, 198 struct dpu_danger_safe_status *status) 199 { 200 struct dpu_hw_blk_reg_map *c; 201 u32 value; 202 203 if (!mdp || !status) 204 return; 205 206 c = &mdp->hw; 207 208 value = DPU_REG_READ(c, SAFE_STATUS); 209 status->mdp = (value >> 0) & 0x1; 210 status->sspp[SSPP_VIG0] = (value >> 4) & 0x1; 211 status->sspp[SSPP_VIG1] = (value >> 6) & 0x1; 212 status->sspp[SSPP_VIG2] = (value >> 8) & 0x1; 213 status->sspp[SSPP_VIG3] = (value >> 10) & 0x1; 214 status->sspp[SSPP_RGB0] = (value >> 12) & 0x1; 215 status->sspp[SSPP_RGB1] = (value >> 14) & 0x1; 216 status->sspp[SSPP_RGB2] = (value >> 16) & 0x1; 217 status->sspp[SSPP_RGB3] = (value >> 18) & 0x1; 218 status->sspp[SSPP_DMA0] = (value >> 20) & 0x1; 219 status->sspp[SSPP_DMA1] = (value >> 22) & 0x1; 220 status->sspp[SSPP_DMA2] = (value >> 28) & 0x1; 221 status->sspp[SSPP_DMA3] = (value >> 30) & 0x1; 222 status->sspp[SSPP_CURSOR0] = (value >> 24) & 0x1; 223 status->sspp[SSPP_CURSOR1] = (value >> 26) & 0x1; 224 } 225 226 static void dpu_hw_intf_audio_select(struct dpu_hw_mdp *mdp) 227 { 228 struct dpu_hw_blk_reg_map *c; 229 230 if (!mdp) 231 return; 232 233 c = &mdp->hw; 234 235 DPU_REG_WRITE(c, HDMI_DP_CORE_SELECT, 0x1); 236 } 237 238 static void _setup_mdp_ops(struct dpu_hw_mdp_ops *ops, 239 unsigned long cap) 240 { 241 ops->setup_split_pipe = dpu_hw_setup_split_pipe; 242 ops->setup_clk_force_ctrl = dpu_hw_setup_clk_force_ctrl; 243 ops->get_danger_status = dpu_hw_get_danger_status; 244 ops->setup_vsync_source = dpu_hw_setup_vsync_source; 245 ops->get_safe_status = dpu_hw_get_safe_status; 246 247 if (cap & BIT(DPU_MDP_AUDIO_SELECT)) 248 ops->intf_audio_select = dpu_hw_intf_audio_select; 249 } 250 251 static const struct dpu_mdp_cfg *_top_offset(enum dpu_mdp mdp, 252 const struct dpu_mdss_cfg *m, 253 void __iomem *addr, 254 struct dpu_hw_blk_reg_map *b) 255 { 256 int i; 257 258 if (!m || !addr || !b) 259 return ERR_PTR(-EINVAL); 260 261 for (i = 0; i < m->mdp_count; i++) { 262 if (mdp == m->mdp[i].id) { 263 b->blk_addr = addr + m->mdp[i].base; 264 b->log_mask = DPU_DBG_MASK_TOP; 265 return &m->mdp[i]; 266 } 267 } 268 269 return ERR_PTR(-EINVAL); 270 } 271 272 struct dpu_hw_mdp *dpu_hw_mdptop_init(enum dpu_mdp idx, 273 void __iomem *addr, 274 const struct dpu_mdss_cfg *m) 275 { 276 struct dpu_hw_mdp *mdp; 277 const struct dpu_mdp_cfg *cfg; 278 279 if (!addr || !m) 280 return ERR_PTR(-EINVAL); 281 282 mdp = kzalloc(sizeof(*mdp), GFP_KERNEL); 283 if (!mdp) 284 return ERR_PTR(-ENOMEM); 285 286 cfg = _top_offset(idx, m, addr, &mdp->hw); 287 if (IS_ERR_OR_NULL(cfg)) { 288 kfree(mdp); 289 return ERR_PTR(-EINVAL); 290 } 291 292 /* 293 * Assign ops 294 */ 295 mdp->idx = idx; 296 mdp->caps = cfg; 297 _setup_mdp_ops(&mdp->ops, mdp->caps->features); 298 299 return mdp; 300 } 301 302 void dpu_hw_mdp_destroy(struct dpu_hw_mdp *mdp) 303 { 304 kfree(mdp); 305 } 306 307