1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
3  */
4 
5 #ifndef _DPU_HW_SSPP_H
6 #define _DPU_HW_SSPP_H
7 
8 #include "dpu_hw_catalog.h"
9 #include "dpu_hw_mdss.h"
10 #include "dpu_hw_util.h"
11 #include "dpu_formats.h"
12 
13 struct dpu_hw_sspp;
14 
15 /**
16  * Flags
17  */
18 #define DPU_SSPP_FLIP_LR		BIT(0)
19 #define DPU_SSPP_FLIP_UD		BIT(1)
20 #define DPU_SSPP_SOURCE_ROTATED_90	BIT(2)
21 #define DPU_SSPP_ROT_90			BIT(3)
22 #define DPU_SSPP_SOLID_FILL		BIT(4)
23 
24 /**
25  * Define all scaler feature bits in catalog
26  */
27 #define DPU_SSPP_SCALER (BIT(DPU_SSPP_SCALER_RGB) | \
28 			 BIT(DPU_SSPP_SCALER_QSEED2) | \
29 			 BIT(DPU_SSPP_SCALER_QSEED3) | \
30 			 BIT(DPU_SSPP_SCALER_QSEED3LITE) | \
31 			 BIT(DPU_SSPP_SCALER_QSEED4))
32 
33 /*
34  * Define all CSC feature bits in catalog
35  */
36 #define DPU_SSPP_CSC_ANY (BIT(DPU_SSPP_CSC) | \
37 			  BIT(DPU_SSPP_CSC_10BIT))
38 
39 /**
40  * Component indices
41  */
42 enum {
43 	DPU_SSPP_COMP_0,
44 	DPU_SSPP_COMP_1_2,
45 	DPU_SSPP_COMP_2,
46 	DPU_SSPP_COMP_3,
47 
48 	DPU_SSPP_COMP_MAX
49 };
50 
51 /**
52  * DPU_SSPP_RECT_SOLO - multirect disabled
53  * DPU_SSPP_RECT_0 - rect0 of a multirect pipe
54  * DPU_SSPP_RECT_1 - rect1 of a multirect pipe
55  *
56  * Note: HW supports multirect with either RECT0 or
57  * RECT1. Considering no benefit of such configs over
58  * SOLO mode and to keep the plane management simple,
59  * we dont support single rect multirect configs.
60  */
61 enum dpu_sspp_multirect_index {
62 	DPU_SSPP_RECT_SOLO = 0,
63 	DPU_SSPP_RECT_0,
64 	DPU_SSPP_RECT_1,
65 };
66 
67 enum dpu_sspp_multirect_mode {
68 	DPU_SSPP_MULTIRECT_NONE = 0,
69 	DPU_SSPP_MULTIRECT_PARALLEL,
70 	DPU_SSPP_MULTIRECT_TIME_MX,
71 };
72 
73 enum {
74 	DPU_FRAME_LINEAR,
75 	DPU_FRAME_TILE_A4X,
76 	DPU_FRAME_TILE_A5X,
77 };
78 
79 enum dpu_hw_filter {
80 	DPU_SCALE_FILTER_NEAREST = 0,
81 	DPU_SCALE_FILTER_BIL,
82 	DPU_SCALE_FILTER_PCMN,
83 	DPU_SCALE_FILTER_CA,
84 	DPU_SCALE_FILTER_MAX
85 };
86 
87 enum dpu_hw_filter_alpa {
88 	DPU_SCALE_ALPHA_PIXEL_REP,
89 	DPU_SCALE_ALPHA_BIL
90 };
91 
92 enum dpu_hw_filter_yuv {
93 	DPU_SCALE_2D_4X4,
94 	DPU_SCALE_2D_CIR,
95 	DPU_SCALE_1D_SEP,
96 	DPU_SCALE_BIL
97 };
98 
99 struct dpu_hw_sharp_cfg {
100 	u32 strength;
101 	u32 edge_thr;
102 	u32 smooth_thr;
103 	u32 noise_thr;
104 };
105 
106 struct dpu_hw_pixel_ext {
107 	/* scaling factors are enabled for this input layer */
108 	uint8_t enable_pxl_ext;
109 
110 	int init_phase_x[DPU_MAX_PLANES];
111 	int phase_step_x[DPU_MAX_PLANES];
112 	int init_phase_y[DPU_MAX_PLANES];
113 	int phase_step_y[DPU_MAX_PLANES];
114 
115 	/*
116 	 * Number of pixels extension in left, right, top and bottom direction
117 	 * for all color components. This pixel value for each color component
118 	 * should be sum of fetch + repeat pixels.
119 	 */
120 	int num_ext_pxls_left[DPU_MAX_PLANES];
121 	int num_ext_pxls_right[DPU_MAX_PLANES];
122 	int num_ext_pxls_top[DPU_MAX_PLANES];
123 	int num_ext_pxls_btm[DPU_MAX_PLANES];
124 
125 	/*
126 	 * Number of pixels needs to be overfetched in left, right, top and
127 	 * bottom directions from source image for scaling.
128 	 */
129 	int left_ftch[DPU_MAX_PLANES];
130 	int right_ftch[DPU_MAX_PLANES];
131 	int top_ftch[DPU_MAX_PLANES];
132 	int btm_ftch[DPU_MAX_PLANES];
133 
134 	/*
135 	 * Number of pixels needs to be repeated in left, right, top and
136 	 * bottom directions for scaling.
137 	 */
138 	int left_rpt[DPU_MAX_PLANES];
139 	int right_rpt[DPU_MAX_PLANES];
140 	int top_rpt[DPU_MAX_PLANES];
141 	int btm_rpt[DPU_MAX_PLANES];
142 
143 	uint32_t roi_w[DPU_MAX_PLANES];
144 	uint32_t roi_h[DPU_MAX_PLANES];
145 
146 	/*
147 	 * Filter type to be used for scaling in horizontal and vertical
148 	 * directions
149 	 */
150 	enum dpu_hw_filter horz_filter[DPU_MAX_PLANES];
151 	enum dpu_hw_filter vert_filter[DPU_MAX_PLANES];
152 
153 };
154 
155 /**
156  * struct dpu_sw_pipe_cfg : software pipe configuration
157  * @src_rect:  src ROI, caller takes into account the different operations
158  *             such as decimation, flip etc to program this field
159  * @dest_rect: destination ROI.
160  */
161 struct dpu_sw_pipe_cfg {
162 	struct drm_rect src_rect;
163 	struct drm_rect dst_rect;
164 };
165 
166 /**
167  * struct dpu_hw_pipe_ts_cfg - traffic shaper configuration
168  * @size: size to prefill in bytes, or zero to disable
169  * @time: time to prefill in usec, or zero to disable
170  */
171 struct dpu_hw_pipe_ts_cfg {
172 	u64 size;
173 	u64 time;
174 };
175 
176 /**
177  * struct dpu_sw_pipe - software pipe description
178  * @sspp:      backing SSPP pipe
179  * @index:     index of the rectangle of SSPP
180  * @mode:      parallel or time multiplex multirect mode
181  */
182 struct dpu_sw_pipe {
183 	struct dpu_hw_sspp *sspp;
184 	enum dpu_sspp_multirect_index multirect_index;
185 	enum dpu_sspp_multirect_mode multirect_mode;
186 };
187 
188 /**
189  * struct dpu_hw_sspp_ops - interface to the SSPP Hw driver functions
190  * Caller must call the init function to get the pipe context for each pipe
191  * Assumption is these functions will be called after clocks are enabled
192  */
193 struct dpu_hw_sspp_ops {
194 	/**
195 	 * setup_format - setup pixel format cropping rectangle, flip
196 	 * @pipe: Pointer to software pipe context
197 	 * @cfg: Pointer to pipe config structure
198 	 * @flags: Extra flags for format config
199 	 */
200 	void (*setup_format)(struct dpu_sw_pipe *pipe,
201 			     const struct dpu_format *fmt, u32 flags);
202 
203 	/**
204 	 * setup_rects - setup pipe ROI rectangles
205 	 * @pipe: Pointer to software pipe context
206 	 * @cfg: Pointer to pipe config structure
207 	 */
208 	void (*setup_rects)(struct dpu_sw_pipe *pipe,
209 			    struct dpu_sw_pipe_cfg *cfg);
210 
211 	/**
212 	 * setup_pe - setup pipe pixel extension
213 	 * @ctx: Pointer to pipe context
214 	 * @pe_ext: Pointer to pixel ext settings
215 	 */
216 	void (*setup_pe)(struct dpu_hw_sspp *ctx,
217 			struct dpu_hw_pixel_ext *pe_ext);
218 
219 	/**
220 	 * setup_sourceaddress - setup pipe source addresses
221 	 * @pipe: Pointer to software pipe context
222 	 * @layout: format layout information for programming buffer to hardware
223 	 */
224 	void (*setup_sourceaddress)(struct dpu_sw_pipe *ctx,
225 				    struct dpu_hw_fmt_layout *layout);
226 
227 	/**
228 	 * setup_csc - setup color space coversion
229 	 * @ctx: Pointer to pipe context
230 	 * @data: Pointer to config structure
231 	 */
232 	void (*setup_csc)(struct dpu_hw_sspp *ctx, const struct dpu_csc_cfg *data);
233 
234 	/**
235 	 * setup_solidfill - enable/disable colorfill
236 	 * @pipe: Pointer to software pipe context
237 	 * @const_color: Fill color value
238 	 * @flags: Pipe flags
239 	 */
240 	void (*setup_solidfill)(struct dpu_sw_pipe *pipe, u32 color);
241 
242 	/**
243 	 * setup_multirect - setup multirect configuration
244 	 * @pipe: Pointer to software pipe context
245 	 */
246 
247 	void (*setup_multirect)(struct dpu_sw_pipe *pipe);
248 
249 	/**
250 	 * setup_sharpening - setup sharpening
251 	 * @ctx: Pointer to pipe context
252 	 * @cfg: Pointer to config structure
253 	 */
254 	void (*setup_sharpening)(struct dpu_hw_sspp *ctx,
255 			struct dpu_hw_sharp_cfg *cfg);
256 
257 
258 	/**
259 	 * setup_qos_lut - setup QoS LUTs
260 	 * @ctx: Pointer to pipe context
261 	 * @cfg: LUT configuration
262 	 */
263 	void (*setup_qos_lut)(struct dpu_hw_sspp *ctx,
264 			struct dpu_hw_qos_cfg *cfg);
265 
266 	/**
267 	 * setup_qos_ctrl - setup QoS control
268 	 * @ctx: Pointer to pipe context
269 	 * @danger_safe_en: flags controlling enabling of danger/safe QoS/LUT
270 	 */
271 	void (*setup_qos_ctrl)(struct dpu_hw_sspp *ctx,
272 			       bool danger_safe_en);
273 
274 	/**
275 	 * setup_histogram - setup histograms
276 	 * @ctx: Pointer to pipe context
277 	 * @cfg: Pointer to histogram configuration
278 	 */
279 	void (*setup_histogram)(struct dpu_hw_sspp *ctx,
280 			void *cfg);
281 
282 	/**
283 	 * setup_scaler - setup scaler
284 	 * @scaler3_cfg: Pointer to scaler configuration
285 	 * @format: pixel format parameters
286 	 */
287 	void (*setup_scaler)(struct dpu_hw_sspp *ctx,
288 		struct dpu_hw_scaler3_cfg *scaler3_cfg,
289 		const struct dpu_format *format);
290 
291 	/**
292 	 * get_scaler_ver - get scaler h/w version
293 	 * @ctx: Pointer to pipe context
294 	 */
295 	u32 (*get_scaler_ver)(struct dpu_hw_sspp *ctx);
296 
297 	/**
298 	 * setup_cdp - setup client driven prefetch
299 	 * @pipe: Pointer to software pipe context
300 	 * @fmt: format used by the sw pipe
301 	 * @enable: whether the CDP should be enabled for this pipe
302 	 */
303 	void (*setup_cdp)(struct dpu_sw_pipe *pipe,
304 			  const struct dpu_format *fmt,
305 			  bool enable);
306 };
307 
308 /**
309  * struct dpu_hw_sspp - pipe description
310  * @base: hardware block base structure
311  * @hw: block hardware details
312  * @ubwc: UBWC configuration data
313  * @idx: pipe index
314  * @cap: pointer to layer_cfg
315  * @ops: pointer to operations possible for this pipe
316  */
317 struct dpu_hw_sspp {
318 	struct dpu_hw_blk base;
319 	struct dpu_hw_blk_reg_map hw;
320 	const struct dpu_ubwc_cfg *ubwc;
321 
322 	/* Pipe */
323 	enum dpu_sspp idx;
324 	const struct dpu_sspp_cfg *cap;
325 
326 	/* Ops */
327 	struct dpu_hw_sspp_ops ops;
328 };
329 
330 struct dpu_kms;
331 /**
332  * dpu_hw_sspp_init() - Initializes the sspp hw driver object.
333  * Should be called once before accessing every pipe.
334  * @cfg:  Pipe catalog entry for which driver object is required
335  * @addr: Mapped register io address of MDP
336  * @ubwc: UBWC configuration data
337  */
338 struct dpu_hw_sspp *dpu_hw_sspp_init(const struct dpu_sspp_cfg *cfg,
339 		void __iomem *addr, const struct dpu_ubwc_cfg *ubwc);
340 
341 /**
342  * dpu_hw_sspp_destroy(): Destroys SSPP driver context
343  * should be called during Hw pipe cleanup.
344  * @ctx:  Pointer to SSPP driver context returned by dpu_hw_sspp_init
345  */
346 void dpu_hw_sspp_destroy(struct dpu_hw_sspp *ctx);
347 
348 int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pipe, struct dpu_kms *kms,
349 			      struct dentry *entry);
350 
351 #endif /*_DPU_HW_SSPP_H */
352 
353