197fb5e8dSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 225fdd593SJeykumar Sankaran /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 325fdd593SJeykumar Sankaran */ 425fdd593SJeykumar Sankaran 525fdd593SJeykumar Sankaran #ifndef _DPU_HW_SSPP_H 625fdd593SJeykumar Sankaran #define _DPU_HW_SSPP_H 725fdd593SJeykumar Sankaran 825fdd593SJeykumar Sankaran #include "dpu_hw_catalog.h" 925fdd593SJeykumar Sankaran #include "dpu_hw_mdss.h" 1025fdd593SJeykumar Sankaran #include "dpu_hw_util.h" 1125fdd593SJeykumar Sankaran #include "dpu_formats.h" 1225fdd593SJeykumar Sankaran 13b187794eSDmitry Baryshkov struct dpu_hw_sspp; 1425fdd593SJeykumar Sankaran 1525fdd593SJeykumar Sankaran /** 1625fdd593SJeykumar Sankaran * Flags 1725fdd593SJeykumar Sankaran */ 1825fdd593SJeykumar Sankaran #define DPU_SSPP_FLIP_LR BIT(0) 1925fdd593SJeykumar Sankaran #define DPU_SSPP_FLIP_UD BIT(1) 2025fdd593SJeykumar Sankaran #define DPU_SSPP_SOURCE_ROTATED_90 BIT(2) 2125fdd593SJeykumar Sankaran #define DPU_SSPP_ROT_90 BIT(3) 2225fdd593SJeykumar Sankaran #define DPU_SSPP_SOLID_FILL BIT(4) 2325fdd593SJeykumar Sankaran 2425fdd593SJeykumar Sankaran /** 2525fdd593SJeykumar Sankaran * Define all scaler feature bits in catalog 2625fdd593SJeykumar Sankaran */ 271e35e3fcSDmitry Baryshkov #define DPU_SSPP_SCALER (BIT(DPU_SSPP_SCALER_RGB) | \ 281e35e3fcSDmitry Baryshkov BIT(DPU_SSPP_SCALER_QSEED2) | \ 291e35e3fcSDmitry Baryshkov BIT(DPU_SSPP_SCALER_QSEED3) | \ 301e35e3fcSDmitry Baryshkov BIT(DPU_SSPP_SCALER_QSEED3LITE) | \ 311e35e3fcSDmitry Baryshkov BIT(DPU_SSPP_SCALER_QSEED4)) 321e35e3fcSDmitry Baryshkov 331e35e3fcSDmitry Baryshkov /* 341e35e3fcSDmitry Baryshkov * Define all CSC feature bits in catalog 351e35e3fcSDmitry Baryshkov */ 361e35e3fcSDmitry Baryshkov #define DPU_SSPP_CSC_ANY (BIT(DPU_SSPP_CSC) | \ 371e35e3fcSDmitry Baryshkov BIT(DPU_SSPP_CSC_10BIT)) 3825fdd593SJeykumar Sankaran 3925fdd593SJeykumar Sankaran /** 4025fdd593SJeykumar Sankaran * Component indices 4125fdd593SJeykumar Sankaran */ 4225fdd593SJeykumar Sankaran enum { 4325fdd593SJeykumar Sankaran DPU_SSPP_COMP_0, 4425fdd593SJeykumar Sankaran DPU_SSPP_COMP_1_2, 4525fdd593SJeykumar Sankaran DPU_SSPP_COMP_2, 4625fdd593SJeykumar Sankaran DPU_SSPP_COMP_3, 4725fdd593SJeykumar Sankaran 4825fdd593SJeykumar Sankaran DPU_SSPP_COMP_MAX 4925fdd593SJeykumar Sankaran }; 5025fdd593SJeykumar Sankaran 5125fdd593SJeykumar Sankaran /** 5225fdd593SJeykumar Sankaran * DPU_SSPP_RECT_SOLO - multirect disabled 5325fdd593SJeykumar Sankaran * DPU_SSPP_RECT_0 - rect0 of a multirect pipe 5425fdd593SJeykumar Sankaran * DPU_SSPP_RECT_1 - rect1 of a multirect pipe 5525fdd593SJeykumar Sankaran * 5625fdd593SJeykumar Sankaran * Note: HW supports multirect with either RECT0 or 5725fdd593SJeykumar Sankaran * RECT1. Considering no benefit of such configs over 5825fdd593SJeykumar Sankaran * SOLO mode and to keep the plane management simple, 5925fdd593SJeykumar Sankaran * we dont support single rect multirect configs. 6025fdd593SJeykumar Sankaran */ 6125fdd593SJeykumar Sankaran enum dpu_sspp_multirect_index { 6225fdd593SJeykumar Sankaran DPU_SSPP_RECT_SOLO = 0, 6325fdd593SJeykumar Sankaran DPU_SSPP_RECT_0, 6425fdd593SJeykumar Sankaran DPU_SSPP_RECT_1, 6525fdd593SJeykumar Sankaran }; 6625fdd593SJeykumar Sankaran 6725fdd593SJeykumar Sankaran enum dpu_sspp_multirect_mode { 6825fdd593SJeykumar Sankaran DPU_SSPP_MULTIRECT_NONE = 0, 6925fdd593SJeykumar Sankaran DPU_SSPP_MULTIRECT_PARALLEL, 7025fdd593SJeykumar Sankaran DPU_SSPP_MULTIRECT_TIME_MX, 7125fdd593SJeykumar Sankaran }; 7225fdd593SJeykumar Sankaran 7325fdd593SJeykumar Sankaran enum { 7425fdd593SJeykumar Sankaran DPU_FRAME_LINEAR, 7525fdd593SJeykumar Sankaran DPU_FRAME_TILE_A4X, 7625fdd593SJeykumar Sankaran DPU_FRAME_TILE_A5X, 7725fdd593SJeykumar Sankaran }; 7825fdd593SJeykumar Sankaran 7925fdd593SJeykumar Sankaran enum dpu_hw_filter { 8025fdd593SJeykumar Sankaran DPU_SCALE_FILTER_NEAREST = 0, 8125fdd593SJeykumar Sankaran DPU_SCALE_FILTER_BIL, 8225fdd593SJeykumar Sankaran DPU_SCALE_FILTER_PCMN, 8325fdd593SJeykumar Sankaran DPU_SCALE_FILTER_CA, 8425fdd593SJeykumar Sankaran DPU_SCALE_FILTER_MAX 8525fdd593SJeykumar Sankaran }; 8625fdd593SJeykumar Sankaran 8725fdd593SJeykumar Sankaran enum dpu_hw_filter_alpa { 8825fdd593SJeykumar Sankaran DPU_SCALE_ALPHA_PIXEL_REP, 8925fdd593SJeykumar Sankaran DPU_SCALE_ALPHA_BIL 9025fdd593SJeykumar Sankaran }; 9125fdd593SJeykumar Sankaran 9225fdd593SJeykumar Sankaran enum dpu_hw_filter_yuv { 9325fdd593SJeykumar Sankaran DPU_SCALE_2D_4X4, 9425fdd593SJeykumar Sankaran DPU_SCALE_2D_CIR, 9525fdd593SJeykumar Sankaran DPU_SCALE_1D_SEP, 9625fdd593SJeykumar Sankaran DPU_SCALE_BIL 9725fdd593SJeykumar Sankaran }; 9825fdd593SJeykumar Sankaran 9925fdd593SJeykumar Sankaran struct dpu_hw_sharp_cfg { 10025fdd593SJeykumar Sankaran u32 strength; 10125fdd593SJeykumar Sankaran u32 edge_thr; 10225fdd593SJeykumar Sankaran u32 smooth_thr; 10325fdd593SJeykumar Sankaran u32 noise_thr; 10425fdd593SJeykumar Sankaran }; 10525fdd593SJeykumar Sankaran 10625fdd593SJeykumar Sankaran struct dpu_hw_pixel_ext { 10725fdd593SJeykumar Sankaran /* scaling factors are enabled for this input layer */ 10825fdd593SJeykumar Sankaran uint8_t enable_pxl_ext; 10925fdd593SJeykumar Sankaran 11025fdd593SJeykumar Sankaran int init_phase_x[DPU_MAX_PLANES]; 11125fdd593SJeykumar Sankaran int phase_step_x[DPU_MAX_PLANES]; 11225fdd593SJeykumar Sankaran int init_phase_y[DPU_MAX_PLANES]; 11325fdd593SJeykumar Sankaran int phase_step_y[DPU_MAX_PLANES]; 11425fdd593SJeykumar Sankaran 11525fdd593SJeykumar Sankaran /* 11625fdd593SJeykumar Sankaran * Number of pixels extension in left, right, top and bottom direction 11725fdd593SJeykumar Sankaran * for all color components. This pixel value for each color component 11825fdd593SJeykumar Sankaran * should be sum of fetch + repeat pixels. 11925fdd593SJeykumar Sankaran */ 12025fdd593SJeykumar Sankaran int num_ext_pxls_left[DPU_MAX_PLANES]; 12125fdd593SJeykumar Sankaran int num_ext_pxls_right[DPU_MAX_PLANES]; 12225fdd593SJeykumar Sankaran int num_ext_pxls_top[DPU_MAX_PLANES]; 12325fdd593SJeykumar Sankaran int num_ext_pxls_btm[DPU_MAX_PLANES]; 12425fdd593SJeykumar Sankaran 12525fdd593SJeykumar Sankaran /* 12625fdd593SJeykumar Sankaran * Number of pixels needs to be overfetched in left, right, top and 12725fdd593SJeykumar Sankaran * bottom directions from source image for scaling. 12825fdd593SJeykumar Sankaran */ 12925fdd593SJeykumar Sankaran int left_ftch[DPU_MAX_PLANES]; 13025fdd593SJeykumar Sankaran int right_ftch[DPU_MAX_PLANES]; 13125fdd593SJeykumar Sankaran int top_ftch[DPU_MAX_PLANES]; 13225fdd593SJeykumar Sankaran int btm_ftch[DPU_MAX_PLANES]; 13325fdd593SJeykumar Sankaran 13425fdd593SJeykumar Sankaran /* 13525fdd593SJeykumar Sankaran * Number of pixels needs to be repeated in left, right, top and 13625fdd593SJeykumar Sankaran * bottom directions for scaling. 13725fdd593SJeykumar Sankaran */ 13825fdd593SJeykumar Sankaran int left_rpt[DPU_MAX_PLANES]; 13925fdd593SJeykumar Sankaran int right_rpt[DPU_MAX_PLANES]; 14025fdd593SJeykumar Sankaran int top_rpt[DPU_MAX_PLANES]; 14125fdd593SJeykumar Sankaran int btm_rpt[DPU_MAX_PLANES]; 14225fdd593SJeykumar Sankaran 14325fdd593SJeykumar Sankaran uint32_t roi_w[DPU_MAX_PLANES]; 14425fdd593SJeykumar Sankaran uint32_t roi_h[DPU_MAX_PLANES]; 14525fdd593SJeykumar Sankaran 14625fdd593SJeykumar Sankaran /* 14725fdd593SJeykumar Sankaran * Filter type to be used for scaling in horizontal and vertical 14825fdd593SJeykumar Sankaran * directions 14925fdd593SJeykumar Sankaran */ 15025fdd593SJeykumar Sankaran enum dpu_hw_filter horz_filter[DPU_MAX_PLANES]; 15125fdd593SJeykumar Sankaran enum dpu_hw_filter vert_filter[DPU_MAX_PLANES]; 15225fdd593SJeykumar Sankaran 15325fdd593SJeykumar Sankaran }; 15425fdd593SJeykumar Sankaran 15525fdd593SJeykumar Sankaran /** 156b187794eSDmitry Baryshkov * struct dpu_hw_sspp_cfg : SSPP configuration 15725fdd593SJeykumar Sankaran * @src_rect: src ROI, caller takes into account the different operations 15825fdd593SJeykumar Sankaran * such as decimation, flip etc to program this field 15925fdd593SJeykumar Sankaran * @dest_rect: destination ROI. 16025fdd593SJeykumar Sankaran */ 161b187794eSDmitry Baryshkov struct dpu_hw_sspp_cfg { 16225fdd593SJeykumar Sankaran struct drm_rect src_rect; 16325fdd593SJeykumar Sankaran struct drm_rect dst_rect; 16425fdd593SJeykumar Sankaran }; 16525fdd593SJeykumar Sankaran 16625fdd593SJeykumar Sankaran /** 16725fdd593SJeykumar Sankaran * struct dpu_hw_pipe_qos_cfg : Source pipe QoS configuration 16825fdd593SJeykumar Sankaran * @creq_vblank: creq value generated to vbif during vertical blanking 16925fdd593SJeykumar Sankaran * @danger_vblank: danger value generated during vertical blanking 17025fdd593SJeykumar Sankaran * @vblank_en: enable creq_vblank and danger_vblank during vblank 17125fdd593SJeykumar Sankaran * @danger_safe_en: enable danger safe generation 17225fdd593SJeykumar Sankaran */ 17325fdd593SJeykumar Sankaran struct dpu_hw_pipe_qos_cfg { 17425fdd593SJeykumar Sankaran u32 creq_vblank; 17525fdd593SJeykumar Sankaran u32 danger_vblank; 17625fdd593SJeykumar Sankaran bool vblank_en; 17725fdd593SJeykumar Sankaran bool danger_safe_en; 17825fdd593SJeykumar Sankaran }; 17925fdd593SJeykumar Sankaran 18025fdd593SJeykumar Sankaran /** 18125fdd593SJeykumar Sankaran * enum CDP preload ahead address size 18225fdd593SJeykumar Sankaran */ 18325fdd593SJeykumar Sankaran enum { 18425fdd593SJeykumar Sankaran DPU_SSPP_CDP_PRELOAD_AHEAD_32, 18525fdd593SJeykumar Sankaran DPU_SSPP_CDP_PRELOAD_AHEAD_64 18625fdd593SJeykumar Sankaran }; 18725fdd593SJeykumar Sankaran 18825fdd593SJeykumar Sankaran /** 18925fdd593SJeykumar Sankaran * struct dpu_hw_pipe_ts_cfg - traffic shaper configuration 19025fdd593SJeykumar Sankaran * @size: size to prefill in bytes, or zero to disable 19125fdd593SJeykumar Sankaran * @time: time to prefill in usec, or zero to disable 19225fdd593SJeykumar Sankaran */ 19325fdd593SJeykumar Sankaran struct dpu_hw_pipe_ts_cfg { 19425fdd593SJeykumar Sankaran u64 size; 19525fdd593SJeykumar Sankaran u64 time; 19625fdd593SJeykumar Sankaran }; 19725fdd593SJeykumar Sankaran 19825fdd593SJeykumar Sankaran /** 1993cfcd130SDmitry Baryshkov * struct dpu_sw_pipe - software pipe description 2003cfcd130SDmitry Baryshkov * @sspp: backing SSPP pipe 2013cfcd130SDmitry Baryshkov * @index: index of the rectangle of SSPP 2023cfcd130SDmitry Baryshkov * @mode: parallel or time multiplex multirect mode 2033cfcd130SDmitry Baryshkov */ 2043cfcd130SDmitry Baryshkov struct dpu_sw_pipe { 2053cfcd130SDmitry Baryshkov struct dpu_hw_sspp *sspp; 2063cfcd130SDmitry Baryshkov enum dpu_sspp_multirect_index multirect_index; 2073cfcd130SDmitry Baryshkov enum dpu_sspp_multirect_mode multirect_mode; 2083cfcd130SDmitry Baryshkov }; 2093cfcd130SDmitry Baryshkov 2103cfcd130SDmitry Baryshkov /** 21125fdd593SJeykumar Sankaran * struct dpu_hw_sspp_ops - interface to the SSPP Hw driver functions 21225fdd593SJeykumar Sankaran * Caller must call the init function to get the pipe context for each pipe 21325fdd593SJeykumar Sankaran * Assumption is these functions will be called after clocks are enabled 21425fdd593SJeykumar Sankaran */ 21525fdd593SJeykumar Sankaran struct dpu_hw_sspp_ops { 21625fdd593SJeykumar Sankaran /** 21725fdd593SJeykumar Sankaran * setup_format - setup pixel format cropping rectangle, flip 21874fd7fdaSDmitry Baryshkov * @pipe: Pointer to software pipe context 21925fdd593SJeykumar Sankaran * @cfg: Pointer to pipe config structure 22025fdd593SJeykumar Sankaran * @flags: Extra flags for format config 22125fdd593SJeykumar Sankaran */ 22274fd7fdaSDmitry Baryshkov void (*setup_format)(struct dpu_sw_pipe *pipe, 22374fd7fdaSDmitry Baryshkov const struct dpu_format *fmt, u32 flags); 22425fdd593SJeykumar Sankaran 22525fdd593SJeykumar Sankaran /** 22625fdd593SJeykumar Sankaran * setup_rects - setup pipe ROI rectangles 22774fd7fdaSDmitry Baryshkov * @pipe: Pointer to software pipe context 22825fdd593SJeykumar Sankaran * @cfg: Pointer to pipe config structure 22925fdd593SJeykumar Sankaran */ 23074fd7fdaSDmitry Baryshkov void (*setup_rects)(struct dpu_sw_pipe *pipe, 23174fd7fdaSDmitry Baryshkov struct dpu_hw_sspp_cfg *cfg); 23225fdd593SJeykumar Sankaran 23325fdd593SJeykumar Sankaran /** 23425fdd593SJeykumar Sankaran * setup_pe - setup pipe pixel extension 23525fdd593SJeykumar Sankaran * @ctx: Pointer to pipe context 23625fdd593SJeykumar Sankaran * @pe_ext: Pointer to pixel ext settings 23725fdd593SJeykumar Sankaran */ 238b187794eSDmitry Baryshkov void (*setup_pe)(struct dpu_hw_sspp *ctx, 23925fdd593SJeykumar Sankaran struct dpu_hw_pixel_ext *pe_ext); 24025fdd593SJeykumar Sankaran 24125fdd593SJeykumar Sankaran /** 24225fdd593SJeykumar Sankaran * setup_sourceaddress - setup pipe source addresses 24374fd7fdaSDmitry Baryshkov * @pipe: Pointer to software pipe context 244*dfdc94e4SDmitry Baryshkov * @layout: format layout information for programming buffer to hardware 24525fdd593SJeykumar Sankaran */ 24674fd7fdaSDmitry Baryshkov void (*setup_sourceaddress)(struct dpu_sw_pipe *ctx, 247*dfdc94e4SDmitry Baryshkov struct dpu_hw_fmt_layout *layout); 24825fdd593SJeykumar Sankaran 24925fdd593SJeykumar Sankaran /** 25025fdd593SJeykumar Sankaran * setup_csc - setup color space coversion 25125fdd593SJeykumar Sankaran * @ctx: Pointer to pipe context 25225fdd593SJeykumar Sankaran * @data: Pointer to config structure 25325fdd593SJeykumar Sankaran */ 254b187794eSDmitry Baryshkov void (*setup_csc)(struct dpu_hw_sspp *ctx, const struct dpu_csc_cfg *data); 25525fdd593SJeykumar Sankaran 25625fdd593SJeykumar Sankaran /** 25725fdd593SJeykumar Sankaran * setup_solidfill - enable/disable colorfill 25874fd7fdaSDmitry Baryshkov * @pipe: Pointer to software pipe context 25925fdd593SJeykumar Sankaran * @const_color: Fill color value 26025fdd593SJeykumar Sankaran * @flags: Pipe flags 26125fdd593SJeykumar Sankaran */ 26274fd7fdaSDmitry Baryshkov void (*setup_solidfill)(struct dpu_sw_pipe *pipe, u32 color); 26325fdd593SJeykumar Sankaran 26425fdd593SJeykumar Sankaran /** 26525fdd593SJeykumar Sankaran * setup_multirect - setup multirect configuration 26674fd7fdaSDmitry Baryshkov * @pipe: Pointer to software pipe context 26725fdd593SJeykumar Sankaran */ 26825fdd593SJeykumar Sankaran 26974fd7fdaSDmitry Baryshkov void (*setup_multirect)(struct dpu_sw_pipe *pipe); 27025fdd593SJeykumar Sankaran 27125fdd593SJeykumar Sankaran /** 27225fdd593SJeykumar Sankaran * setup_sharpening - setup sharpening 27325fdd593SJeykumar Sankaran * @ctx: Pointer to pipe context 27425fdd593SJeykumar Sankaran * @cfg: Pointer to config structure 27525fdd593SJeykumar Sankaran */ 276b187794eSDmitry Baryshkov void (*setup_sharpening)(struct dpu_hw_sspp *ctx, 27725fdd593SJeykumar Sankaran struct dpu_hw_sharp_cfg *cfg); 27825fdd593SJeykumar Sankaran 27925fdd593SJeykumar Sankaran /** 28025fdd593SJeykumar Sankaran * setup_danger_safe_lut - setup danger safe LUTs 28125fdd593SJeykumar Sankaran * @ctx: Pointer to pipe context 28244aab22dSDmitry Baryshkov * @danger_lut: LUT for generate danger level based on fill level 28344aab22dSDmitry Baryshkov * @safe_lut: LUT for generate safe level based on fill level 28425fdd593SJeykumar Sankaran * 28525fdd593SJeykumar Sankaran */ 286b187794eSDmitry Baryshkov void (*setup_danger_safe_lut)(struct dpu_hw_sspp *ctx, 28744aab22dSDmitry Baryshkov u32 danger_lut, 28844aab22dSDmitry Baryshkov u32 safe_lut); 28925fdd593SJeykumar Sankaran 29025fdd593SJeykumar Sankaran /** 29125fdd593SJeykumar Sankaran * setup_creq_lut - setup CREQ LUT 29225fdd593SJeykumar Sankaran * @ctx: Pointer to pipe context 29344aab22dSDmitry Baryshkov * @creq_lut: LUT for generate creq level based on fill level 29425fdd593SJeykumar Sankaran * 29525fdd593SJeykumar Sankaran */ 296b187794eSDmitry Baryshkov void (*setup_creq_lut)(struct dpu_hw_sspp *ctx, 29744aab22dSDmitry Baryshkov u64 creq_lut); 29825fdd593SJeykumar Sankaran 29925fdd593SJeykumar Sankaran /** 30025fdd593SJeykumar Sankaran * setup_qos_ctrl - setup QoS control 30125fdd593SJeykumar Sankaran * @ctx: Pointer to pipe context 30225fdd593SJeykumar Sankaran * @cfg: Pointer to pipe QoS configuration 30325fdd593SJeykumar Sankaran * 30425fdd593SJeykumar Sankaran */ 305b187794eSDmitry Baryshkov void (*setup_qos_ctrl)(struct dpu_hw_sspp *ctx, 30625fdd593SJeykumar Sankaran struct dpu_hw_pipe_qos_cfg *cfg); 30725fdd593SJeykumar Sankaran 30825fdd593SJeykumar Sankaran /** 30925fdd593SJeykumar Sankaran * setup_histogram - setup histograms 31025fdd593SJeykumar Sankaran * @ctx: Pointer to pipe context 31125fdd593SJeykumar Sankaran * @cfg: Pointer to histogram configuration 31225fdd593SJeykumar Sankaran */ 313b187794eSDmitry Baryshkov void (*setup_histogram)(struct dpu_hw_sspp *ctx, 31425fdd593SJeykumar Sankaran void *cfg); 31525fdd593SJeykumar Sankaran 31625fdd593SJeykumar Sankaran /** 31725fdd593SJeykumar Sankaran * setup_scaler - setup scaler 3186edb12d1SDmitry Baryshkov * @scaler3_cfg: Pointer to scaler configuration 3196edb12d1SDmitry Baryshkov * @format: pixel format parameters 32025fdd593SJeykumar Sankaran */ 321b187794eSDmitry Baryshkov void (*setup_scaler)(struct dpu_hw_sspp *ctx, 3226edb12d1SDmitry Baryshkov struct dpu_hw_scaler3_cfg *scaler3_cfg, 3236edb12d1SDmitry Baryshkov const struct dpu_format *format); 32425fdd593SJeykumar Sankaran 32525fdd593SJeykumar Sankaran /** 32625fdd593SJeykumar Sankaran * get_scaler_ver - get scaler h/w version 32725fdd593SJeykumar Sankaran * @ctx: Pointer to pipe context 32825fdd593SJeykumar Sankaran */ 329b187794eSDmitry Baryshkov u32 (*get_scaler_ver)(struct dpu_hw_sspp *ctx); 33025fdd593SJeykumar Sankaran 33125fdd593SJeykumar Sankaran /** 33225fdd593SJeykumar Sankaran * setup_cdp - setup client driven prefetch 33374fd7fdaSDmitry Baryshkov * @pipe: Pointer to software pipe context 33425fdd593SJeykumar Sankaran * @cfg: Pointer to cdp configuration 33525fdd593SJeykumar Sankaran */ 33674fd7fdaSDmitry Baryshkov void (*setup_cdp)(struct dpu_sw_pipe *pipe, 33774fd7fdaSDmitry Baryshkov struct dpu_hw_cdp_cfg *cfg); 33825fdd593SJeykumar Sankaran }; 33925fdd593SJeykumar Sankaran 34025fdd593SJeykumar Sankaran /** 341b187794eSDmitry Baryshkov * struct dpu_hw_sspp - pipe description 34225fdd593SJeykumar Sankaran * @base: hardware block base structure 34325fdd593SJeykumar Sankaran * @hw: block hardware details 34425fdd593SJeykumar Sankaran * @catalog: back pointer to catalog 34525fdd593SJeykumar Sankaran * @mdp: pointer to associated mdp portion of the catalog 34625fdd593SJeykumar Sankaran * @idx: pipe index 34725fdd593SJeykumar Sankaran * @cap: pointer to layer_cfg 34825fdd593SJeykumar Sankaran * @ops: pointer to operations possible for this pipe 34925fdd593SJeykumar Sankaran */ 350b187794eSDmitry Baryshkov struct dpu_hw_sspp { 35125fdd593SJeykumar Sankaran struct dpu_hw_blk base; 35225fdd593SJeykumar Sankaran struct dpu_hw_blk_reg_map hw; 35332084967SDmitry Baryshkov const struct dpu_mdss_cfg *catalog; 354abda0d92SStephen Boyd const struct dpu_mdp_cfg *mdp; 35525fdd593SJeykumar Sankaran 35625fdd593SJeykumar Sankaran /* Pipe */ 35725fdd593SJeykumar Sankaran enum dpu_sspp idx; 35825fdd593SJeykumar Sankaran const struct dpu_sspp_cfg *cap; 35925fdd593SJeykumar Sankaran 36025fdd593SJeykumar Sankaran /* Ops */ 36125fdd593SJeykumar Sankaran struct dpu_hw_sspp_ops ops; 36225fdd593SJeykumar Sankaran }; 36325fdd593SJeykumar Sankaran 3642672e4e7SDmitry Baryshkov struct dpu_kms; 36525fdd593SJeykumar Sankaran /** 36625fdd593SJeykumar Sankaran * dpu_hw_sspp_init - initializes the sspp hw driver object. 36725fdd593SJeykumar Sankaran * Should be called once before accessing every pipe. 36825fdd593SJeykumar Sankaran * @idx: Pipe index for which driver object is required 36925fdd593SJeykumar Sankaran * @addr: Mapped register io address of MDP 37025fdd593SJeykumar Sankaran * @catalog : Pointer to mdss catalog data 37125fdd593SJeykumar Sankaran */ 372b187794eSDmitry Baryshkov struct dpu_hw_sspp *dpu_hw_sspp_init(enum dpu_sspp idx, 373aabf9220SDmitry Baryshkov void __iomem *addr, const struct dpu_mdss_cfg *catalog); 37425fdd593SJeykumar Sankaran 37525fdd593SJeykumar Sankaran /** 37625fdd593SJeykumar Sankaran * dpu_hw_sspp_destroy(): Destroys SSPP driver context 37725fdd593SJeykumar Sankaran * should be called during Hw pipe cleanup. 37825fdd593SJeykumar Sankaran * @ctx: Pointer to SSPP driver context returned by dpu_hw_sspp_init 37925fdd593SJeykumar Sankaran */ 380b187794eSDmitry Baryshkov void dpu_hw_sspp_destroy(struct dpu_hw_sspp *ctx); 38125fdd593SJeykumar Sankaran 382b187794eSDmitry Baryshkov int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pipe, struct dpu_kms *kms, 383b187794eSDmitry Baryshkov struct dentry *entry); 3842672e4e7SDmitry Baryshkov 38525fdd593SJeykumar Sankaran #endif /*_DPU_HW_SSPP_H */ 38625fdd593SJeykumar Sankaran 387