197fb5e8dSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 225fdd593SJeykumar Sankaran /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 325fdd593SJeykumar Sankaran */ 425fdd593SJeykumar Sankaran 525fdd593SJeykumar Sankaran #ifndef _DPU_HW_SSPP_H 625fdd593SJeykumar Sankaran #define _DPU_HW_SSPP_H 725fdd593SJeykumar Sankaran 825fdd593SJeykumar Sankaran #include "dpu_hw_catalog.h" 925fdd593SJeykumar Sankaran #include "dpu_hw_mdss.h" 1025fdd593SJeykumar Sankaran #include "dpu_hw_util.h" 1125fdd593SJeykumar Sankaran #include "dpu_hw_blk.h" 1225fdd593SJeykumar Sankaran #include "dpu_formats.h" 1325fdd593SJeykumar Sankaran 1425fdd593SJeykumar Sankaran struct dpu_hw_pipe; 1525fdd593SJeykumar Sankaran 1625fdd593SJeykumar Sankaran /** 1725fdd593SJeykumar Sankaran * Flags 1825fdd593SJeykumar Sankaran */ 1925fdd593SJeykumar Sankaran #define DPU_SSPP_FLIP_LR BIT(0) 2025fdd593SJeykumar Sankaran #define DPU_SSPP_FLIP_UD BIT(1) 2125fdd593SJeykumar Sankaran #define DPU_SSPP_SOURCE_ROTATED_90 BIT(2) 2225fdd593SJeykumar Sankaran #define DPU_SSPP_ROT_90 BIT(3) 2325fdd593SJeykumar Sankaran #define DPU_SSPP_SOLID_FILL BIT(4) 2425fdd593SJeykumar Sankaran 2525fdd593SJeykumar Sankaran /** 2625fdd593SJeykumar Sankaran * Define all scaler feature bits in catalog 2725fdd593SJeykumar Sankaran */ 2825fdd593SJeykumar Sankaran #define DPU_SSPP_SCALER ((1UL << DPU_SSPP_SCALER_RGB) | \ 2925fdd593SJeykumar Sankaran (1UL << DPU_SSPP_SCALER_QSEED2) | \ 30b75ab05aSShubhashree Dhar (1UL << DPU_SSPP_SCALER_QSEED3) | \ 31*d21fc5dfSDmitry Baryshkov (1UL << DPU_SSPP_SCALER_QSEED3LITE) | \ 32b75ab05aSShubhashree Dhar (1UL << DPU_SSPP_SCALER_QSEED4)) 3325fdd593SJeykumar Sankaran 3425fdd593SJeykumar Sankaran /** 3525fdd593SJeykumar Sankaran * Component indices 3625fdd593SJeykumar Sankaran */ 3725fdd593SJeykumar Sankaran enum { 3825fdd593SJeykumar Sankaran DPU_SSPP_COMP_0, 3925fdd593SJeykumar Sankaran DPU_SSPP_COMP_1_2, 4025fdd593SJeykumar Sankaran DPU_SSPP_COMP_2, 4125fdd593SJeykumar Sankaran DPU_SSPP_COMP_3, 4225fdd593SJeykumar Sankaran 4325fdd593SJeykumar Sankaran DPU_SSPP_COMP_MAX 4425fdd593SJeykumar Sankaran }; 4525fdd593SJeykumar Sankaran 4625fdd593SJeykumar Sankaran /** 4725fdd593SJeykumar Sankaran * DPU_SSPP_RECT_SOLO - multirect disabled 4825fdd593SJeykumar Sankaran * DPU_SSPP_RECT_0 - rect0 of a multirect pipe 4925fdd593SJeykumar Sankaran * DPU_SSPP_RECT_1 - rect1 of a multirect pipe 5025fdd593SJeykumar Sankaran * 5125fdd593SJeykumar Sankaran * Note: HW supports multirect with either RECT0 or 5225fdd593SJeykumar Sankaran * RECT1. Considering no benefit of such configs over 5325fdd593SJeykumar Sankaran * SOLO mode and to keep the plane management simple, 5425fdd593SJeykumar Sankaran * we dont support single rect multirect configs. 5525fdd593SJeykumar Sankaran */ 5625fdd593SJeykumar Sankaran enum dpu_sspp_multirect_index { 5725fdd593SJeykumar Sankaran DPU_SSPP_RECT_SOLO = 0, 5825fdd593SJeykumar Sankaran DPU_SSPP_RECT_0, 5925fdd593SJeykumar Sankaran DPU_SSPP_RECT_1, 6025fdd593SJeykumar Sankaran }; 6125fdd593SJeykumar Sankaran 6225fdd593SJeykumar Sankaran enum dpu_sspp_multirect_mode { 6325fdd593SJeykumar Sankaran DPU_SSPP_MULTIRECT_NONE = 0, 6425fdd593SJeykumar Sankaran DPU_SSPP_MULTIRECT_PARALLEL, 6525fdd593SJeykumar Sankaran DPU_SSPP_MULTIRECT_TIME_MX, 6625fdd593SJeykumar Sankaran }; 6725fdd593SJeykumar Sankaran 6825fdd593SJeykumar Sankaran enum { 6925fdd593SJeykumar Sankaran DPU_FRAME_LINEAR, 7025fdd593SJeykumar Sankaran DPU_FRAME_TILE_A4X, 7125fdd593SJeykumar Sankaran DPU_FRAME_TILE_A5X, 7225fdd593SJeykumar Sankaran }; 7325fdd593SJeykumar Sankaran 7425fdd593SJeykumar Sankaran enum dpu_hw_filter { 7525fdd593SJeykumar Sankaran DPU_SCALE_FILTER_NEAREST = 0, 7625fdd593SJeykumar Sankaran DPU_SCALE_FILTER_BIL, 7725fdd593SJeykumar Sankaran DPU_SCALE_FILTER_PCMN, 7825fdd593SJeykumar Sankaran DPU_SCALE_FILTER_CA, 7925fdd593SJeykumar Sankaran DPU_SCALE_FILTER_MAX 8025fdd593SJeykumar Sankaran }; 8125fdd593SJeykumar Sankaran 8225fdd593SJeykumar Sankaran enum dpu_hw_filter_alpa { 8325fdd593SJeykumar Sankaran DPU_SCALE_ALPHA_PIXEL_REP, 8425fdd593SJeykumar Sankaran DPU_SCALE_ALPHA_BIL 8525fdd593SJeykumar Sankaran }; 8625fdd593SJeykumar Sankaran 8725fdd593SJeykumar Sankaran enum dpu_hw_filter_yuv { 8825fdd593SJeykumar Sankaran DPU_SCALE_2D_4X4, 8925fdd593SJeykumar Sankaran DPU_SCALE_2D_CIR, 9025fdd593SJeykumar Sankaran DPU_SCALE_1D_SEP, 9125fdd593SJeykumar Sankaran DPU_SCALE_BIL 9225fdd593SJeykumar Sankaran }; 9325fdd593SJeykumar Sankaran 9425fdd593SJeykumar Sankaran struct dpu_hw_sharp_cfg { 9525fdd593SJeykumar Sankaran u32 strength; 9625fdd593SJeykumar Sankaran u32 edge_thr; 9725fdd593SJeykumar Sankaran u32 smooth_thr; 9825fdd593SJeykumar Sankaran u32 noise_thr; 9925fdd593SJeykumar Sankaran }; 10025fdd593SJeykumar Sankaran 10125fdd593SJeykumar Sankaran struct dpu_hw_pixel_ext { 10225fdd593SJeykumar Sankaran /* scaling factors are enabled for this input layer */ 10325fdd593SJeykumar Sankaran uint8_t enable_pxl_ext; 10425fdd593SJeykumar Sankaran 10525fdd593SJeykumar Sankaran int init_phase_x[DPU_MAX_PLANES]; 10625fdd593SJeykumar Sankaran int phase_step_x[DPU_MAX_PLANES]; 10725fdd593SJeykumar Sankaran int init_phase_y[DPU_MAX_PLANES]; 10825fdd593SJeykumar Sankaran int phase_step_y[DPU_MAX_PLANES]; 10925fdd593SJeykumar Sankaran 11025fdd593SJeykumar Sankaran /* 11125fdd593SJeykumar Sankaran * Number of pixels extension in left, right, top and bottom direction 11225fdd593SJeykumar Sankaran * for all color components. This pixel value for each color component 11325fdd593SJeykumar Sankaran * should be sum of fetch + repeat pixels. 11425fdd593SJeykumar Sankaran */ 11525fdd593SJeykumar Sankaran int num_ext_pxls_left[DPU_MAX_PLANES]; 11625fdd593SJeykumar Sankaran int num_ext_pxls_right[DPU_MAX_PLANES]; 11725fdd593SJeykumar Sankaran int num_ext_pxls_top[DPU_MAX_PLANES]; 11825fdd593SJeykumar Sankaran int num_ext_pxls_btm[DPU_MAX_PLANES]; 11925fdd593SJeykumar Sankaran 12025fdd593SJeykumar Sankaran /* 12125fdd593SJeykumar Sankaran * Number of pixels needs to be overfetched in left, right, top and 12225fdd593SJeykumar Sankaran * bottom directions from source image for scaling. 12325fdd593SJeykumar Sankaran */ 12425fdd593SJeykumar Sankaran int left_ftch[DPU_MAX_PLANES]; 12525fdd593SJeykumar Sankaran int right_ftch[DPU_MAX_PLANES]; 12625fdd593SJeykumar Sankaran int top_ftch[DPU_MAX_PLANES]; 12725fdd593SJeykumar Sankaran int btm_ftch[DPU_MAX_PLANES]; 12825fdd593SJeykumar Sankaran 12925fdd593SJeykumar Sankaran /* 13025fdd593SJeykumar Sankaran * Number of pixels needs to be repeated in left, right, top and 13125fdd593SJeykumar Sankaran * bottom directions for scaling. 13225fdd593SJeykumar Sankaran */ 13325fdd593SJeykumar Sankaran int left_rpt[DPU_MAX_PLANES]; 13425fdd593SJeykumar Sankaran int right_rpt[DPU_MAX_PLANES]; 13525fdd593SJeykumar Sankaran int top_rpt[DPU_MAX_PLANES]; 13625fdd593SJeykumar Sankaran int btm_rpt[DPU_MAX_PLANES]; 13725fdd593SJeykumar Sankaran 13825fdd593SJeykumar Sankaran uint32_t roi_w[DPU_MAX_PLANES]; 13925fdd593SJeykumar Sankaran uint32_t roi_h[DPU_MAX_PLANES]; 14025fdd593SJeykumar Sankaran 14125fdd593SJeykumar Sankaran /* 14225fdd593SJeykumar Sankaran * Filter type to be used for scaling in horizontal and vertical 14325fdd593SJeykumar Sankaran * directions 14425fdd593SJeykumar Sankaran */ 14525fdd593SJeykumar Sankaran enum dpu_hw_filter horz_filter[DPU_MAX_PLANES]; 14625fdd593SJeykumar Sankaran enum dpu_hw_filter vert_filter[DPU_MAX_PLANES]; 14725fdd593SJeykumar Sankaran 14825fdd593SJeykumar Sankaran }; 14925fdd593SJeykumar Sankaran 15025fdd593SJeykumar Sankaran /** 15125fdd593SJeykumar Sankaran * struct dpu_hw_pipe_cfg : Pipe description 15225fdd593SJeykumar Sankaran * @layout: format layout information for programming buffer to hardware 15325fdd593SJeykumar Sankaran * @src_rect: src ROI, caller takes into account the different operations 15425fdd593SJeykumar Sankaran * such as decimation, flip etc to program this field 15525fdd593SJeykumar Sankaran * @dest_rect: destination ROI. 15625fdd593SJeykumar Sankaran * @index: index of the rectangle of SSPP 15725fdd593SJeykumar Sankaran * @mode: parallel or time multiplex multirect mode 15825fdd593SJeykumar Sankaran */ 15925fdd593SJeykumar Sankaran struct dpu_hw_pipe_cfg { 16025fdd593SJeykumar Sankaran struct dpu_hw_fmt_layout layout; 16125fdd593SJeykumar Sankaran struct drm_rect src_rect; 16225fdd593SJeykumar Sankaran struct drm_rect dst_rect; 16325fdd593SJeykumar Sankaran enum dpu_sspp_multirect_index index; 16425fdd593SJeykumar Sankaran enum dpu_sspp_multirect_mode mode; 16525fdd593SJeykumar Sankaran }; 16625fdd593SJeykumar Sankaran 16725fdd593SJeykumar Sankaran /** 16825fdd593SJeykumar Sankaran * struct dpu_hw_pipe_qos_cfg : Source pipe QoS configuration 16925fdd593SJeykumar Sankaran * @danger_lut: LUT for generate danger level based on fill level 17025fdd593SJeykumar Sankaran * @safe_lut: LUT for generate safe level based on fill level 17125fdd593SJeykumar Sankaran * @creq_lut: LUT for generate creq level based on fill level 17225fdd593SJeykumar Sankaran * @creq_vblank: creq value generated to vbif during vertical blanking 17325fdd593SJeykumar Sankaran * @danger_vblank: danger value generated during vertical blanking 17425fdd593SJeykumar Sankaran * @vblank_en: enable creq_vblank and danger_vblank during vblank 17525fdd593SJeykumar Sankaran * @danger_safe_en: enable danger safe generation 17625fdd593SJeykumar Sankaran */ 17725fdd593SJeykumar Sankaran struct dpu_hw_pipe_qos_cfg { 17825fdd593SJeykumar Sankaran u32 danger_lut; 17925fdd593SJeykumar Sankaran u32 safe_lut; 18025fdd593SJeykumar Sankaran u64 creq_lut; 18125fdd593SJeykumar Sankaran u32 creq_vblank; 18225fdd593SJeykumar Sankaran u32 danger_vblank; 18325fdd593SJeykumar Sankaran bool vblank_en; 18425fdd593SJeykumar Sankaran bool danger_safe_en; 18525fdd593SJeykumar Sankaran }; 18625fdd593SJeykumar Sankaran 18725fdd593SJeykumar Sankaran /** 18825fdd593SJeykumar Sankaran * enum CDP preload ahead address size 18925fdd593SJeykumar Sankaran */ 19025fdd593SJeykumar Sankaran enum { 19125fdd593SJeykumar Sankaran DPU_SSPP_CDP_PRELOAD_AHEAD_32, 19225fdd593SJeykumar Sankaran DPU_SSPP_CDP_PRELOAD_AHEAD_64 19325fdd593SJeykumar Sankaran }; 19425fdd593SJeykumar Sankaran 19525fdd593SJeykumar Sankaran /** 19625fdd593SJeykumar Sankaran * struct dpu_hw_pipe_cdp_cfg : CDP configuration 19725fdd593SJeykumar Sankaran * @enable: true to enable CDP 19825fdd593SJeykumar Sankaran * @ubwc_meta_enable: true to enable ubwc metadata preload 19925fdd593SJeykumar Sankaran * @tile_amortize_enable: true to enable amortization control for tile format 20025fdd593SJeykumar Sankaran * @preload_ahead: number of request to preload ahead 20125fdd593SJeykumar Sankaran * DPU_SSPP_CDP_PRELOAD_AHEAD_32, 20225fdd593SJeykumar Sankaran * DPU_SSPP_CDP_PRELOAD_AHEAD_64 20325fdd593SJeykumar Sankaran */ 20425fdd593SJeykumar Sankaran struct dpu_hw_pipe_cdp_cfg { 20525fdd593SJeykumar Sankaran bool enable; 20625fdd593SJeykumar Sankaran bool ubwc_meta_enable; 20725fdd593SJeykumar Sankaran bool tile_amortize_enable; 20825fdd593SJeykumar Sankaran u32 preload_ahead; 20925fdd593SJeykumar Sankaran }; 21025fdd593SJeykumar Sankaran 21125fdd593SJeykumar Sankaran /** 21225fdd593SJeykumar Sankaran * struct dpu_hw_pipe_ts_cfg - traffic shaper configuration 21325fdd593SJeykumar Sankaran * @size: size to prefill in bytes, or zero to disable 21425fdd593SJeykumar Sankaran * @time: time to prefill in usec, or zero to disable 21525fdd593SJeykumar Sankaran */ 21625fdd593SJeykumar Sankaran struct dpu_hw_pipe_ts_cfg { 21725fdd593SJeykumar Sankaran u64 size; 21825fdd593SJeykumar Sankaran u64 time; 21925fdd593SJeykumar Sankaran }; 22025fdd593SJeykumar Sankaran 22125fdd593SJeykumar Sankaran /** 22225fdd593SJeykumar Sankaran * struct dpu_hw_sspp_ops - interface to the SSPP Hw driver functions 22325fdd593SJeykumar Sankaran * Caller must call the init function to get the pipe context for each pipe 22425fdd593SJeykumar Sankaran * Assumption is these functions will be called after clocks are enabled 22525fdd593SJeykumar Sankaran */ 22625fdd593SJeykumar Sankaran struct dpu_hw_sspp_ops { 22725fdd593SJeykumar Sankaran /** 22825fdd593SJeykumar Sankaran * setup_format - setup pixel format cropping rectangle, flip 22925fdd593SJeykumar Sankaran * @ctx: Pointer to pipe context 23025fdd593SJeykumar Sankaran * @cfg: Pointer to pipe config structure 23125fdd593SJeykumar Sankaran * @flags: Extra flags for format config 23225fdd593SJeykumar Sankaran * @index: rectangle index in multirect 23325fdd593SJeykumar Sankaran */ 23425fdd593SJeykumar Sankaran void (*setup_format)(struct dpu_hw_pipe *ctx, 23525fdd593SJeykumar Sankaran const struct dpu_format *fmt, u32 flags, 23625fdd593SJeykumar Sankaran enum dpu_sspp_multirect_index index); 23725fdd593SJeykumar Sankaran 23825fdd593SJeykumar Sankaran /** 23925fdd593SJeykumar Sankaran * setup_rects - setup pipe ROI rectangles 24025fdd593SJeykumar Sankaran * @ctx: Pointer to pipe context 24125fdd593SJeykumar Sankaran * @cfg: Pointer to pipe config structure 24225fdd593SJeykumar Sankaran * @index: rectangle index in multirect 24325fdd593SJeykumar Sankaran */ 24425fdd593SJeykumar Sankaran void (*setup_rects)(struct dpu_hw_pipe *ctx, 24525fdd593SJeykumar Sankaran struct dpu_hw_pipe_cfg *cfg, 24625fdd593SJeykumar Sankaran enum dpu_sspp_multirect_index index); 24725fdd593SJeykumar Sankaran 24825fdd593SJeykumar Sankaran /** 24925fdd593SJeykumar Sankaran * setup_pe - setup pipe pixel extension 25025fdd593SJeykumar Sankaran * @ctx: Pointer to pipe context 25125fdd593SJeykumar Sankaran * @pe_ext: Pointer to pixel ext settings 25225fdd593SJeykumar Sankaran */ 25325fdd593SJeykumar Sankaran void (*setup_pe)(struct dpu_hw_pipe *ctx, 25425fdd593SJeykumar Sankaran struct dpu_hw_pixel_ext *pe_ext); 25525fdd593SJeykumar Sankaran 25625fdd593SJeykumar Sankaran /** 25725fdd593SJeykumar Sankaran * setup_sourceaddress - setup pipe source addresses 25825fdd593SJeykumar Sankaran * @ctx: Pointer to pipe context 25925fdd593SJeykumar Sankaran * @cfg: Pointer to pipe config structure 26025fdd593SJeykumar Sankaran * @index: rectangle index in multirect 26125fdd593SJeykumar Sankaran */ 26225fdd593SJeykumar Sankaran void (*setup_sourceaddress)(struct dpu_hw_pipe *ctx, 26325fdd593SJeykumar Sankaran struct dpu_hw_pipe_cfg *cfg, 26425fdd593SJeykumar Sankaran enum dpu_sspp_multirect_index index); 26525fdd593SJeykumar Sankaran 26625fdd593SJeykumar Sankaran /** 26725fdd593SJeykumar Sankaran * setup_csc - setup color space coversion 26825fdd593SJeykumar Sankaran * @ctx: Pointer to pipe context 26925fdd593SJeykumar Sankaran * @data: Pointer to config structure 27025fdd593SJeykumar Sankaran */ 27125fdd593SJeykumar Sankaran void (*setup_csc)(struct dpu_hw_pipe *ctx, struct dpu_csc_cfg *data); 27225fdd593SJeykumar Sankaran 27325fdd593SJeykumar Sankaran /** 27425fdd593SJeykumar Sankaran * setup_solidfill - enable/disable colorfill 27525fdd593SJeykumar Sankaran * @ctx: Pointer to pipe context 27625fdd593SJeykumar Sankaran * @const_color: Fill color value 27725fdd593SJeykumar Sankaran * @flags: Pipe flags 27825fdd593SJeykumar Sankaran * @index: rectangle index in multirect 27925fdd593SJeykumar Sankaran */ 28025fdd593SJeykumar Sankaran void (*setup_solidfill)(struct dpu_hw_pipe *ctx, u32 color, 28125fdd593SJeykumar Sankaran enum dpu_sspp_multirect_index index); 28225fdd593SJeykumar Sankaran 28325fdd593SJeykumar Sankaran /** 28425fdd593SJeykumar Sankaran * setup_multirect - setup multirect configuration 28525fdd593SJeykumar Sankaran * @ctx: Pointer to pipe context 28625fdd593SJeykumar Sankaran * @index: rectangle index in multirect 28725fdd593SJeykumar Sankaran * @mode: parallel fetch / time multiplex multirect mode 28825fdd593SJeykumar Sankaran */ 28925fdd593SJeykumar Sankaran 29025fdd593SJeykumar Sankaran void (*setup_multirect)(struct dpu_hw_pipe *ctx, 29125fdd593SJeykumar Sankaran enum dpu_sspp_multirect_index index, 29225fdd593SJeykumar Sankaran enum dpu_sspp_multirect_mode mode); 29325fdd593SJeykumar Sankaran 29425fdd593SJeykumar Sankaran /** 29525fdd593SJeykumar Sankaran * setup_sharpening - setup sharpening 29625fdd593SJeykumar Sankaran * @ctx: Pointer to pipe context 29725fdd593SJeykumar Sankaran * @cfg: Pointer to config structure 29825fdd593SJeykumar Sankaran */ 29925fdd593SJeykumar Sankaran void (*setup_sharpening)(struct dpu_hw_pipe *ctx, 30025fdd593SJeykumar Sankaran struct dpu_hw_sharp_cfg *cfg); 30125fdd593SJeykumar Sankaran 30225fdd593SJeykumar Sankaran /** 30325fdd593SJeykumar Sankaran * setup_danger_safe_lut - setup danger safe LUTs 30425fdd593SJeykumar Sankaran * @ctx: Pointer to pipe context 30525fdd593SJeykumar Sankaran * @cfg: Pointer to pipe QoS configuration 30625fdd593SJeykumar Sankaran * 30725fdd593SJeykumar Sankaran */ 30825fdd593SJeykumar Sankaran void (*setup_danger_safe_lut)(struct dpu_hw_pipe *ctx, 30925fdd593SJeykumar Sankaran struct dpu_hw_pipe_qos_cfg *cfg); 31025fdd593SJeykumar Sankaran 31125fdd593SJeykumar Sankaran /** 31225fdd593SJeykumar Sankaran * setup_creq_lut - setup CREQ LUT 31325fdd593SJeykumar Sankaran * @ctx: Pointer to pipe context 31425fdd593SJeykumar Sankaran * @cfg: Pointer to pipe QoS configuration 31525fdd593SJeykumar Sankaran * 31625fdd593SJeykumar Sankaran */ 31725fdd593SJeykumar Sankaran void (*setup_creq_lut)(struct dpu_hw_pipe *ctx, 31825fdd593SJeykumar Sankaran struct dpu_hw_pipe_qos_cfg *cfg); 31925fdd593SJeykumar Sankaran 32025fdd593SJeykumar Sankaran /** 32125fdd593SJeykumar Sankaran * setup_qos_ctrl - setup QoS control 32225fdd593SJeykumar Sankaran * @ctx: Pointer to pipe context 32325fdd593SJeykumar Sankaran * @cfg: Pointer to pipe QoS configuration 32425fdd593SJeykumar Sankaran * 32525fdd593SJeykumar Sankaran */ 32625fdd593SJeykumar Sankaran void (*setup_qos_ctrl)(struct dpu_hw_pipe *ctx, 32725fdd593SJeykumar Sankaran struct dpu_hw_pipe_qos_cfg *cfg); 32825fdd593SJeykumar Sankaran 32925fdd593SJeykumar Sankaran /** 33025fdd593SJeykumar Sankaran * setup_histogram - setup histograms 33125fdd593SJeykumar Sankaran * @ctx: Pointer to pipe context 33225fdd593SJeykumar Sankaran * @cfg: Pointer to histogram configuration 33325fdd593SJeykumar Sankaran */ 33425fdd593SJeykumar Sankaran void (*setup_histogram)(struct dpu_hw_pipe *ctx, 33525fdd593SJeykumar Sankaran void *cfg); 33625fdd593SJeykumar Sankaran 33725fdd593SJeykumar Sankaran /** 33825fdd593SJeykumar Sankaran * setup_scaler - setup scaler 33925fdd593SJeykumar Sankaran * @ctx: Pointer to pipe context 34025fdd593SJeykumar Sankaran * @pipe_cfg: Pointer to pipe configuration 34125fdd593SJeykumar Sankaran * @pe_cfg: Pointer to pixel extension configuration 34225fdd593SJeykumar Sankaran * @scaler_cfg: Pointer to scaler configuration 34325fdd593SJeykumar Sankaran */ 34425fdd593SJeykumar Sankaran void (*setup_scaler)(struct dpu_hw_pipe *ctx, 34525fdd593SJeykumar Sankaran struct dpu_hw_pipe_cfg *pipe_cfg, 34625fdd593SJeykumar Sankaran struct dpu_hw_pixel_ext *pe_cfg, 34725fdd593SJeykumar Sankaran void *scaler_cfg); 34825fdd593SJeykumar Sankaran 34925fdd593SJeykumar Sankaran /** 35025fdd593SJeykumar Sankaran * get_scaler_ver - get scaler h/w version 35125fdd593SJeykumar Sankaran * @ctx: Pointer to pipe context 35225fdd593SJeykumar Sankaran */ 35325fdd593SJeykumar Sankaran u32 (*get_scaler_ver)(struct dpu_hw_pipe *ctx); 35425fdd593SJeykumar Sankaran 35525fdd593SJeykumar Sankaran /** 35625fdd593SJeykumar Sankaran * setup_cdp - setup client driven prefetch 35725fdd593SJeykumar Sankaran * @ctx: Pointer to pipe context 35825fdd593SJeykumar Sankaran * @cfg: Pointer to cdp configuration 35925fdd593SJeykumar Sankaran */ 36025fdd593SJeykumar Sankaran void (*setup_cdp)(struct dpu_hw_pipe *ctx, 36125fdd593SJeykumar Sankaran struct dpu_hw_pipe_cdp_cfg *cfg); 36225fdd593SJeykumar Sankaran }; 36325fdd593SJeykumar Sankaran 36425fdd593SJeykumar Sankaran /** 36525fdd593SJeykumar Sankaran * struct dpu_hw_pipe - pipe description 36625fdd593SJeykumar Sankaran * @base: hardware block base structure 36725fdd593SJeykumar Sankaran * @hw: block hardware details 36825fdd593SJeykumar Sankaran * @catalog: back pointer to catalog 36925fdd593SJeykumar Sankaran * @mdp: pointer to associated mdp portion of the catalog 37025fdd593SJeykumar Sankaran * @idx: pipe index 37125fdd593SJeykumar Sankaran * @cap: pointer to layer_cfg 37225fdd593SJeykumar Sankaran * @ops: pointer to operations possible for this pipe 37325fdd593SJeykumar Sankaran */ 37425fdd593SJeykumar Sankaran struct dpu_hw_pipe { 37525fdd593SJeykumar Sankaran struct dpu_hw_blk base; 37625fdd593SJeykumar Sankaran struct dpu_hw_blk_reg_map hw; 37725fdd593SJeykumar Sankaran struct dpu_mdss_cfg *catalog; 378abda0d92SStephen Boyd const struct dpu_mdp_cfg *mdp; 37925fdd593SJeykumar Sankaran 38025fdd593SJeykumar Sankaran /* Pipe */ 38125fdd593SJeykumar Sankaran enum dpu_sspp idx; 38225fdd593SJeykumar Sankaran const struct dpu_sspp_cfg *cap; 38325fdd593SJeykumar Sankaran 38425fdd593SJeykumar Sankaran /* Ops */ 38525fdd593SJeykumar Sankaran struct dpu_hw_sspp_ops ops; 38625fdd593SJeykumar Sankaran }; 38725fdd593SJeykumar Sankaran 38825fdd593SJeykumar Sankaran /** 38925fdd593SJeykumar Sankaran * dpu_hw_sspp_init - initializes the sspp hw driver object. 39025fdd593SJeykumar Sankaran * Should be called once before accessing every pipe. 39125fdd593SJeykumar Sankaran * @idx: Pipe index for which driver object is required 39225fdd593SJeykumar Sankaran * @addr: Mapped register io address of MDP 39325fdd593SJeykumar Sankaran * @catalog : Pointer to mdss catalog data 39425fdd593SJeykumar Sankaran * @is_virtual_pipe: is this pipe virtual pipe 39525fdd593SJeykumar Sankaran */ 39625fdd593SJeykumar Sankaran struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx, 39725fdd593SJeykumar Sankaran void __iomem *addr, struct dpu_mdss_cfg *catalog, 39825fdd593SJeykumar Sankaran bool is_virtual_pipe); 39925fdd593SJeykumar Sankaran 40025fdd593SJeykumar Sankaran /** 40125fdd593SJeykumar Sankaran * dpu_hw_sspp_destroy(): Destroys SSPP driver context 40225fdd593SJeykumar Sankaran * should be called during Hw pipe cleanup. 40325fdd593SJeykumar Sankaran * @ctx: Pointer to SSPP driver context returned by dpu_hw_sspp_init 40425fdd593SJeykumar Sankaran */ 40525fdd593SJeykumar Sankaran void dpu_hw_sspp_destroy(struct dpu_hw_pipe *ctx); 40625fdd593SJeykumar Sankaran 40725fdd593SJeykumar Sankaran #endif /*_DPU_HW_SSPP_H */ 40825fdd593SJeykumar Sankaran 409