197fb5e8dSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 225fdd593SJeykumar Sankaran /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 325fdd593SJeykumar Sankaran */ 425fdd593SJeykumar Sankaran 525fdd593SJeykumar Sankaran #ifndef _DPU_HW_SSPP_H 625fdd593SJeykumar Sankaran #define _DPU_HW_SSPP_H 725fdd593SJeykumar Sankaran 825fdd593SJeykumar Sankaran #include "dpu_hw_catalog.h" 925fdd593SJeykumar Sankaran #include "dpu_hw_mdss.h" 1025fdd593SJeykumar Sankaran #include "dpu_hw_util.h" 1125fdd593SJeykumar Sankaran #include "dpu_formats.h" 1225fdd593SJeykumar Sankaran 13b187794eSDmitry Baryshkov struct dpu_hw_sspp; 1425fdd593SJeykumar Sankaran 1525fdd593SJeykumar Sankaran /** 1625fdd593SJeykumar Sankaran * Flags 1725fdd593SJeykumar Sankaran */ 1825fdd593SJeykumar Sankaran #define DPU_SSPP_FLIP_LR BIT(0) 1925fdd593SJeykumar Sankaran #define DPU_SSPP_FLIP_UD BIT(1) 2025fdd593SJeykumar Sankaran #define DPU_SSPP_SOURCE_ROTATED_90 BIT(2) 2125fdd593SJeykumar Sankaran #define DPU_SSPP_ROT_90 BIT(3) 2225fdd593SJeykumar Sankaran #define DPU_SSPP_SOLID_FILL BIT(4) 2325fdd593SJeykumar Sankaran 2425fdd593SJeykumar Sankaran /** 2525fdd593SJeykumar Sankaran * Define all scaler feature bits in catalog 2625fdd593SJeykumar Sankaran */ 271e35e3fcSDmitry Baryshkov #define DPU_SSPP_SCALER (BIT(DPU_SSPP_SCALER_RGB) | \ 281e35e3fcSDmitry Baryshkov BIT(DPU_SSPP_SCALER_QSEED2) | \ 291e35e3fcSDmitry Baryshkov BIT(DPU_SSPP_SCALER_QSEED3) | \ 301e35e3fcSDmitry Baryshkov BIT(DPU_SSPP_SCALER_QSEED3LITE) | \ 311e35e3fcSDmitry Baryshkov BIT(DPU_SSPP_SCALER_QSEED4)) 321e35e3fcSDmitry Baryshkov 331e35e3fcSDmitry Baryshkov /* 341e35e3fcSDmitry Baryshkov * Define all CSC feature bits in catalog 351e35e3fcSDmitry Baryshkov */ 361e35e3fcSDmitry Baryshkov #define DPU_SSPP_CSC_ANY (BIT(DPU_SSPP_CSC) | \ 371e35e3fcSDmitry Baryshkov BIT(DPU_SSPP_CSC_10BIT)) 3825fdd593SJeykumar Sankaran 3925fdd593SJeykumar Sankaran /** 4025fdd593SJeykumar Sankaran * Component indices 4125fdd593SJeykumar Sankaran */ 4225fdd593SJeykumar Sankaran enum { 4325fdd593SJeykumar Sankaran DPU_SSPP_COMP_0, 4425fdd593SJeykumar Sankaran DPU_SSPP_COMP_1_2, 4525fdd593SJeykumar Sankaran DPU_SSPP_COMP_2, 4625fdd593SJeykumar Sankaran DPU_SSPP_COMP_3, 4725fdd593SJeykumar Sankaran 4825fdd593SJeykumar Sankaran DPU_SSPP_COMP_MAX 4925fdd593SJeykumar Sankaran }; 5025fdd593SJeykumar Sankaran 5125fdd593SJeykumar Sankaran /** 5225fdd593SJeykumar Sankaran * DPU_SSPP_RECT_SOLO - multirect disabled 5325fdd593SJeykumar Sankaran * DPU_SSPP_RECT_0 - rect0 of a multirect pipe 5425fdd593SJeykumar Sankaran * DPU_SSPP_RECT_1 - rect1 of a multirect pipe 5525fdd593SJeykumar Sankaran * 5625fdd593SJeykumar Sankaran * Note: HW supports multirect with either RECT0 or 5725fdd593SJeykumar Sankaran * RECT1. Considering no benefit of such configs over 5825fdd593SJeykumar Sankaran * SOLO mode and to keep the plane management simple, 5925fdd593SJeykumar Sankaran * we dont support single rect multirect configs. 6025fdd593SJeykumar Sankaran */ 6125fdd593SJeykumar Sankaran enum dpu_sspp_multirect_index { 6225fdd593SJeykumar Sankaran DPU_SSPP_RECT_SOLO = 0, 6325fdd593SJeykumar Sankaran DPU_SSPP_RECT_0, 6425fdd593SJeykumar Sankaran DPU_SSPP_RECT_1, 6525fdd593SJeykumar Sankaran }; 6625fdd593SJeykumar Sankaran 6725fdd593SJeykumar Sankaran enum dpu_sspp_multirect_mode { 6825fdd593SJeykumar Sankaran DPU_SSPP_MULTIRECT_NONE = 0, 6925fdd593SJeykumar Sankaran DPU_SSPP_MULTIRECT_PARALLEL, 7025fdd593SJeykumar Sankaran DPU_SSPP_MULTIRECT_TIME_MX, 7125fdd593SJeykumar Sankaran }; 7225fdd593SJeykumar Sankaran 7325fdd593SJeykumar Sankaran enum { 7425fdd593SJeykumar Sankaran DPU_FRAME_LINEAR, 7525fdd593SJeykumar Sankaran DPU_FRAME_TILE_A4X, 7625fdd593SJeykumar Sankaran DPU_FRAME_TILE_A5X, 7725fdd593SJeykumar Sankaran }; 7825fdd593SJeykumar Sankaran 7925fdd593SJeykumar Sankaran enum dpu_hw_filter { 8025fdd593SJeykumar Sankaran DPU_SCALE_FILTER_NEAREST = 0, 8125fdd593SJeykumar Sankaran DPU_SCALE_FILTER_BIL, 8225fdd593SJeykumar Sankaran DPU_SCALE_FILTER_PCMN, 8325fdd593SJeykumar Sankaran DPU_SCALE_FILTER_CA, 8425fdd593SJeykumar Sankaran DPU_SCALE_FILTER_MAX 8525fdd593SJeykumar Sankaran }; 8625fdd593SJeykumar Sankaran 8725fdd593SJeykumar Sankaran enum dpu_hw_filter_alpa { 8825fdd593SJeykumar Sankaran DPU_SCALE_ALPHA_PIXEL_REP, 8925fdd593SJeykumar Sankaran DPU_SCALE_ALPHA_BIL 9025fdd593SJeykumar Sankaran }; 9125fdd593SJeykumar Sankaran 9225fdd593SJeykumar Sankaran enum dpu_hw_filter_yuv { 9325fdd593SJeykumar Sankaran DPU_SCALE_2D_4X4, 9425fdd593SJeykumar Sankaran DPU_SCALE_2D_CIR, 9525fdd593SJeykumar Sankaran DPU_SCALE_1D_SEP, 9625fdd593SJeykumar Sankaran DPU_SCALE_BIL 9725fdd593SJeykumar Sankaran }; 9825fdd593SJeykumar Sankaran 9925fdd593SJeykumar Sankaran struct dpu_hw_sharp_cfg { 10025fdd593SJeykumar Sankaran u32 strength; 10125fdd593SJeykumar Sankaran u32 edge_thr; 10225fdd593SJeykumar Sankaran u32 smooth_thr; 10325fdd593SJeykumar Sankaran u32 noise_thr; 10425fdd593SJeykumar Sankaran }; 10525fdd593SJeykumar Sankaran 10625fdd593SJeykumar Sankaran struct dpu_hw_pixel_ext { 10725fdd593SJeykumar Sankaran /* scaling factors are enabled for this input layer */ 10825fdd593SJeykumar Sankaran uint8_t enable_pxl_ext; 10925fdd593SJeykumar Sankaran 11025fdd593SJeykumar Sankaran int init_phase_x[DPU_MAX_PLANES]; 11125fdd593SJeykumar Sankaran int phase_step_x[DPU_MAX_PLANES]; 11225fdd593SJeykumar Sankaran int init_phase_y[DPU_MAX_PLANES]; 11325fdd593SJeykumar Sankaran int phase_step_y[DPU_MAX_PLANES]; 11425fdd593SJeykumar Sankaran 11525fdd593SJeykumar Sankaran /* 11625fdd593SJeykumar Sankaran * Number of pixels extension in left, right, top and bottom direction 11725fdd593SJeykumar Sankaran * for all color components. This pixel value for each color component 11825fdd593SJeykumar Sankaran * should be sum of fetch + repeat pixels. 11925fdd593SJeykumar Sankaran */ 12025fdd593SJeykumar Sankaran int num_ext_pxls_left[DPU_MAX_PLANES]; 12125fdd593SJeykumar Sankaran int num_ext_pxls_right[DPU_MAX_PLANES]; 12225fdd593SJeykumar Sankaran int num_ext_pxls_top[DPU_MAX_PLANES]; 12325fdd593SJeykumar Sankaran int num_ext_pxls_btm[DPU_MAX_PLANES]; 12425fdd593SJeykumar Sankaran 12525fdd593SJeykumar Sankaran /* 12625fdd593SJeykumar Sankaran * Number of pixels needs to be overfetched in left, right, top and 12725fdd593SJeykumar Sankaran * bottom directions from source image for scaling. 12825fdd593SJeykumar Sankaran */ 12925fdd593SJeykumar Sankaran int left_ftch[DPU_MAX_PLANES]; 13025fdd593SJeykumar Sankaran int right_ftch[DPU_MAX_PLANES]; 13125fdd593SJeykumar Sankaran int top_ftch[DPU_MAX_PLANES]; 13225fdd593SJeykumar Sankaran int btm_ftch[DPU_MAX_PLANES]; 13325fdd593SJeykumar Sankaran 13425fdd593SJeykumar Sankaran /* 13525fdd593SJeykumar Sankaran * Number of pixels needs to be repeated in left, right, top and 13625fdd593SJeykumar Sankaran * bottom directions for scaling. 13725fdd593SJeykumar Sankaran */ 13825fdd593SJeykumar Sankaran int left_rpt[DPU_MAX_PLANES]; 13925fdd593SJeykumar Sankaran int right_rpt[DPU_MAX_PLANES]; 14025fdd593SJeykumar Sankaran int top_rpt[DPU_MAX_PLANES]; 14125fdd593SJeykumar Sankaran int btm_rpt[DPU_MAX_PLANES]; 14225fdd593SJeykumar Sankaran 14325fdd593SJeykumar Sankaran uint32_t roi_w[DPU_MAX_PLANES]; 14425fdd593SJeykumar Sankaran uint32_t roi_h[DPU_MAX_PLANES]; 14525fdd593SJeykumar Sankaran 14625fdd593SJeykumar Sankaran /* 14725fdd593SJeykumar Sankaran * Filter type to be used for scaling in horizontal and vertical 14825fdd593SJeykumar Sankaran * directions 14925fdd593SJeykumar Sankaran */ 15025fdd593SJeykumar Sankaran enum dpu_hw_filter horz_filter[DPU_MAX_PLANES]; 15125fdd593SJeykumar Sankaran enum dpu_hw_filter vert_filter[DPU_MAX_PLANES]; 15225fdd593SJeykumar Sankaran 15325fdd593SJeykumar Sankaran }; 15425fdd593SJeykumar Sankaran 15525fdd593SJeykumar Sankaran /** 156b187794eSDmitry Baryshkov * struct dpu_hw_sspp_cfg : SSPP configuration 15725fdd593SJeykumar Sankaran * @layout: format layout information for programming buffer to hardware 15825fdd593SJeykumar Sankaran * @src_rect: src ROI, caller takes into account the different operations 15925fdd593SJeykumar Sankaran * such as decimation, flip etc to program this field 16025fdd593SJeykumar Sankaran * @dest_rect: destination ROI. 16125fdd593SJeykumar Sankaran */ 162b187794eSDmitry Baryshkov struct dpu_hw_sspp_cfg { 16325fdd593SJeykumar Sankaran struct dpu_hw_fmt_layout layout; 16425fdd593SJeykumar Sankaran struct drm_rect src_rect; 16525fdd593SJeykumar Sankaran struct drm_rect dst_rect; 16625fdd593SJeykumar Sankaran }; 16725fdd593SJeykumar Sankaran 16825fdd593SJeykumar Sankaran /** 16925fdd593SJeykumar Sankaran * struct dpu_hw_pipe_qos_cfg : Source pipe QoS configuration 17025fdd593SJeykumar Sankaran * @creq_vblank: creq value generated to vbif during vertical blanking 17125fdd593SJeykumar Sankaran * @danger_vblank: danger value generated during vertical blanking 17225fdd593SJeykumar Sankaran * @vblank_en: enable creq_vblank and danger_vblank during vblank 17325fdd593SJeykumar Sankaran * @danger_safe_en: enable danger safe generation 17425fdd593SJeykumar Sankaran */ 17525fdd593SJeykumar Sankaran struct dpu_hw_pipe_qos_cfg { 17625fdd593SJeykumar Sankaran u32 creq_vblank; 17725fdd593SJeykumar Sankaran u32 danger_vblank; 17825fdd593SJeykumar Sankaran bool vblank_en; 17925fdd593SJeykumar Sankaran bool danger_safe_en; 18025fdd593SJeykumar Sankaran }; 18125fdd593SJeykumar Sankaran 18225fdd593SJeykumar Sankaran /** 18325fdd593SJeykumar Sankaran * enum CDP preload ahead address size 18425fdd593SJeykumar Sankaran */ 18525fdd593SJeykumar Sankaran enum { 18625fdd593SJeykumar Sankaran DPU_SSPP_CDP_PRELOAD_AHEAD_32, 18725fdd593SJeykumar Sankaran DPU_SSPP_CDP_PRELOAD_AHEAD_64 18825fdd593SJeykumar Sankaran }; 18925fdd593SJeykumar Sankaran 19025fdd593SJeykumar Sankaran /** 19125fdd593SJeykumar Sankaran * struct dpu_hw_pipe_ts_cfg - traffic shaper configuration 19225fdd593SJeykumar Sankaran * @size: size to prefill in bytes, or zero to disable 19325fdd593SJeykumar Sankaran * @time: time to prefill in usec, or zero to disable 19425fdd593SJeykumar Sankaran */ 19525fdd593SJeykumar Sankaran struct dpu_hw_pipe_ts_cfg { 19625fdd593SJeykumar Sankaran u64 size; 19725fdd593SJeykumar Sankaran u64 time; 19825fdd593SJeykumar Sankaran }; 19925fdd593SJeykumar Sankaran 20025fdd593SJeykumar Sankaran /** 201*3cfcd130SDmitry Baryshkov * struct dpu_sw_pipe - software pipe description 202*3cfcd130SDmitry Baryshkov * @sspp: backing SSPP pipe 203*3cfcd130SDmitry Baryshkov * @index: index of the rectangle of SSPP 204*3cfcd130SDmitry Baryshkov * @mode: parallel or time multiplex multirect mode 205*3cfcd130SDmitry Baryshkov */ 206*3cfcd130SDmitry Baryshkov struct dpu_sw_pipe { 207*3cfcd130SDmitry Baryshkov struct dpu_hw_sspp *sspp; 208*3cfcd130SDmitry Baryshkov enum dpu_sspp_multirect_index multirect_index; 209*3cfcd130SDmitry Baryshkov enum dpu_sspp_multirect_mode multirect_mode; 210*3cfcd130SDmitry Baryshkov }; 211*3cfcd130SDmitry Baryshkov 212*3cfcd130SDmitry Baryshkov /** 21325fdd593SJeykumar Sankaran * struct dpu_hw_sspp_ops - interface to the SSPP Hw driver functions 21425fdd593SJeykumar Sankaran * Caller must call the init function to get the pipe context for each pipe 21525fdd593SJeykumar Sankaran * Assumption is these functions will be called after clocks are enabled 21625fdd593SJeykumar Sankaran */ 21725fdd593SJeykumar Sankaran struct dpu_hw_sspp_ops { 21825fdd593SJeykumar Sankaran /** 21925fdd593SJeykumar Sankaran * setup_format - setup pixel format cropping rectangle, flip 22025fdd593SJeykumar Sankaran * @ctx: Pointer to pipe context 22125fdd593SJeykumar Sankaran * @cfg: Pointer to pipe config structure 22225fdd593SJeykumar Sankaran * @flags: Extra flags for format config 22325fdd593SJeykumar Sankaran * @index: rectangle index in multirect 22425fdd593SJeykumar Sankaran */ 225b187794eSDmitry Baryshkov void (*setup_format)(struct dpu_hw_sspp *ctx, 22625fdd593SJeykumar Sankaran const struct dpu_format *fmt, u32 flags, 22725fdd593SJeykumar Sankaran enum dpu_sspp_multirect_index index); 22825fdd593SJeykumar Sankaran 22925fdd593SJeykumar Sankaran /** 23025fdd593SJeykumar Sankaran * setup_rects - setup pipe ROI rectangles 23125fdd593SJeykumar Sankaran * @ctx: Pointer to pipe context 23225fdd593SJeykumar Sankaran * @cfg: Pointer to pipe config structure 23325fdd593SJeykumar Sankaran * @index: rectangle index in multirect 23425fdd593SJeykumar Sankaran */ 235b187794eSDmitry Baryshkov void (*setup_rects)(struct dpu_hw_sspp *ctx, 236b187794eSDmitry Baryshkov struct dpu_hw_sspp_cfg *cfg, 23725fdd593SJeykumar Sankaran enum dpu_sspp_multirect_index index); 23825fdd593SJeykumar Sankaran 23925fdd593SJeykumar Sankaran /** 24025fdd593SJeykumar Sankaran * setup_pe - setup pipe pixel extension 24125fdd593SJeykumar Sankaran * @ctx: Pointer to pipe context 24225fdd593SJeykumar Sankaran * @pe_ext: Pointer to pixel ext settings 24325fdd593SJeykumar Sankaran */ 244b187794eSDmitry Baryshkov void (*setup_pe)(struct dpu_hw_sspp *ctx, 24525fdd593SJeykumar Sankaran struct dpu_hw_pixel_ext *pe_ext); 24625fdd593SJeykumar Sankaran 24725fdd593SJeykumar Sankaran /** 24825fdd593SJeykumar Sankaran * setup_sourceaddress - setup pipe source addresses 24925fdd593SJeykumar Sankaran * @ctx: Pointer to pipe context 25025fdd593SJeykumar Sankaran * @cfg: Pointer to pipe config structure 25125fdd593SJeykumar Sankaran * @index: rectangle index in multirect 25225fdd593SJeykumar Sankaran */ 253b187794eSDmitry Baryshkov void (*setup_sourceaddress)(struct dpu_hw_sspp *ctx, 254b187794eSDmitry Baryshkov struct dpu_hw_sspp_cfg *cfg, 25525fdd593SJeykumar Sankaran enum dpu_sspp_multirect_index index); 25625fdd593SJeykumar Sankaran 25725fdd593SJeykumar Sankaran /** 25825fdd593SJeykumar Sankaran * setup_csc - setup color space coversion 25925fdd593SJeykumar Sankaran * @ctx: Pointer to pipe context 26025fdd593SJeykumar Sankaran * @data: Pointer to config structure 26125fdd593SJeykumar Sankaran */ 262b187794eSDmitry Baryshkov void (*setup_csc)(struct dpu_hw_sspp *ctx, const struct dpu_csc_cfg *data); 26325fdd593SJeykumar Sankaran 26425fdd593SJeykumar Sankaran /** 26525fdd593SJeykumar Sankaran * setup_solidfill - enable/disable colorfill 26625fdd593SJeykumar Sankaran * @ctx: Pointer to pipe context 26725fdd593SJeykumar Sankaran * @const_color: Fill color value 26825fdd593SJeykumar Sankaran * @flags: Pipe flags 26925fdd593SJeykumar Sankaran * @index: rectangle index in multirect 27025fdd593SJeykumar Sankaran */ 271b187794eSDmitry Baryshkov void (*setup_solidfill)(struct dpu_hw_sspp *ctx, u32 color, 27225fdd593SJeykumar Sankaran enum dpu_sspp_multirect_index index); 27325fdd593SJeykumar Sankaran 27425fdd593SJeykumar Sankaran /** 27525fdd593SJeykumar Sankaran * setup_multirect - setup multirect configuration 27625fdd593SJeykumar Sankaran * @ctx: Pointer to pipe context 27725fdd593SJeykumar Sankaran * @index: rectangle index in multirect 27825fdd593SJeykumar Sankaran * @mode: parallel fetch / time multiplex multirect mode 27925fdd593SJeykumar Sankaran */ 28025fdd593SJeykumar Sankaran 281b187794eSDmitry Baryshkov void (*setup_multirect)(struct dpu_hw_sspp *ctx, 28225fdd593SJeykumar Sankaran enum dpu_sspp_multirect_index index, 28325fdd593SJeykumar Sankaran enum dpu_sspp_multirect_mode mode); 28425fdd593SJeykumar Sankaran 28525fdd593SJeykumar Sankaran /** 28625fdd593SJeykumar Sankaran * setup_sharpening - setup sharpening 28725fdd593SJeykumar Sankaran * @ctx: Pointer to pipe context 28825fdd593SJeykumar Sankaran * @cfg: Pointer to config structure 28925fdd593SJeykumar Sankaran */ 290b187794eSDmitry Baryshkov void (*setup_sharpening)(struct dpu_hw_sspp *ctx, 29125fdd593SJeykumar Sankaran struct dpu_hw_sharp_cfg *cfg); 29225fdd593SJeykumar Sankaran 29325fdd593SJeykumar Sankaran /** 29425fdd593SJeykumar Sankaran * setup_danger_safe_lut - setup danger safe LUTs 29525fdd593SJeykumar Sankaran * @ctx: Pointer to pipe context 29644aab22dSDmitry Baryshkov * @danger_lut: LUT for generate danger level based on fill level 29744aab22dSDmitry Baryshkov * @safe_lut: LUT for generate safe level based on fill level 29825fdd593SJeykumar Sankaran * 29925fdd593SJeykumar Sankaran */ 300b187794eSDmitry Baryshkov void (*setup_danger_safe_lut)(struct dpu_hw_sspp *ctx, 30144aab22dSDmitry Baryshkov u32 danger_lut, 30244aab22dSDmitry Baryshkov u32 safe_lut); 30325fdd593SJeykumar Sankaran 30425fdd593SJeykumar Sankaran /** 30525fdd593SJeykumar Sankaran * setup_creq_lut - setup CREQ LUT 30625fdd593SJeykumar Sankaran * @ctx: Pointer to pipe context 30744aab22dSDmitry Baryshkov * @creq_lut: LUT for generate creq level based on fill level 30825fdd593SJeykumar Sankaran * 30925fdd593SJeykumar Sankaran */ 310b187794eSDmitry Baryshkov void (*setup_creq_lut)(struct dpu_hw_sspp *ctx, 31144aab22dSDmitry Baryshkov u64 creq_lut); 31225fdd593SJeykumar Sankaran 31325fdd593SJeykumar Sankaran /** 31425fdd593SJeykumar Sankaran * setup_qos_ctrl - setup QoS control 31525fdd593SJeykumar Sankaran * @ctx: Pointer to pipe context 31625fdd593SJeykumar Sankaran * @cfg: Pointer to pipe QoS configuration 31725fdd593SJeykumar Sankaran * 31825fdd593SJeykumar Sankaran */ 319b187794eSDmitry Baryshkov void (*setup_qos_ctrl)(struct dpu_hw_sspp *ctx, 32025fdd593SJeykumar Sankaran struct dpu_hw_pipe_qos_cfg *cfg); 32125fdd593SJeykumar Sankaran 32225fdd593SJeykumar Sankaran /** 32325fdd593SJeykumar Sankaran * setup_histogram - setup histograms 32425fdd593SJeykumar Sankaran * @ctx: Pointer to pipe context 32525fdd593SJeykumar Sankaran * @cfg: Pointer to histogram configuration 32625fdd593SJeykumar Sankaran */ 327b187794eSDmitry Baryshkov void (*setup_histogram)(struct dpu_hw_sspp *ctx, 32825fdd593SJeykumar Sankaran void *cfg); 32925fdd593SJeykumar Sankaran 33025fdd593SJeykumar Sankaran /** 33125fdd593SJeykumar Sankaran * setup_scaler - setup scaler 33225fdd593SJeykumar Sankaran * @ctx: Pointer to pipe context 33325fdd593SJeykumar Sankaran * @pipe_cfg: Pointer to pipe configuration 33425fdd593SJeykumar Sankaran * @scaler_cfg: Pointer to scaler configuration 33525fdd593SJeykumar Sankaran */ 336b187794eSDmitry Baryshkov void (*setup_scaler)(struct dpu_hw_sspp *ctx, 337b187794eSDmitry Baryshkov struct dpu_hw_sspp_cfg *pipe_cfg, 33825fdd593SJeykumar Sankaran void *scaler_cfg); 33925fdd593SJeykumar Sankaran 34025fdd593SJeykumar Sankaran /** 34125fdd593SJeykumar Sankaran * get_scaler_ver - get scaler h/w version 34225fdd593SJeykumar Sankaran * @ctx: Pointer to pipe context 34325fdd593SJeykumar Sankaran */ 344b187794eSDmitry Baryshkov u32 (*get_scaler_ver)(struct dpu_hw_sspp *ctx); 34525fdd593SJeykumar Sankaran 34625fdd593SJeykumar Sankaran /** 34725fdd593SJeykumar Sankaran * setup_cdp - setup client driven prefetch 34825fdd593SJeykumar Sankaran * @ctx: Pointer to pipe context 34925fdd593SJeykumar Sankaran * @cfg: Pointer to cdp configuration 350f7254785SDmitry Baryshkov * @index: rectangle index in multirect 35125fdd593SJeykumar Sankaran */ 352b187794eSDmitry Baryshkov void (*setup_cdp)(struct dpu_hw_sspp *ctx, 353786de937SAbhinav Kumar struct dpu_hw_cdp_cfg *cfg, 354f7254785SDmitry Baryshkov enum dpu_sspp_multirect_index index); 35525fdd593SJeykumar Sankaran }; 35625fdd593SJeykumar Sankaran 35725fdd593SJeykumar Sankaran /** 358b187794eSDmitry Baryshkov * struct dpu_hw_sspp - pipe description 35925fdd593SJeykumar Sankaran * @base: hardware block base structure 36025fdd593SJeykumar Sankaran * @hw: block hardware details 36125fdd593SJeykumar Sankaran * @catalog: back pointer to catalog 36225fdd593SJeykumar Sankaran * @mdp: pointer to associated mdp portion of the catalog 36325fdd593SJeykumar Sankaran * @idx: pipe index 36425fdd593SJeykumar Sankaran * @cap: pointer to layer_cfg 36525fdd593SJeykumar Sankaran * @ops: pointer to operations possible for this pipe 36625fdd593SJeykumar Sankaran */ 367b187794eSDmitry Baryshkov struct dpu_hw_sspp { 36825fdd593SJeykumar Sankaran struct dpu_hw_blk base; 36925fdd593SJeykumar Sankaran struct dpu_hw_blk_reg_map hw; 37032084967SDmitry Baryshkov const struct dpu_mdss_cfg *catalog; 371abda0d92SStephen Boyd const struct dpu_mdp_cfg *mdp; 37225fdd593SJeykumar Sankaran 37325fdd593SJeykumar Sankaran /* Pipe */ 37425fdd593SJeykumar Sankaran enum dpu_sspp idx; 37525fdd593SJeykumar Sankaran const struct dpu_sspp_cfg *cap; 37625fdd593SJeykumar Sankaran 37725fdd593SJeykumar Sankaran /* Ops */ 37825fdd593SJeykumar Sankaran struct dpu_hw_sspp_ops ops; 37925fdd593SJeykumar Sankaran }; 38025fdd593SJeykumar Sankaran 3812672e4e7SDmitry Baryshkov struct dpu_kms; 38225fdd593SJeykumar Sankaran /** 38325fdd593SJeykumar Sankaran * dpu_hw_sspp_init - initializes the sspp hw driver object. 38425fdd593SJeykumar Sankaran * Should be called once before accessing every pipe. 38525fdd593SJeykumar Sankaran * @idx: Pipe index for which driver object is required 38625fdd593SJeykumar Sankaran * @addr: Mapped register io address of MDP 38725fdd593SJeykumar Sankaran * @catalog : Pointer to mdss catalog data 38825fdd593SJeykumar Sankaran */ 389b187794eSDmitry Baryshkov struct dpu_hw_sspp *dpu_hw_sspp_init(enum dpu_sspp idx, 390aabf9220SDmitry Baryshkov void __iomem *addr, const struct dpu_mdss_cfg *catalog); 39125fdd593SJeykumar Sankaran 39225fdd593SJeykumar Sankaran /** 39325fdd593SJeykumar Sankaran * dpu_hw_sspp_destroy(): Destroys SSPP driver context 39425fdd593SJeykumar Sankaran * should be called during Hw pipe cleanup. 39525fdd593SJeykumar Sankaran * @ctx: Pointer to SSPP driver context returned by dpu_hw_sspp_init 39625fdd593SJeykumar Sankaran */ 397b187794eSDmitry Baryshkov void dpu_hw_sspp_destroy(struct dpu_hw_sspp *ctx); 39825fdd593SJeykumar Sankaran 399b187794eSDmitry Baryshkov int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pipe, struct dpu_kms *kms, 400b187794eSDmitry Baryshkov struct dentry *entry); 4012672e4e7SDmitry Baryshkov 40225fdd593SJeykumar Sankaran #endif /*_DPU_HW_SSPP_H */ 40325fdd593SJeykumar Sankaran 404