1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 3 */ 4 5 #include "dpu_hwio.h" 6 #include "dpu_hw_catalog.h" 7 #include "dpu_hw_lm.h" 8 #include "dpu_hw_sspp.h" 9 #include "dpu_kms.h" 10 11 #include <drm/drm_file.h> 12 13 #define DPU_FETCH_CONFIG_RESET_VALUE 0x00000087 14 15 /* DPU_SSPP_SRC */ 16 #define SSPP_SRC_SIZE 0x00 17 #define SSPP_SRC_XY 0x08 18 #define SSPP_OUT_SIZE 0x0c 19 #define SSPP_OUT_XY 0x10 20 #define SSPP_SRC0_ADDR 0x14 21 #define SSPP_SRC1_ADDR 0x18 22 #define SSPP_SRC2_ADDR 0x1C 23 #define SSPP_SRC3_ADDR 0x20 24 #define SSPP_SRC_YSTRIDE0 0x24 25 #define SSPP_SRC_YSTRIDE1 0x28 26 #define SSPP_SRC_FORMAT 0x30 27 #define SSPP_SRC_UNPACK_PATTERN 0x34 28 #define SSPP_SRC_OP_MODE 0x38 29 30 /* SSPP_MULTIRECT*/ 31 #define SSPP_SRC_SIZE_REC1 0x16C 32 #define SSPP_SRC_XY_REC1 0x168 33 #define SSPP_OUT_SIZE_REC1 0x160 34 #define SSPP_OUT_XY_REC1 0x164 35 #define SSPP_SRC_FORMAT_REC1 0x174 36 #define SSPP_SRC_UNPACK_PATTERN_REC1 0x178 37 #define SSPP_SRC_OP_MODE_REC1 0x17C 38 #define SSPP_MULTIRECT_OPMODE 0x170 39 #define SSPP_SRC_CONSTANT_COLOR_REC1 0x180 40 #define SSPP_EXCL_REC_SIZE_REC1 0x184 41 #define SSPP_EXCL_REC_XY_REC1 0x188 42 43 #define MDSS_MDP_OP_DEINTERLACE BIT(22) 44 #define MDSS_MDP_OP_DEINTERLACE_ODD BIT(23) 45 #define MDSS_MDP_OP_IGC_ROM_1 BIT(18) 46 #define MDSS_MDP_OP_IGC_ROM_0 BIT(17) 47 #define MDSS_MDP_OP_IGC_EN BIT(16) 48 #define MDSS_MDP_OP_FLIP_UD BIT(14) 49 #define MDSS_MDP_OP_FLIP_LR BIT(13) 50 #define MDSS_MDP_OP_BWC_EN BIT(0) 51 #define MDSS_MDP_OP_PE_OVERRIDE BIT(31) 52 #define MDSS_MDP_OP_BWC_LOSSLESS (0 << 1) 53 #define MDSS_MDP_OP_BWC_Q_HIGH (1 << 1) 54 #define MDSS_MDP_OP_BWC_Q_MED (2 << 1) 55 56 #define SSPP_SRC_CONSTANT_COLOR 0x3c 57 #define SSPP_EXCL_REC_CTL 0x40 58 #define SSPP_UBWC_STATIC_CTRL 0x44 59 #define SSPP_FETCH_CONFIG 0x048 60 #define SSPP_DANGER_LUT 0x60 61 #define SSPP_SAFE_LUT 0x64 62 #define SSPP_CREQ_LUT 0x68 63 #define SSPP_QOS_CTRL 0x6C 64 #define SSPP_DECIMATION_CONFIG 0xB4 65 #define SSPP_SRC_ADDR_SW_STATUS 0x70 66 #define SSPP_CREQ_LUT_0 0x74 67 #define SSPP_CREQ_LUT_1 0x78 68 #define SSPP_SW_PIX_EXT_C0_LR 0x100 69 #define SSPP_SW_PIX_EXT_C0_TB 0x104 70 #define SSPP_SW_PIX_EXT_C0_REQ_PIXELS 0x108 71 #define SSPP_SW_PIX_EXT_C1C2_LR 0x110 72 #define SSPP_SW_PIX_EXT_C1C2_TB 0x114 73 #define SSPP_SW_PIX_EXT_C1C2_REQ_PIXELS 0x118 74 #define SSPP_SW_PIX_EXT_C3_LR 0x120 75 #define SSPP_SW_PIX_EXT_C3_TB 0x124 76 #define SSPP_SW_PIX_EXT_C3_REQ_PIXELS 0x128 77 #define SSPP_TRAFFIC_SHAPER 0x130 78 #define SSPP_CDP_CNTL 0x134 79 #define SSPP_UBWC_ERROR_STATUS 0x138 80 #define SSPP_CDP_CNTL_REC1 0x13c 81 #define SSPP_TRAFFIC_SHAPER_PREFILL 0x150 82 #define SSPP_TRAFFIC_SHAPER_REC1_PREFILL 0x154 83 #define SSPP_TRAFFIC_SHAPER_REC1 0x158 84 #define SSPP_EXCL_REC_SIZE 0x1B4 85 #define SSPP_EXCL_REC_XY 0x1B8 86 #define SSPP_VIG_OP_MODE 0x0 87 #define SSPP_VIG_CSC_10_OP_MODE 0x0 88 #define SSPP_TRAFFIC_SHAPER_BPC_MAX 0xFF 89 90 /* SSPP_QOS_CTRL */ 91 #define SSPP_QOS_CTRL_VBLANK_EN BIT(16) 92 #define SSPP_QOS_CTRL_DANGER_SAFE_EN BIT(0) 93 #define SSPP_QOS_CTRL_DANGER_VBLANK_MASK 0x3 94 #define SSPP_QOS_CTRL_DANGER_VBLANK_OFF 4 95 #define SSPP_QOS_CTRL_CREQ_VBLANK_MASK 0x3 96 #define SSPP_QOS_CTRL_CREQ_VBLANK_OFF 20 97 98 /* DPU_SSPP_SCALER_QSEED2 */ 99 #define SCALE_CONFIG 0x04 100 #define COMP0_3_PHASE_STEP_X 0x10 101 #define COMP0_3_PHASE_STEP_Y 0x14 102 #define COMP1_2_PHASE_STEP_X 0x18 103 #define COMP1_2_PHASE_STEP_Y 0x1c 104 #define COMP0_3_INIT_PHASE_X 0x20 105 #define COMP0_3_INIT_PHASE_Y 0x24 106 #define COMP1_2_INIT_PHASE_X 0x28 107 #define COMP1_2_INIT_PHASE_Y 0x2C 108 #define VIG_0_QSEED2_SHARP 0x30 109 110 /* 111 * Definitions for ViG op modes 112 */ 113 #define VIG_OP_CSC_DST_DATAFMT BIT(19) 114 #define VIG_OP_CSC_SRC_DATAFMT BIT(18) 115 #define VIG_OP_CSC_EN BIT(17) 116 #define VIG_OP_MEM_PROT_CONT BIT(15) 117 #define VIG_OP_MEM_PROT_VAL BIT(14) 118 #define VIG_OP_MEM_PROT_SAT BIT(13) 119 #define VIG_OP_MEM_PROT_HUE BIT(12) 120 #define VIG_OP_HIST BIT(8) 121 #define VIG_OP_SKY_COL BIT(7) 122 #define VIG_OP_FOIL BIT(6) 123 #define VIG_OP_SKIN_COL BIT(5) 124 #define VIG_OP_PA_EN BIT(4) 125 #define VIG_OP_PA_SAT_ZERO_EXP BIT(2) 126 #define VIG_OP_MEM_PROT_BLEND BIT(1) 127 128 /* 129 * Definitions for CSC 10 op modes 130 */ 131 #define VIG_CSC_10_SRC_DATAFMT BIT(1) 132 #define VIG_CSC_10_EN BIT(0) 133 #define CSC_10BIT_OFFSET 4 134 135 /* traffic shaper clock in Hz */ 136 #define TS_CLK 19200000 137 138 139 static int _sspp_subblk_offset(struct dpu_hw_pipe *ctx, 140 int s_id, 141 u32 *idx) 142 { 143 int rc = 0; 144 const struct dpu_sspp_sub_blks *sblk; 145 146 if (!ctx || !ctx->cap || !ctx->cap->sblk) 147 return -EINVAL; 148 149 sblk = ctx->cap->sblk; 150 151 switch (s_id) { 152 case DPU_SSPP_SRC: 153 *idx = sblk->src_blk.base; 154 break; 155 case DPU_SSPP_SCALER_QSEED2: 156 case DPU_SSPP_SCALER_QSEED3: 157 case DPU_SSPP_SCALER_RGB: 158 *idx = sblk->scaler_blk.base; 159 break; 160 case DPU_SSPP_CSC: 161 case DPU_SSPP_CSC_10BIT: 162 *idx = sblk->csc_blk.base; 163 break; 164 default: 165 rc = -EINVAL; 166 } 167 168 return rc; 169 } 170 171 static void dpu_hw_sspp_setup_multirect(struct dpu_hw_pipe *ctx, 172 enum dpu_sspp_multirect_index index, 173 enum dpu_sspp_multirect_mode mode) 174 { 175 u32 mode_mask; 176 u32 idx; 177 178 if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx)) 179 return; 180 181 if (index == DPU_SSPP_RECT_SOLO) { 182 /** 183 * if rect index is RECT_SOLO, we cannot expect a 184 * virtual plane sharing the same SSPP id. So we go 185 * and disable multirect 186 */ 187 mode_mask = 0; 188 } else { 189 mode_mask = DPU_REG_READ(&ctx->hw, SSPP_MULTIRECT_OPMODE + idx); 190 mode_mask |= index; 191 if (mode == DPU_SSPP_MULTIRECT_TIME_MX) 192 mode_mask |= BIT(2); 193 else 194 mode_mask &= ~BIT(2); 195 } 196 197 DPU_REG_WRITE(&ctx->hw, SSPP_MULTIRECT_OPMODE + idx, mode_mask); 198 } 199 200 static void _sspp_setup_opmode(struct dpu_hw_pipe *ctx, 201 u32 mask, u8 en) 202 { 203 u32 idx; 204 u32 opmode; 205 206 if (!test_bit(DPU_SSPP_SCALER_QSEED2, &ctx->cap->features) || 207 _sspp_subblk_offset(ctx, DPU_SSPP_SCALER_QSEED2, &idx) || 208 !test_bit(DPU_SSPP_CSC, &ctx->cap->features)) 209 return; 210 211 opmode = DPU_REG_READ(&ctx->hw, SSPP_VIG_OP_MODE + idx); 212 213 if (en) 214 opmode |= mask; 215 else 216 opmode &= ~mask; 217 218 DPU_REG_WRITE(&ctx->hw, SSPP_VIG_OP_MODE + idx, opmode); 219 } 220 221 static void _sspp_setup_csc10_opmode(struct dpu_hw_pipe *ctx, 222 u32 mask, u8 en) 223 { 224 u32 idx; 225 u32 opmode; 226 227 if (_sspp_subblk_offset(ctx, DPU_SSPP_CSC_10BIT, &idx)) 228 return; 229 230 opmode = DPU_REG_READ(&ctx->hw, SSPP_VIG_CSC_10_OP_MODE + idx); 231 if (en) 232 opmode |= mask; 233 else 234 opmode &= ~mask; 235 236 DPU_REG_WRITE(&ctx->hw, SSPP_VIG_CSC_10_OP_MODE + idx, opmode); 237 } 238 239 /* 240 * Setup source pixel format, flip, 241 */ 242 static void dpu_hw_sspp_setup_format(struct dpu_hw_pipe *ctx, 243 const struct dpu_format *fmt, u32 flags, 244 enum dpu_sspp_multirect_index rect_mode) 245 { 246 struct dpu_hw_blk_reg_map *c; 247 u32 chroma_samp, unpack, src_format; 248 u32 opmode = 0; 249 u32 fast_clear = 0; 250 u32 op_mode_off, unpack_pat_off, format_off; 251 u32 idx; 252 253 if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx) || !fmt) 254 return; 255 256 if (rect_mode == DPU_SSPP_RECT_SOLO || rect_mode == DPU_SSPP_RECT_0) { 257 op_mode_off = SSPP_SRC_OP_MODE; 258 unpack_pat_off = SSPP_SRC_UNPACK_PATTERN; 259 format_off = SSPP_SRC_FORMAT; 260 } else { 261 op_mode_off = SSPP_SRC_OP_MODE_REC1; 262 unpack_pat_off = SSPP_SRC_UNPACK_PATTERN_REC1; 263 format_off = SSPP_SRC_FORMAT_REC1; 264 } 265 266 c = &ctx->hw; 267 opmode = DPU_REG_READ(c, op_mode_off + idx); 268 opmode &= ~(MDSS_MDP_OP_FLIP_LR | MDSS_MDP_OP_FLIP_UD | 269 MDSS_MDP_OP_BWC_EN | MDSS_MDP_OP_PE_OVERRIDE); 270 271 if (flags & DPU_SSPP_FLIP_LR) 272 opmode |= MDSS_MDP_OP_FLIP_LR; 273 if (flags & DPU_SSPP_FLIP_UD) 274 opmode |= MDSS_MDP_OP_FLIP_UD; 275 276 chroma_samp = fmt->chroma_sample; 277 if (flags & DPU_SSPP_SOURCE_ROTATED_90) { 278 if (chroma_samp == DPU_CHROMA_H2V1) 279 chroma_samp = DPU_CHROMA_H1V2; 280 else if (chroma_samp == DPU_CHROMA_H1V2) 281 chroma_samp = DPU_CHROMA_H2V1; 282 } 283 284 src_format = (chroma_samp << 23) | (fmt->fetch_planes << 19) | 285 (fmt->bits[C3_ALPHA] << 6) | (fmt->bits[C2_R_Cr] << 4) | 286 (fmt->bits[C1_B_Cb] << 2) | (fmt->bits[C0_G_Y] << 0); 287 288 if (flags & DPU_SSPP_ROT_90) 289 src_format |= BIT(11); /* ROT90 */ 290 291 if (fmt->alpha_enable && fmt->fetch_planes == DPU_PLANE_INTERLEAVED) 292 src_format |= BIT(8); /* SRCC3_EN */ 293 294 if (flags & DPU_SSPP_SOLID_FILL) 295 src_format |= BIT(22); 296 297 unpack = (fmt->element[3] << 24) | (fmt->element[2] << 16) | 298 (fmt->element[1] << 8) | (fmt->element[0] << 0); 299 src_format |= ((fmt->unpack_count - 1) << 12) | 300 (fmt->unpack_tight << 17) | 301 (fmt->unpack_align_msb << 18) | 302 ((fmt->bpp - 1) << 9); 303 304 if (fmt->fetch_mode != DPU_FETCH_LINEAR) { 305 if (DPU_FORMAT_IS_UBWC(fmt)) 306 opmode |= MDSS_MDP_OP_BWC_EN; 307 src_format |= (fmt->fetch_mode & 3) << 30; /*FRAME_FORMAT */ 308 DPU_REG_WRITE(c, SSPP_FETCH_CONFIG, 309 DPU_FETCH_CONFIG_RESET_VALUE | 310 ctx->mdp->highest_bank_bit << 18); 311 switch (ctx->catalog->caps->ubwc_version) { 312 case DPU_HW_UBWC_VER_10: 313 fast_clear = fmt->alpha_enable ? BIT(31) : 0; 314 DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, 315 fast_clear | (ctx->mdp->ubwc_swizzle & 0x1) | 316 BIT(8) | 317 (ctx->mdp->highest_bank_bit << 4)); 318 break; 319 case DPU_HW_UBWC_VER_20: 320 fast_clear = fmt->alpha_enable ? BIT(31) : 0; 321 DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, 322 fast_clear | (ctx->mdp->ubwc_swizzle) | 323 (ctx->mdp->highest_bank_bit << 4)); 324 break; 325 case DPU_HW_UBWC_VER_30: 326 DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, 327 BIT(30) | (ctx->mdp->ubwc_swizzle) | 328 (ctx->mdp->highest_bank_bit << 4)); 329 break; 330 case DPU_HW_UBWC_VER_40: 331 DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, 332 DPU_FORMAT_IS_YUV(fmt) ? 0 : BIT(30)); 333 break; 334 } 335 } 336 337 opmode |= MDSS_MDP_OP_PE_OVERRIDE; 338 339 /* if this is YUV pixel format, enable CSC */ 340 if (DPU_FORMAT_IS_YUV(fmt)) 341 src_format |= BIT(15); 342 343 if (DPU_FORMAT_IS_DX(fmt)) 344 src_format |= BIT(14); 345 346 /* update scaler opmode, if appropriate */ 347 if (test_bit(DPU_SSPP_CSC, &ctx->cap->features)) 348 _sspp_setup_opmode(ctx, VIG_OP_CSC_EN | VIG_OP_CSC_SRC_DATAFMT, 349 DPU_FORMAT_IS_YUV(fmt)); 350 else if (test_bit(DPU_SSPP_CSC_10BIT, &ctx->cap->features)) 351 _sspp_setup_csc10_opmode(ctx, 352 VIG_CSC_10_EN | VIG_CSC_10_SRC_DATAFMT, 353 DPU_FORMAT_IS_YUV(fmt)); 354 355 DPU_REG_WRITE(c, format_off + idx, src_format); 356 DPU_REG_WRITE(c, unpack_pat_off + idx, unpack); 357 DPU_REG_WRITE(c, op_mode_off + idx, opmode); 358 359 /* clear previous UBWC error */ 360 DPU_REG_WRITE(c, SSPP_UBWC_ERROR_STATUS + idx, BIT(31)); 361 } 362 363 static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_pipe *ctx, 364 struct dpu_hw_pixel_ext *pe_ext) 365 { 366 struct dpu_hw_blk_reg_map *c; 367 u8 color; 368 u32 lr_pe[4], tb_pe[4], tot_req_pixels[4]; 369 const u32 bytemask = 0xff; 370 const u32 shortmask = 0xffff; 371 u32 idx; 372 373 if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx) || !pe_ext) 374 return; 375 376 c = &ctx->hw; 377 378 /* program SW pixel extension override for all pipes*/ 379 for (color = 0; color < DPU_MAX_PLANES; color++) { 380 /* color 2 has the same set of registers as color 1 */ 381 if (color == 2) 382 continue; 383 384 lr_pe[color] = ((pe_ext->right_ftch[color] & bytemask) << 24)| 385 ((pe_ext->right_rpt[color] & bytemask) << 16)| 386 ((pe_ext->left_ftch[color] & bytemask) << 8)| 387 (pe_ext->left_rpt[color] & bytemask); 388 389 tb_pe[color] = ((pe_ext->btm_ftch[color] & bytemask) << 24)| 390 ((pe_ext->btm_rpt[color] & bytemask) << 16)| 391 ((pe_ext->top_ftch[color] & bytemask) << 8)| 392 (pe_ext->top_rpt[color] & bytemask); 393 394 tot_req_pixels[color] = (((pe_ext->roi_h[color] + 395 pe_ext->num_ext_pxls_top[color] + 396 pe_ext->num_ext_pxls_btm[color]) & shortmask) << 16) | 397 ((pe_ext->roi_w[color] + 398 pe_ext->num_ext_pxls_left[color] + 399 pe_ext->num_ext_pxls_right[color]) & shortmask); 400 } 401 402 /* color 0 */ 403 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C0_LR + idx, lr_pe[0]); 404 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C0_TB + idx, tb_pe[0]); 405 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C0_REQ_PIXELS + idx, 406 tot_req_pixels[0]); 407 408 /* color 1 and color 2 */ 409 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C1C2_LR + idx, lr_pe[1]); 410 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C1C2_TB + idx, tb_pe[1]); 411 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C1C2_REQ_PIXELS + idx, 412 tot_req_pixels[1]); 413 414 /* color 3 */ 415 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C3_LR + idx, lr_pe[3]); 416 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C3_TB + idx, lr_pe[3]); 417 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C3_REQ_PIXELS + idx, 418 tot_req_pixels[3]); 419 } 420 421 static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_pipe *ctx, 422 struct dpu_hw_pipe_cfg *sspp, 423 void *scaler_cfg) 424 { 425 u32 idx; 426 struct dpu_hw_scaler3_cfg *scaler3_cfg = scaler_cfg; 427 428 if (_sspp_subblk_offset(ctx, DPU_SSPP_SCALER_QSEED3, &idx) || !sspp 429 || !scaler3_cfg) 430 return; 431 432 dpu_hw_setup_scaler3(&ctx->hw, scaler3_cfg, idx, 433 ctx->cap->sblk->scaler_blk.version, 434 sspp->layout.format); 435 } 436 437 static u32 _dpu_hw_sspp_get_scaler3_ver(struct dpu_hw_pipe *ctx) 438 { 439 u32 idx; 440 441 if (!ctx || _sspp_subblk_offset(ctx, DPU_SSPP_SCALER_QSEED3, &idx)) 442 return 0; 443 444 return dpu_hw_get_scaler3_ver(&ctx->hw, idx); 445 } 446 447 /* 448 * dpu_hw_sspp_setup_rects() 449 */ 450 static void dpu_hw_sspp_setup_rects(struct dpu_hw_pipe *ctx, 451 struct dpu_hw_pipe_cfg *cfg, 452 enum dpu_sspp_multirect_index rect_index) 453 { 454 struct dpu_hw_blk_reg_map *c; 455 u32 src_size, src_xy, dst_size, dst_xy, ystride0, ystride1; 456 u32 src_size_off, src_xy_off, out_size_off, out_xy_off; 457 u32 idx; 458 459 if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx) || !cfg) 460 return; 461 462 c = &ctx->hw; 463 464 if (rect_index == DPU_SSPP_RECT_SOLO || rect_index == DPU_SSPP_RECT_0) { 465 src_size_off = SSPP_SRC_SIZE; 466 src_xy_off = SSPP_SRC_XY; 467 out_size_off = SSPP_OUT_SIZE; 468 out_xy_off = SSPP_OUT_XY; 469 } else { 470 src_size_off = SSPP_SRC_SIZE_REC1; 471 src_xy_off = SSPP_SRC_XY_REC1; 472 out_size_off = SSPP_OUT_SIZE_REC1; 473 out_xy_off = SSPP_OUT_XY_REC1; 474 } 475 476 477 /* src and dest rect programming */ 478 src_xy = (cfg->src_rect.y1 << 16) | cfg->src_rect.x1; 479 src_size = (drm_rect_height(&cfg->src_rect) << 16) | 480 drm_rect_width(&cfg->src_rect); 481 dst_xy = (cfg->dst_rect.y1 << 16) | cfg->dst_rect.x1; 482 dst_size = (drm_rect_height(&cfg->dst_rect) << 16) | 483 drm_rect_width(&cfg->dst_rect); 484 485 if (rect_index == DPU_SSPP_RECT_SOLO) { 486 ystride0 = (cfg->layout.plane_pitch[0]) | 487 (cfg->layout.plane_pitch[1] << 16); 488 ystride1 = (cfg->layout.plane_pitch[2]) | 489 (cfg->layout.plane_pitch[3] << 16); 490 } else { 491 ystride0 = DPU_REG_READ(c, SSPP_SRC_YSTRIDE0 + idx); 492 ystride1 = DPU_REG_READ(c, SSPP_SRC_YSTRIDE1 + idx); 493 494 if (rect_index == DPU_SSPP_RECT_0) { 495 ystride0 = (ystride0 & 0xFFFF0000) | 496 (cfg->layout.plane_pitch[0] & 0x0000FFFF); 497 ystride1 = (ystride1 & 0xFFFF0000)| 498 (cfg->layout.plane_pitch[2] & 0x0000FFFF); 499 } else { 500 ystride0 = (ystride0 & 0x0000FFFF) | 501 ((cfg->layout.plane_pitch[0] << 16) & 502 0xFFFF0000); 503 ystride1 = (ystride1 & 0x0000FFFF) | 504 ((cfg->layout.plane_pitch[2] << 16) & 505 0xFFFF0000); 506 } 507 } 508 509 /* rectangle register programming */ 510 DPU_REG_WRITE(c, src_size_off + idx, src_size); 511 DPU_REG_WRITE(c, src_xy_off + idx, src_xy); 512 DPU_REG_WRITE(c, out_size_off + idx, dst_size); 513 DPU_REG_WRITE(c, out_xy_off + idx, dst_xy); 514 515 DPU_REG_WRITE(c, SSPP_SRC_YSTRIDE0 + idx, ystride0); 516 DPU_REG_WRITE(c, SSPP_SRC_YSTRIDE1 + idx, ystride1); 517 } 518 519 static void dpu_hw_sspp_setup_sourceaddress(struct dpu_hw_pipe *ctx, 520 struct dpu_hw_pipe_cfg *cfg, 521 enum dpu_sspp_multirect_index rect_mode) 522 { 523 int i; 524 u32 idx; 525 526 if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx)) 527 return; 528 529 if (rect_mode == DPU_SSPP_RECT_SOLO) { 530 for (i = 0; i < ARRAY_SIZE(cfg->layout.plane_addr); i++) 531 DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx + i * 0x4, 532 cfg->layout.plane_addr[i]); 533 } else if (rect_mode == DPU_SSPP_RECT_0) { 534 DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx, 535 cfg->layout.plane_addr[0]); 536 DPU_REG_WRITE(&ctx->hw, SSPP_SRC2_ADDR + idx, 537 cfg->layout.plane_addr[2]); 538 } else { 539 DPU_REG_WRITE(&ctx->hw, SSPP_SRC1_ADDR + idx, 540 cfg->layout.plane_addr[0]); 541 DPU_REG_WRITE(&ctx->hw, SSPP_SRC3_ADDR + idx, 542 cfg->layout.plane_addr[2]); 543 } 544 } 545 546 static void dpu_hw_sspp_setup_csc(struct dpu_hw_pipe *ctx, 547 const struct dpu_csc_cfg *data) 548 { 549 u32 idx; 550 bool csc10 = false; 551 552 if (_sspp_subblk_offset(ctx, DPU_SSPP_CSC, &idx) || !data) 553 return; 554 555 if (test_bit(DPU_SSPP_CSC_10BIT, &ctx->cap->features)) { 556 idx += CSC_10BIT_OFFSET; 557 csc10 = true; 558 } 559 560 dpu_hw_csc_setup(&ctx->hw, idx, data, csc10); 561 } 562 563 static void dpu_hw_sspp_setup_solidfill(struct dpu_hw_pipe *ctx, u32 color, enum 564 dpu_sspp_multirect_index rect_index) 565 { 566 u32 idx; 567 568 if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx)) 569 return; 570 571 if (rect_index == DPU_SSPP_RECT_SOLO || rect_index == DPU_SSPP_RECT_0) 572 DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR + idx, color); 573 else 574 DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR_REC1 + idx, 575 color); 576 } 577 578 static void dpu_hw_sspp_setup_danger_safe_lut(struct dpu_hw_pipe *ctx, 579 u32 danger_lut, 580 u32 safe_lut) 581 { 582 u32 idx; 583 584 if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx)) 585 return; 586 587 DPU_REG_WRITE(&ctx->hw, SSPP_DANGER_LUT + idx, danger_lut); 588 DPU_REG_WRITE(&ctx->hw, SSPP_SAFE_LUT + idx, safe_lut); 589 } 590 591 static void dpu_hw_sspp_setup_creq_lut(struct dpu_hw_pipe *ctx, 592 u64 creq_lut) 593 { 594 u32 idx; 595 596 if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx)) 597 return; 598 599 if (ctx->cap && test_bit(DPU_SSPP_QOS_8LVL, &ctx->cap->features)) { 600 DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT_0 + idx, creq_lut); 601 DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT_1 + idx, 602 creq_lut >> 32); 603 } else { 604 DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT + idx, creq_lut); 605 } 606 } 607 608 static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_pipe *ctx, 609 struct dpu_hw_pipe_qos_cfg *cfg) 610 { 611 u32 idx; 612 u32 qos_ctrl = 0; 613 614 if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx)) 615 return; 616 617 if (cfg->vblank_en) { 618 qos_ctrl |= ((cfg->creq_vblank & 619 SSPP_QOS_CTRL_CREQ_VBLANK_MASK) << 620 SSPP_QOS_CTRL_CREQ_VBLANK_OFF); 621 qos_ctrl |= ((cfg->danger_vblank & 622 SSPP_QOS_CTRL_DANGER_VBLANK_MASK) << 623 SSPP_QOS_CTRL_DANGER_VBLANK_OFF); 624 qos_ctrl |= SSPP_QOS_CTRL_VBLANK_EN; 625 } 626 627 if (cfg->danger_safe_en) 628 qos_ctrl |= SSPP_QOS_CTRL_DANGER_SAFE_EN; 629 630 DPU_REG_WRITE(&ctx->hw, SSPP_QOS_CTRL + idx, qos_ctrl); 631 } 632 633 static void dpu_hw_sspp_setup_cdp(struct dpu_hw_pipe *ctx, 634 struct dpu_hw_cdp_cfg *cfg, 635 enum dpu_sspp_multirect_index index) 636 { 637 u32 idx; 638 u32 cdp_cntl = 0; 639 u32 cdp_cntl_offset = 0; 640 641 if (!ctx || !cfg) 642 return; 643 644 if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx)) 645 return; 646 647 if (index == DPU_SSPP_RECT_SOLO || index == DPU_SSPP_RECT_0) 648 cdp_cntl_offset = SSPP_CDP_CNTL; 649 else 650 cdp_cntl_offset = SSPP_CDP_CNTL_REC1; 651 652 if (cfg->enable) 653 cdp_cntl |= BIT(0); 654 if (cfg->ubwc_meta_enable) 655 cdp_cntl |= BIT(1); 656 if (cfg->tile_amortize_enable) 657 cdp_cntl |= BIT(2); 658 if (cfg->preload_ahead == DPU_SSPP_CDP_PRELOAD_AHEAD_64) 659 cdp_cntl |= BIT(3); 660 661 DPU_REG_WRITE(&ctx->hw, cdp_cntl_offset, cdp_cntl); 662 } 663 664 static void _setup_layer_ops(struct dpu_hw_pipe *c, 665 unsigned long features) 666 { 667 if (test_bit(DPU_SSPP_SRC, &features)) { 668 c->ops.setup_format = dpu_hw_sspp_setup_format; 669 c->ops.setup_rects = dpu_hw_sspp_setup_rects; 670 c->ops.setup_sourceaddress = dpu_hw_sspp_setup_sourceaddress; 671 c->ops.setup_solidfill = dpu_hw_sspp_setup_solidfill; 672 c->ops.setup_pe = dpu_hw_sspp_setup_pe_config; 673 } 674 675 if (test_bit(DPU_SSPP_QOS, &features)) { 676 c->ops.setup_danger_safe_lut = 677 dpu_hw_sspp_setup_danger_safe_lut; 678 c->ops.setup_creq_lut = dpu_hw_sspp_setup_creq_lut; 679 c->ops.setup_qos_ctrl = dpu_hw_sspp_setup_qos_ctrl; 680 } 681 682 if (test_bit(DPU_SSPP_CSC, &features) || 683 test_bit(DPU_SSPP_CSC_10BIT, &features)) 684 c->ops.setup_csc = dpu_hw_sspp_setup_csc; 685 686 if (test_bit(DPU_SSPP_SMART_DMA_V1, &c->cap->features) || 687 test_bit(DPU_SSPP_SMART_DMA_V2, &c->cap->features)) 688 c->ops.setup_multirect = dpu_hw_sspp_setup_multirect; 689 690 if (test_bit(DPU_SSPP_SCALER_QSEED3, &features) || 691 test_bit(DPU_SSPP_SCALER_QSEED3LITE, &features) || 692 test_bit(DPU_SSPP_SCALER_QSEED4, &features)) { 693 c->ops.setup_scaler = _dpu_hw_sspp_setup_scaler3; 694 c->ops.get_scaler_ver = _dpu_hw_sspp_get_scaler3_ver; 695 } 696 697 if (test_bit(DPU_SSPP_CDP, &features)) 698 c->ops.setup_cdp = dpu_hw_sspp_setup_cdp; 699 } 700 701 #ifdef CONFIG_DEBUG_FS 702 int _dpu_hw_sspp_init_debugfs(struct dpu_hw_pipe *hw_pipe, struct dpu_kms *kms, struct dentry *entry) 703 { 704 const struct dpu_sspp_cfg *cfg = hw_pipe->cap; 705 const struct dpu_sspp_sub_blks *sblk = cfg->sblk; 706 struct dentry *debugfs_root; 707 char sspp_name[32]; 708 709 snprintf(sspp_name, sizeof(sspp_name), "%d", hw_pipe->idx); 710 711 /* create overall sub-directory for the pipe */ 712 debugfs_root = 713 debugfs_create_dir(sspp_name, entry); 714 715 /* don't error check these */ 716 debugfs_create_xul("features", 0600, 717 debugfs_root, (unsigned long *)&hw_pipe->cap->features); 718 719 /* add register dump support */ 720 dpu_debugfs_create_regset32("src_blk", 0400, 721 debugfs_root, 722 sblk->src_blk.base + cfg->base, 723 sblk->src_blk.len, 724 kms); 725 726 if (cfg->features & BIT(DPU_SSPP_SCALER_QSEED3) || 727 cfg->features & BIT(DPU_SSPP_SCALER_QSEED3LITE) || 728 cfg->features & BIT(DPU_SSPP_SCALER_QSEED2) || 729 cfg->features & BIT(DPU_SSPP_SCALER_QSEED4)) 730 dpu_debugfs_create_regset32("scaler_blk", 0400, 731 debugfs_root, 732 sblk->scaler_blk.base + cfg->base, 733 sblk->scaler_blk.len, 734 kms); 735 736 if (cfg->features & BIT(DPU_SSPP_CSC) || 737 cfg->features & BIT(DPU_SSPP_CSC_10BIT)) 738 dpu_debugfs_create_regset32("csc_blk", 0400, 739 debugfs_root, 740 sblk->csc_blk.base + cfg->base, 741 sblk->csc_blk.len, 742 kms); 743 744 debugfs_create_u32("xin_id", 745 0400, 746 debugfs_root, 747 (u32 *) &cfg->xin_id); 748 debugfs_create_u32("clk_ctrl", 749 0400, 750 debugfs_root, 751 (u32 *) &cfg->clk_ctrl); 752 debugfs_create_x32("creq_vblank", 753 0600, 754 debugfs_root, 755 (u32 *) &sblk->creq_vblank); 756 debugfs_create_x32("danger_vblank", 757 0600, 758 debugfs_root, 759 (u32 *) &sblk->danger_vblank); 760 761 return 0; 762 } 763 #endif 764 765 766 static const struct dpu_sspp_cfg *_sspp_offset(enum dpu_sspp sspp, 767 void __iomem *addr, 768 const struct dpu_mdss_cfg *catalog, 769 struct dpu_hw_blk_reg_map *b) 770 { 771 int i; 772 773 if ((sspp < SSPP_MAX) && catalog && addr && b) { 774 for (i = 0; i < catalog->sspp_count; i++) { 775 if (sspp == catalog->sspp[i].id) { 776 b->blk_addr = addr + catalog->sspp[i].base; 777 b->log_mask = DPU_DBG_MASK_SSPP; 778 return &catalog->sspp[i]; 779 } 780 } 781 } 782 783 return ERR_PTR(-ENOMEM); 784 } 785 786 struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx, 787 void __iomem *addr, const struct dpu_mdss_cfg *catalog) 788 { 789 struct dpu_hw_pipe *hw_pipe; 790 const struct dpu_sspp_cfg *cfg; 791 792 if (!addr || !catalog) 793 return ERR_PTR(-EINVAL); 794 795 hw_pipe = kzalloc(sizeof(*hw_pipe), GFP_KERNEL); 796 if (!hw_pipe) 797 return ERR_PTR(-ENOMEM); 798 799 cfg = _sspp_offset(idx, addr, catalog, &hw_pipe->hw); 800 if (IS_ERR_OR_NULL(cfg)) { 801 kfree(hw_pipe); 802 return ERR_PTR(-EINVAL); 803 } 804 805 /* Assign ops */ 806 hw_pipe->catalog = catalog; 807 hw_pipe->mdp = &catalog->mdp[0]; 808 hw_pipe->idx = idx; 809 hw_pipe->cap = cfg; 810 _setup_layer_ops(hw_pipe, hw_pipe->cap->features); 811 812 return hw_pipe; 813 } 814 815 void dpu_hw_sspp_destroy(struct dpu_hw_pipe *ctx) 816 { 817 kfree(ctx); 818 } 819 820