1 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 2 * 3 * This program is free software; you can redistribute it and/or modify 4 * it under the terms of the GNU General Public License version 2 and 5 * only version 2 as published by the Free Software Foundation. 6 * 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 */ 12 13 #include "dpu_hwio.h" 14 #include "dpu_hw_catalog.h" 15 #include "dpu_hw_lm.h" 16 #include "dpu_hw_sspp.h" 17 #include "dpu_kms.h" 18 19 #define DPU_FETCH_CONFIG_RESET_VALUE 0x00000087 20 21 /* DPU_SSPP_SRC */ 22 #define SSPP_SRC_SIZE 0x00 23 #define SSPP_SRC_XY 0x08 24 #define SSPP_OUT_SIZE 0x0c 25 #define SSPP_OUT_XY 0x10 26 #define SSPP_SRC0_ADDR 0x14 27 #define SSPP_SRC1_ADDR 0x18 28 #define SSPP_SRC2_ADDR 0x1C 29 #define SSPP_SRC3_ADDR 0x20 30 #define SSPP_SRC_YSTRIDE0 0x24 31 #define SSPP_SRC_YSTRIDE1 0x28 32 #define SSPP_SRC_FORMAT 0x30 33 #define SSPP_SRC_UNPACK_PATTERN 0x34 34 #define SSPP_SRC_OP_MODE 0x38 35 36 /* SSPP_MULTIRECT*/ 37 #define SSPP_SRC_SIZE_REC1 0x16C 38 #define SSPP_SRC_XY_REC1 0x168 39 #define SSPP_OUT_SIZE_REC1 0x160 40 #define SSPP_OUT_XY_REC1 0x164 41 #define SSPP_SRC_FORMAT_REC1 0x174 42 #define SSPP_SRC_UNPACK_PATTERN_REC1 0x178 43 #define SSPP_SRC_OP_MODE_REC1 0x17C 44 #define SSPP_MULTIRECT_OPMODE 0x170 45 #define SSPP_SRC_CONSTANT_COLOR_REC1 0x180 46 #define SSPP_EXCL_REC_SIZE_REC1 0x184 47 #define SSPP_EXCL_REC_XY_REC1 0x188 48 49 #define MDSS_MDP_OP_DEINTERLACE BIT(22) 50 #define MDSS_MDP_OP_DEINTERLACE_ODD BIT(23) 51 #define MDSS_MDP_OP_IGC_ROM_1 BIT(18) 52 #define MDSS_MDP_OP_IGC_ROM_0 BIT(17) 53 #define MDSS_MDP_OP_IGC_EN BIT(16) 54 #define MDSS_MDP_OP_FLIP_UD BIT(14) 55 #define MDSS_MDP_OP_FLIP_LR BIT(13) 56 #define MDSS_MDP_OP_BWC_EN BIT(0) 57 #define MDSS_MDP_OP_PE_OVERRIDE BIT(31) 58 #define MDSS_MDP_OP_BWC_LOSSLESS (0 << 1) 59 #define MDSS_MDP_OP_BWC_Q_HIGH (1 << 1) 60 #define MDSS_MDP_OP_BWC_Q_MED (2 << 1) 61 62 #define SSPP_SRC_CONSTANT_COLOR 0x3c 63 #define SSPP_EXCL_REC_CTL 0x40 64 #define SSPP_UBWC_STATIC_CTRL 0x44 65 #define SSPP_FETCH_CONFIG 0x048 66 #define SSPP_DANGER_LUT 0x60 67 #define SSPP_SAFE_LUT 0x64 68 #define SSPP_CREQ_LUT 0x68 69 #define SSPP_QOS_CTRL 0x6C 70 #define SSPP_DECIMATION_CONFIG 0xB4 71 #define SSPP_SRC_ADDR_SW_STATUS 0x70 72 #define SSPP_CREQ_LUT_0 0x74 73 #define SSPP_CREQ_LUT_1 0x78 74 #define SSPP_SW_PIX_EXT_C0_LR 0x100 75 #define SSPP_SW_PIX_EXT_C0_TB 0x104 76 #define SSPP_SW_PIX_EXT_C0_REQ_PIXELS 0x108 77 #define SSPP_SW_PIX_EXT_C1C2_LR 0x110 78 #define SSPP_SW_PIX_EXT_C1C2_TB 0x114 79 #define SSPP_SW_PIX_EXT_C1C2_REQ_PIXELS 0x118 80 #define SSPP_SW_PIX_EXT_C3_LR 0x120 81 #define SSPP_SW_PIX_EXT_C3_TB 0x124 82 #define SSPP_SW_PIX_EXT_C3_REQ_PIXELS 0x128 83 #define SSPP_TRAFFIC_SHAPER 0x130 84 #define SSPP_CDP_CNTL 0x134 85 #define SSPP_UBWC_ERROR_STATUS 0x138 86 #define SSPP_TRAFFIC_SHAPER_PREFILL 0x150 87 #define SSPP_TRAFFIC_SHAPER_REC1_PREFILL 0x154 88 #define SSPP_TRAFFIC_SHAPER_REC1 0x158 89 #define SSPP_EXCL_REC_SIZE 0x1B4 90 #define SSPP_EXCL_REC_XY 0x1B8 91 #define SSPP_VIG_OP_MODE 0x0 92 #define SSPP_VIG_CSC_10_OP_MODE 0x0 93 #define SSPP_TRAFFIC_SHAPER_BPC_MAX 0xFF 94 95 /* SSPP_QOS_CTRL */ 96 #define SSPP_QOS_CTRL_VBLANK_EN BIT(16) 97 #define SSPP_QOS_CTRL_DANGER_SAFE_EN BIT(0) 98 #define SSPP_QOS_CTRL_DANGER_VBLANK_MASK 0x3 99 #define SSPP_QOS_CTRL_DANGER_VBLANK_OFF 4 100 #define SSPP_QOS_CTRL_CREQ_VBLANK_MASK 0x3 101 #define SSPP_QOS_CTRL_CREQ_VBLANK_OFF 20 102 103 /* DPU_SSPP_SCALER_QSEED2 */ 104 #define SCALE_CONFIG 0x04 105 #define COMP0_3_PHASE_STEP_X 0x10 106 #define COMP0_3_PHASE_STEP_Y 0x14 107 #define COMP1_2_PHASE_STEP_X 0x18 108 #define COMP1_2_PHASE_STEP_Y 0x1c 109 #define COMP0_3_INIT_PHASE_X 0x20 110 #define COMP0_3_INIT_PHASE_Y 0x24 111 #define COMP1_2_INIT_PHASE_X 0x28 112 #define COMP1_2_INIT_PHASE_Y 0x2C 113 #define VIG_0_QSEED2_SHARP 0x30 114 115 /* 116 * Definitions for ViG op modes 117 */ 118 #define VIG_OP_CSC_DST_DATAFMT BIT(19) 119 #define VIG_OP_CSC_SRC_DATAFMT BIT(18) 120 #define VIG_OP_CSC_EN BIT(17) 121 #define VIG_OP_MEM_PROT_CONT BIT(15) 122 #define VIG_OP_MEM_PROT_VAL BIT(14) 123 #define VIG_OP_MEM_PROT_SAT BIT(13) 124 #define VIG_OP_MEM_PROT_HUE BIT(12) 125 #define VIG_OP_HIST BIT(8) 126 #define VIG_OP_SKY_COL BIT(7) 127 #define VIG_OP_FOIL BIT(6) 128 #define VIG_OP_SKIN_COL BIT(5) 129 #define VIG_OP_PA_EN BIT(4) 130 #define VIG_OP_PA_SAT_ZERO_EXP BIT(2) 131 #define VIG_OP_MEM_PROT_BLEND BIT(1) 132 133 /* 134 * Definitions for CSC 10 op modes 135 */ 136 #define VIG_CSC_10_SRC_DATAFMT BIT(1) 137 #define VIG_CSC_10_EN BIT(0) 138 #define CSC_10BIT_OFFSET 4 139 140 /* traffic shaper clock in Hz */ 141 #define TS_CLK 19200000 142 143 static int _sspp_subblk_offset(struct dpu_hw_pipe *ctx, 144 int s_id, 145 u32 *idx) 146 { 147 int rc = 0; 148 const struct dpu_sspp_sub_blks *sblk = ctx->cap->sblk; 149 150 if (!ctx) 151 return -EINVAL; 152 153 switch (s_id) { 154 case DPU_SSPP_SRC: 155 *idx = sblk->src_blk.base; 156 break; 157 case DPU_SSPP_SCALER_QSEED2: 158 case DPU_SSPP_SCALER_QSEED3: 159 case DPU_SSPP_SCALER_RGB: 160 *idx = sblk->scaler_blk.base; 161 break; 162 case DPU_SSPP_CSC: 163 case DPU_SSPP_CSC_10BIT: 164 *idx = sblk->csc_blk.base; 165 break; 166 default: 167 rc = -EINVAL; 168 } 169 170 return rc; 171 } 172 173 static void dpu_hw_sspp_setup_multirect(struct dpu_hw_pipe *ctx, 174 enum dpu_sspp_multirect_index index, 175 enum dpu_sspp_multirect_mode mode) 176 { 177 u32 mode_mask; 178 u32 idx; 179 180 if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx)) 181 return; 182 183 if (index == DPU_SSPP_RECT_SOLO) { 184 /** 185 * if rect index is RECT_SOLO, we cannot expect a 186 * virtual plane sharing the same SSPP id. So we go 187 * and disable multirect 188 */ 189 mode_mask = 0; 190 } else { 191 mode_mask = DPU_REG_READ(&ctx->hw, SSPP_MULTIRECT_OPMODE + idx); 192 mode_mask |= index; 193 if (mode == DPU_SSPP_MULTIRECT_TIME_MX) 194 mode_mask |= BIT(2); 195 else 196 mode_mask &= ~BIT(2); 197 } 198 199 DPU_REG_WRITE(&ctx->hw, SSPP_MULTIRECT_OPMODE + idx, mode_mask); 200 } 201 202 static void _sspp_setup_opmode(struct dpu_hw_pipe *ctx, 203 u32 mask, u8 en) 204 { 205 u32 idx; 206 u32 opmode; 207 208 if (!test_bit(DPU_SSPP_SCALER_QSEED2, &ctx->cap->features) || 209 _sspp_subblk_offset(ctx, DPU_SSPP_SCALER_QSEED2, &idx) || 210 !test_bit(DPU_SSPP_CSC, &ctx->cap->features)) 211 return; 212 213 opmode = DPU_REG_READ(&ctx->hw, SSPP_VIG_OP_MODE + idx); 214 215 if (en) 216 opmode |= mask; 217 else 218 opmode &= ~mask; 219 220 DPU_REG_WRITE(&ctx->hw, SSPP_VIG_OP_MODE + idx, opmode); 221 } 222 223 static void _sspp_setup_csc10_opmode(struct dpu_hw_pipe *ctx, 224 u32 mask, u8 en) 225 { 226 u32 idx; 227 u32 opmode; 228 229 if (_sspp_subblk_offset(ctx, DPU_SSPP_CSC_10BIT, &idx)) 230 return; 231 232 opmode = DPU_REG_READ(&ctx->hw, SSPP_VIG_CSC_10_OP_MODE + idx); 233 if (en) 234 opmode |= mask; 235 else 236 opmode &= ~mask; 237 238 DPU_REG_WRITE(&ctx->hw, SSPP_VIG_CSC_10_OP_MODE + idx, opmode); 239 } 240 241 /** 242 * Setup source pixel format, flip, 243 */ 244 static void dpu_hw_sspp_setup_format(struct dpu_hw_pipe *ctx, 245 const struct dpu_format *fmt, u32 flags, 246 enum dpu_sspp_multirect_index rect_mode) 247 { 248 struct dpu_hw_blk_reg_map *c; 249 u32 chroma_samp, unpack, src_format; 250 u32 opmode = 0; 251 u32 fast_clear = 0; 252 u32 op_mode_off, unpack_pat_off, format_off; 253 u32 idx; 254 255 if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx) || !fmt) 256 return; 257 258 if (rect_mode == DPU_SSPP_RECT_SOLO || rect_mode == DPU_SSPP_RECT_0) { 259 op_mode_off = SSPP_SRC_OP_MODE; 260 unpack_pat_off = SSPP_SRC_UNPACK_PATTERN; 261 format_off = SSPP_SRC_FORMAT; 262 } else { 263 op_mode_off = SSPP_SRC_OP_MODE_REC1; 264 unpack_pat_off = SSPP_SRC_UNPACK_PATTERN_REC1; 265 format_off = SSPP_SRC_FORMAT_REC1; 266 } 267 268 c = &ctx->hw; 269 opmode = DPU_REG_READ(c, op_mode_off + idx); 270 opmode &= ~(MDSS_MDP_OP_FLIP_LR | MDSS_MDP_OP_FLIP_UD | 271 MDSS_MDP_OP_BWC_EN | MDSS_MDP_OP_PE_OVERRIDE); 272 273 if (flags & DPU_SSPP_FLIP_LR) 274 opmode |= MDSS_MDP_OP_FLIP_LR; 275 if (flags & DPU_SSPP_FLIP_UD) 276 opmode |= MDSS_MDP_OP_FLIP_UD; 277 278 chroma_samp = fmt->chroma_sample; 279 if (flags & DPU_SSPP_SOURCE_ROTATED_90) { 280 if (chroma_samp == DPU_CHROMA_H2V1) 281 chroma_samp = DPU_CHROMA_H1V2; 282 else if (chroma_samp == DPU_CHROMA_H1V2) 283 chroma_samp = DPU_CHROMA_H2V1; 284 } 285 286 src_format = (chroma_samp << 23) | (fmt->fetch_planes << 19) | 287 (fmt->bits[C3_ALPHA] << 6) | (fmt->bits[C2_R_Cr] << 4) | 288 (fmt->bits[C1_B_Cb] << 2) | (fmt->bits[C0_G_Y] << 0); 289 290 if (flags & DPU_SSPP_ROT_90) 291 src_format |= BIT(11); /* ROT90 */ 292 293 if (fmt->alpha_enable && fmt->fetch_planes == DPU_PLANE_INTERLEAVED) 294 src_format |= BIT(8); /* SRCC3_EN */ 295 296 if (flags & DPU_SSPP_SOLID_FILL) 297 src_format |= BIT(22); 298 299 unpack = (fmt->element[3] << 24) | (fmt->element[2] << 16) | 300 (fmt->element[1] << 8) | (fmt->element[0] << 0); 301 src_format |= ((fmt->unpack_count - 1) << 12) | 302 (fmt->unpack_tight << 17) | 303 (fmt->unpack_align_msb << 18) | 304 ((fmt->bpp - 1) << 9); 305 306 if (fmt->fetch_mode != DPU_FETCH_LINEAR) { 307 if (DPU_FORMAT_IS_UBWC(fmt)) 308 opmode |= MDSS_MDP_OP_BWC_EN; 309 src_format |= (fmt->fetch_mode & 3) << 30; /*FRAME_FORMAT */ 310 DPU_REG_WRITE(c, SSPP_FETCH_CONFIG, 311 DPU_FETCH_CONFIG_RESET_VALUE | 312 ctx->mdp->highest_bank_bit << 18); 313 if (IS_UBWC_20_SUPPORTED(ctx->catalog->caps->ubwc_version)) { 314 fast_clear = fmt->alpha_enable ? BIT(31) : 0; 315 DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, 316 fast_clear | (ctx->mdp->ubwc_swizzle) | 317 (ctx->mdp->highest_bank_bit << 4)); 318 } 319 } 320 321 opmode |= MDSS_MDP_OP_PE_OVERRIDE; 322 323 /* if this is YUV pixel format, enable CSC */ 324 if (DPU_FORMAT_IS_YUV(fmt)) 325 src_format |= BIT(15); 326 327 if (DPU_FORMAT_IS_DX(fmt)) 328 src_format |= BIT(14); 329 330 /* update scaler opmode, if appropriate */ 331 if (test_bit(DPU_SSPP_CSC, &ctx->cap->features)) 332 _sspp_setup_opmode(ctx, VIG_OP_CSC_EN | VIG_OP_CSC_SRC_DATAFMT, 333 DPU_FORMAT_IS_YUV(fmt)); 334 else if (test_bit(DPU_SSPP_CSC_10BIT, &ctx->cap->features)) 335 _sspp_setup_csc10_opmode(ctx, 336 VIG_CSC_10_EN | VIG_CSC_10_SRC_DATAFMT, 337 DPU_FORMAT_IS_YUV(fmt)); 338 339 DPU_REG_WRITE(c, format_off + idx, src_format); 340 DPU_REG_WRITE(c, unpack_pat_off + idx, unpack); 341 DPU_REG_WRITE(c, op_mode_off + idx, opmode); 342 343 /* clear previous UBWC error */ 344 DPU_REG_WRITE(c, SSPP_UBWC_ERROR_STATUS + idx, BIT(31)); 345 } 346 347 static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_pipe *ctx, 348 struct dpu_hw_pixel_ext *pe_ext) 349 { 350 struct dpu_hw_blk_reg_map *c; 351 u8 color; 352 u32 lr_pe[4], tb_pe[4], tot_req_pixels[4]; 353 const u32 bytemask = 0xff; 354 const u32 shortmask = 0xffff; 355 u32 idx; 356 357 if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx) || !pe_ext) 358 return; 359 360 c = &ctx->hw; 361 362 /* program SW pixel extension override for all pipes*/ 363 for (color = 0; color < DPU_MAX_PLANES; color++) { 364 /* color 2 has the same set of registers as color 1 */ 365 if (color == 2) 366 continue; 367 368 lr_pe[color] = ((pe_ext->right_ftch[color] & bytemask) << 24)| 369 ((pe_ext->right_rpt[color] & bytemask) << 16)| 370 ((pe_ext->left_ftch[color] & bytemask) << 8)| 371 (pe_ext->left_rpt[color] & bytemask); 372 373 tb_pe[color] = ((pe_ext->btm_ftch[color] & bytemask) << 24)| 374 ((pe_ext->btm_rpt[color] & bytemask) << 16)| 375 ((pe_ext->top_ftch[color] & bytemask) << 8)| 376 (pe_ext->top_rpt[color] & bytemask); 377 378 tot_req_pixels[color] = (((pe_ext->roi_h[color] + 379 pe_ext->num_ext_pxls_top[color] + 380 pe_ext->num_ext_pxls_btm[color]) & shortmask) << 16) | 381 ((pe_ext->roi_w[color] + 382 pe_ext->num_ext_pxls_left[color] + 383 pe_ext->num_ext_pxls_right[color]) & shortmask); 384 } 385 386 /* color 0 */ 387 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C0_LR + idx, lr_pe[0]); 388 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C0_TB + idx, tb_pe[0]); 389 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C0_REQ_PIXELS + idx, 390 tot_req_pixels[0]); 391 392 /* color 1 and color 2 */ 393 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C1C2_LR + idx, lr_pe[1]); 394 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C1C2_TB + idx, tb_pe[1]); 395 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C1C2_REQ_PIXELS + idx, 396 tot_req_pixels[1]); 397 398 /* color 3 */ 399 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C3_LR + idx, lr_pe[3]); 400 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C3_TB + idx, lr_pe[3]); 401 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C3_REQ_PIXELS + idx, 402 tot_req_pixels[3]); 403 } 404 405 static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_pipe *ctx, 406 struct dpu_hw_pipe_cfg *sspp, 407 struct dpu_hw_pixel_ext *pe, 408 void *scaler_cfg) 409 { 410 u32 idx; 411 struct dpu_hw_scaler3_cfg *scaler3_cfg = scaler_cfg; 412 413 (void)pe; 414 if (_sspp_subblk_offset(ctx, DPU_SSPP_SCALER_QSEED3, &idx) || !sspp 415 || !scaler3_cfg || !ctx || !ctx->cap || !ctx->cap->sblk) 416 return; 417 418 dpu_hw_setup_scaler3(&ctx->hw, scaler3_cfg, idx, 419 ctx->cap->sblk->scaler_blk.version, 420 sspp->layout.format); 421 } 422 423 static u32 _dpu_hw_sspp_get_scaler3_ver(struct dpu_hw_pipe *ctx) 424 { 425 u32 idx; 426 427 if (!ctx || _sspp_subblk_offset(ctx, DPU_SSPP_SCALER_QSEED3, &idx)) 428 return 0; 429 430 return dpu_hw_get_scaler3_ver(&ctx->hw, idx); 431 } 432 433 /** 434 * dpu_hw_sspp_setup_rects() 435 */ 436 static void dpu_hw_sspp_setup_rects(struct dpu_hw_pipe *ctx, 437 struct dpu_hw_pipe_cfg *cfg, 438 enum dpu_sspp_multirect_index rect_index) 439 { 440 struct dpu_hw_blk_reg_map *c; 441 u32 src_size, src_xy, dst_size, dst_xy, ystride0, ystride1; 442 u32 src_size_off, src_xy_off, out_size_off, out_xy_off; 443 u32 idx; 444 445 if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx) || !cfg) 446 return; 447 448 c = &ctx->hw; 449 450 if (rect_index == DPU_SSPP_RECT_SOLO || rect_index == DPU_SSPP_RECT_0) { 451 src_size_off = SSPP_SRC_SIZE; 452 src_xy_off = SSPP_SRC_XY; 453 out_size_off = SSPP_OUT_SIZE; 454 out_xy_off = SSPP_OUT_XY; 455 } else { 456 src_size_off = SSPP_SRC_SIZE_REC1; 457 src_xy_off = SSPP_SRC_XY_REC1; 458 out_size_off = SSPP_OUT_SIZE_REC1; 459 out_xy_off = SSPP_OUT_XY_REC1; 460 } 461 462 463 /* src and dest rect programming */ 464 src_xy = (cfg->src_rect.y1 << 16) | cfg->src_rect.x1; 465 src_size = (drm_rect_height(&cfg->src_rect) << 16) | 466 drm_rect_width(&cfg->src_rect); 467 dst_xy = (cfg->dst_rect.y1 << 16) | cfg->dst_rect.x1; 468 dst_size = (drm_rect_height(&cfg->dst_rect) << 16) | 469 drm_rect_width(&cfg->dst_rect); 470 471 if (rect_index == DPU_SSPP_RECT_SOLO) { 472 ystride0 = (cfg->layout.plane_pitch[0]) | 473 (cfg->layout.plane_pitch[1] << 16); 474 ystride1 = (cfg->layout.plane_pitch[2]) | 475 (cfg->layout.plane_pitch[3] << 16); 476 } else { 477 ystride0 = DPU_REG_READ(c, SSPP_SRC_YSTRIDE0 + idx); 478 ystride1 = DPU_REG_READ(c, SSPP_SRC_YSTRIDE1 + idx); 479 480 if (rect_index == DPU_SSPP_RECT_0) { 481 ystride0 = (ystride0 & 0xFFFF0000) | 482 (cfg->layout.plane_pitch[0] & 0x0000FFFF); 483 ystride1 = (ystride1 & 0xFFFF0000)| 484 (cfg->layout.plane_pitch[2] & 0x0000FFFF); 485 } else { 486 ystride0 = (ystride0 & 0x0000FFFF) | 487 ((cfg->layout.plane_pitch[0] << 16) & 488 0xFFFF0000); 489 ystride1 = (ystride1 & 0x0000FFFF) | 490 ((cfg->layout.plane_pitch[2] << 16) & 491 0xFFFF0000); 492 } 493 } 494 495 /* rectangle register programming */ 496 DPU_REG_WRITE(c, src_size_off + idx, src_size); 497 DPU_REG_WRITE(c, src_xy_off + idx, src_xy); 498 DPU_REG_WRITE(c, out_size_off + idx, dst_size); 499 DPU_REG_WRITE(c, out_xy_off + idx, dst_xy); 500 501 DPU_REG_WRITE(c, SSPP_SRC_YSTRIDE0 + idx, ystride0); 502 DPU_REG_WRITE(c, SSPP_SRC_YSTRIDE1 + idx, ystride1); 503 } 504 505 static void dpu_hw_sspp_setup_sourceaddress(struct dpu_hw_pipe *ctx, 506 struct dpu_hw_pipe_cfg *cfg, 507 enum dpu_sspp_multirect_index rect_mode) 508 { 509 int i; 510 u32 idx; 511 512 if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx)) 513 return; 514 515 if (rect_mode == DPU_SSPP_RECT_SOLO) { 516 for (i = 0; i < ARRAY_SIZE(cfg->layout.plane_addr); i++) 517 DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx + i * 0x4, 518 cfg->layout.plane_addr[i]); 519 } else if (rect_mode == DPU_SSPP_RECT_0) { 520 DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx, 521 cfg->layout.plane_addr[0]); 522 DPU_REG_WRITE(&ctx->hw, SSPP_SRC2_ADDR + idx, 523 cfg->layout.plane_addr[2]); 524 } else { 525 DPU_REG_WRITE(&ctx->hw, SSPP_SRC1_ADDR + idx, 526 cfg->layout.plane_addr[0]); 527 DPU_REG_WRITE(&ctx->hw, SSPP_SRC3_ADDR + idx, 528 cfg->layout.plane_addr[2]); 529 } 530 } 531 532 static void dpu_hw_sspp_setup_csc(struct dpu_hw_pipe *ctx, 533 struct dpu_csc_cfg *data) 534 { 535 u32 idx; 536 bool csc10 = false; 537 538 if (_sspp_subblk_offset(ctx, DPU_SSPP_CSC, &idx) || !data) 539 return; 540 541 if (test_bit(DPU_SSPP_CSC_10BIT, &ctx->cap->features)) { 542 idx += CSC_10BIT_OFFSET; 543 csc10 = true; 544 } 545 546 dpu_hw_csc_setup(&ctx->hw, idx, data, csc10); 547 } 548 549 static void dpu_hw_sspp_setup_solidfill(struct dpu_hw_pipe *ctx, u32 color, enum 550 dpu_sspp_multirect_index rect_index) 551 { 552 u32 idx; 553 554 if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx)) 555 return; 556 557 if (rect_index == DPU_SSPP_RECT_SOLO || rect_index == DPU_SSPP_RECT_0) 558 DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR + idx, color); 559 else 560 DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR_REC1 + idx, 561 color); 562 } 563 564 static void dpu_hw_sspp_setup_danger_safe_lut(struct dpu_hw_pipe *ctx, 565 struct dpu_hw_pipe_qos_cfg *cfg) 566 { 567 u32 idx; 568 569 if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx)) 570 return; 571 572 DPU_REG_WRITE(&ctx->hw, SSPP_DANGER_LUT + idx, cfg->danger_lut); 573 DPU_REG_WRITE(&ctx->hw, SSPP_SAFE_LUT + idx, cfg->safe_lut); 574 } 575 576 static void dpu_hw_sspp_setup_creq_lut(struct dpu_hw_pipe *ctx, 577 struct dpu_hw_pipe_qos_cfg *cfg) 578 { 579 u32 idx; 580 581 if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx)) 582 return; 583 584 if (ctx->cap && test_bit(DPU_SSPP_QOS_8LVL, &ctx->cap->features)) { 585 DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT_0 + idx, cfg->creq_lut); 586 DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT_1 + idx, 587 cfg->creq_lut >> 32); 588 } else { 589 DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT + idx, cfg->creq_lut); 590 } 591 } 592 593 static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_pipe *ctx, 594 struct dpu_hw_pipe_qos_cfg *cfg) 595 { 596 u32 idx; 597 u32 qos_ctrl = 0; 598 599 if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx)) 600 return; 601 602 if (cfg->vblank_en) { 603 qos_ctrl |= ((cfg->creq_vblank & 604 SSPP_QOS_CTRL_CREQ_VBLANK_MASK) << 605 SSPP_QOS_CTRL_CREQ_VBLANK_OFF); 606 qos_ctrl |= ((cfg->danger_vblank & 607 SSPP_QOS_CTRL_DANGER_VBLANK_MASK) << 608 SSPP_QOS_CTRL_DANGER_VBLANK_OFF); 609 qos_ctrl |= SSPP_QOS_CTRL_VBLANK_EN; 610 } 611 612 if (cfg->danger_safe_en) 613 qos_ctrl |= SSPP_QOS_CTRL_DANGER_SAFE_EN; 614 615 DPU_REG_WRITE(&ctx->hw, SSPP_QOS_CTRL + idx, qos_ctrl); 616 } 617 618 static void dpu_hw_sspp_setup_cdp(struct dpu_hw_pipe *ctx, 619 struct dpu_hw_pipe_cdp_cfg *cfg) 620 { 621 u32 idx; 622 u32 cdp_cntl = 0; 623 624 if (!ctx || !cfg) 625 return; 626 627 if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx)) 628 return; 629 630 if (cfg->enable) 631 cdp_cntl |= BIT(0); 632 if (cfg->ubwc_meta_enable) 633 cdp_cntl |= BIT(1); 634 if (cfg->tile_amortize_enable) 635 cdp_cntl |= BIT(2); 636 if (cfg->preload_ahead == DPU_SSPP_CDP_PRELOAD_AHEAD_64) 637 cdp_cntl |= BIT(3); 638 639 DPU_REG_WRITE(&ctx->hw, SSPP_CDP_CNTL, cdp_cntl); 640 } 641 642 static void _setup_layer_ops(struct dpu_hw_pipe *c, 643 unsigned long features) 644 { 645 if (test_bit(DPU_SSPP_SRC, &features)) { 646 c->ops.setup_format = dpu_hw_sspp_setup_format; 647 c->ops.setup_rects = dpu_hw_sspp_setup_rects; 648 c->ops.setup_sourceaddress = dpu_hw_sspp_setup_sourceaddress; 649 c->ops.setup_solidfill = dpu_hw_sspp_setup_solidfill; 650 c->ops.setup_pe = dpu_hw_sspp_setup_pe_config; 651 } 652 653 if (test_bit(DPU_SSPP_QOS, &features)) { 654 c->ops.setup_danger_safe_lut = 655 dpu_hw_sspp_setup_danger_safe_lut; 656 c->ops.setup_creq_lut = dpu_hw_sspp_setup_creq_lut; 657 c->ops.setup_qos_ctrl = dpu_hw_sspp_setup_qos_ctrl; 658 } 659 660 if (test_bit(DPU_SSPP_CSC, &features) || 661 test_bit(DPU_SSPP_CSC_10BIT, &features)) 662 c->ops.setup_csc = dpu_hw_sspp_setup_csc; 663 664 if (test_bit(DPU_SSPP_SMART_DMA_V1, &c->cap->features) || 665 test_bit(DPU_SSPP_SMART_DMA_V2, &c->cap->features)) 666 c->ops.setup_multirect = dpu_hw_sspp_setup_multirect; 667 668 if (test_bit(DPU_SSPP_SCALER_QSEED3, &features)) { 669 c->ops.setup_scaler = _dpu_hw_sspp_setup_scaler3; 670 c->ops.get_scaler_ver = _dpu_hw_sspp_get_scaler3_ver; 671 } 672 673 if (test_bit(DPU_SSPP_CDP, &features)) 674 c->ops.setup_cdp = dpu_hw_sspp_setup_cdp; 675 } 676 677 static struct dpu_sspp_cfg *_sspp_offset(enum dpu_sspp sspp, 678 void __iomem *addr, 679 struct dpu_mdss_cfg *catalog, 680 struct dpu_hw_blk_reg_map *b) 681 { 682 int i; 683 684 if ((sspp < SSPP_MAX) && catalog && addr && b) { 685 for (i = 0; i < catalog->sspp_count; i++) { 686 if (sspp == catalog->sspp[i].id) { 687 b->base_off = addr; 688 b->blk_off = catalog->sspp[i].base; 689 b->length = catalog->sspp[i].len; 690 b->hwversion = catalog->hwversion; 691 b->log_mask = DPU_DBG_MASK_SSPP; 692 return &catalog->sspp[i]; 693 } 694 } 695 } 696 697 return ERR_PTR(-ENOMEM); 698 } 699 700 static struct dpu_hw_blk_ops dpu_hw_ops; 701 702 struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx, 703 void __iomem *addr, struct dpu_mdss_cfg *catalog, 704 bool is_virtual_pipe) 705 { 706 struct dpu_hw_pipe *hw_pipe; 707 struct dpu_sspp_cfg *cfg; 708 709 if (!addr || !catalog) 710 return ERR_PTR(-EINVAL); 711 712 hw_pipe = kzalloc(sizeof(*hw_pipe), GFP_KERNEL); 713 if (!hw_pipe) 714 return ERR_PTR(-ENOMEM); 715 716 cfg = _sspp_offset(idx, addr, catalog, &hw_pipe->hw); 717 if (IS_ERR_OR_NULL(cfg)) { 718 kfree(hw_pipe); 719 return ERR_PTR(-EINVAL); 720 } 721 722 /* Assign ops */ 723 hw_pipe->catalog = catalog; 724 hw_pipe->mdp = &catalog->mdp[0]; 725 hw_pipe->idx = idx; 726 hw_pipe->cap = cfg; 727 _setup_layer_ops(hw_pipe, hw_pipe->cap->features); 728 729 dpu_hw_blk_init(&hw_pipe->base, DPU_HW_BLK_SSPP, idx, &dpu_hw_ops); 730 731 return hw_pipe; 732 } 733 734 void dpu_hw_sspp_destroy(struct dpu_hw_pipe *ctx) 735 { 736 if (ctx) 737 dpu_hw_blk_destroy(&ctx->base); 738 kfree(ctx); 739 } 740 741