1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 3 */ 4 5 #include "dpu_hwio.h" 6 #include "dpu_hw_catalog.h" 7 #include "dpu_hw_lm.h" 8 #include "dpu_hw_sspp.h" 9 #include "dpu_kms.h" 10 11 #define DPU_FETCH_CONFIG_RESET_VALUE 0x00000087 12 13 /* DPU_SSPP_SRC */ 14 #define SSPP_SRC_SIZE 0x00 15 #define SSPP_SRC_XY 0x08 16 #define SSPP_OUT_SIZE 0x0c 17 #define SSPP_OUT_XY 0x10 18 #define SSPP_SRC0_ADDR 0x14 19 #define SSPP_SRC1_ADDR 0x18 20 #define SSPP_SRC2_ADDR 0x1C 21 #define SSPP_SRC3_ADDR 0x20 22 #define SSPP_SRC_YSTRIDE0 0x24 23 #define SSPP_SRC_YSTRIDE1 0x28 24 #define SSPP_SRC_FORMAT 0x30 25 #define SSPP_SRC_UNPACK_PATTERN 0x34 26 #define SSPP_SRC_OP_MODE 0x38 27 28 /* SSPP_MULTIRECT*/ 29 #define SSPP_SRC_SIZE_REC1 0x16C 30 #define SSPP_SRC_XY_REC1 0x168 31 #define SSPP_OUT_SIZE_REC1 0x160 32 #define SSPP_OUT_XY_REC1 0x164 33 #define SSPP_SRC_FORMAT_REC1 0x174 34 #define SSPP_SRC_UNPACK_PATTERN_REC1 0x178 35 #define SSPP_SRC_OP_MODE_REC1 0x17C 36 #define SSPP_MULTIRECT_OPMODE 0x170 37 #define SSPP_SRC_CONSTANT_COLOR_REC1 0x180 38 #define SSPP_EXCL_REC_SIZE_REC1 0x184 39 #define SSPP_EXCL_REC_XY_REC1 0x188 40 41 #define MDSS_MDP_OP_DEINTERLACE BIT(22) 42 #define MDSS_MDP_OP_DEINTERLACE_ODD BIT(23) 43 #define MDSS_MDP_OP_IGC_ROM_1 BIT(18) 44 #define MDSS_MDP_OP_IGC_ROM_0 BIT(17) 45 #define MDSS_MDP_OP_IGC_EN BIT(16) 46 #define MDSS_MDP_OP_FLIP_UD BIT(14) 47 #define MDSS_MDP_OP_FLIP_LR BIT(13) 48 #define MDSS_MDP_OP_BWC_EN BIT(0) 49 #define MDSS_MDP_OP_PE_OVERRIDE BIT(31) 50 #define MDSS_MDP_OP_BWC_LOSSLESS (0 << 1) 51 #define MDSS_MDP_OP_BWC_Q_HIGH (1 << 1) 52 #define MDSS_MDP_OP_BWC_Q_MED (2 << 1) 53 54 #define SSPP_SRC_CONSTANT_COLOR 0x3c 55 #define SSPP_EXCL_REC_CTL 0x40 56 #define SSPP_UBWC_STATIC_CTRL 0x44 57 #define SSPP_FETCH_CONFIG 0x048 58 #define SSPP_DANGER_LUT 0x60 59 #define SSPP_SAFE_LUT 0x64 60 #define SSPP_CREQ_LUT 0x68 61 #define SSPP_QOS_CTRL 0x6C 62 #define SSPP_DECIMATION_CONFIG 0xB4 63 #define SSPP_SRC_ADDR_SW_STATUS 0x70 64 #define SSPP_CREQ_LUT_0 0x74 65 #define SSPP_CREQ_LUT_1 0x78 66 #define SSPP_SW_PIX_EXT_C0_LR 0x100 67 #define SSPP_SW_PIX_EXT_C0_TB 0x104 68 #define SSPP_SW_PIX_EXT_C0_REQ_PIXELS 0x108 69 #define SSPP_SW_PIX_EXT_C1C2_LR 0x110 70 #define SSPP_SW_PIX_EXT_C1C2_TB 0x114 71 #define SSPP_SW_PIX_EXT_C1C2_REQ_PIXELS 0x118 72 #define SSPP_SW_PIX_EXT_C3_LR 0x120 73 #define SSPP_SW_PIX_EXT_C3_TB 0x124 74 #define SSPP_SW_PIX_EXT_C3_REQ_PIXELS 0x128 75 #define SSPP_TRAFFIC_SHAPER 0x130 76 #define SSPP_CDP_CNTL 0x134 77 #define SSPP_UBWC_ERROR_STATUS 0x138 78 #define SSPP_TRAFFIC_SHAPER_PREFILL 0x150 79 #define SSPP_TRAFFIC_SHAPER_REC1_PREFILL 0x154 80 #define SSPP_TRAFFIC_SHAPER_REC1 0x158 81 #define SSPP_EXCL_REC_SIZE 0x1B4 82 #define SSPP_EXCL_REC_XY 0x1B8 83 #define SSPP_VIG_OP_MODE 0x0 84 #define SSPP_VIG_CSC_10_OP_MODE 0x0 85 #define SSPP_TRAFFIC_SHAPER_BPC_MAX 0xFF 86 87 /* SSPP_QOS_CTRL */ 88 #define SSPP_QOS_CTRL_VBLANK_EN BIT(16) 89 #define SSPP_QOS_CTRL_DANGER_SAFE_EN BIT(0) 90 #define SSPP_QOS_CTRL_DANGER_VBLANK_MASK 0x3 91 #define SSPP_QOS_CTRL_DANGER_VBLANK_OFF 4 92 #define SSPP_QOS_CTRL_CREQ_VBLANK_MASK 0x3 93 #define SSPP_QOS_CTRL_CREQ_VBLANK_OFF 20 94 95 /* DPU_SSPP_SCALER_QSEED2 */ 96 #define SCALE_CONFIG 0x04 97 #define COMP0_3_PHASE_STEP_X 0x10 98 #define COMP0_3_PHASE_STEP_Y 0x14 99 #define COMP1_2_PHASE_STEP_X 0x18 100 #define COMP1_2_PHASE_STEP_Y 0x1c 101 #define COMP0_3_INIT_PHASE_X 0x20 102 #define COMP0_3_INIT_PHASE_Y 0x24 103 #define COMP1_2_INIT_PHASE_X 0x28 104 #define COMP1_2_INIT_PHASE_Y 0x2C 105 #define VIG_0_QSEED2_SHARP 0x30 106 107 /* 108 * Definitions for ViG op modes 109 */ 110 #define VIG_OP_CSC_DST_DATAFMT BIT(19) 111 #define VIG_OP_CSC_SRC_DATAFMT BIT(18) 112 #define VIG_OP_CSC_EN BIT(17) 113 #define VIG_OP_MEM_PROT_CONT BIT(15) 114 #define VIG_OP_MEM_PROT_VAL BIT(14) 115 #define VIG_OP_MEM_PROT_SAT BIT(13) 116 #define VIG_OP_MEM_PROT_HUE BIT(12) 117 #define VIG_OP_HIST BIT(8) 118 #define VIG_OP_SKY_COL BIT(7) 119 #define VIG_OP_FOIL BIT(6) 120 #define VIG_OP_SKIN_COL BIT(5) 121 #define VIG_OP_PA_EN BIT(4) 122 #define VIG_OP_PA_SAT_ZERO_EXP BIT(2) 123 #define VIG_OP_MEM_PROT_BLEND BIT(1) 124 125 /* 126 * Definitions for CSC 10 op modes 127 */ 128 #define VIG_CSC_10_SRC_DATAFMT BIT(1) 129 #define VIG_CSC_10_EN BIT(0) 130 #define CSC_10BIT_OFFSET 4 131 132 /* traffic shaper clock in Hz */ 133 #define TS_CLK 19200000 134 135 136 static int _sspp_subblk_offset(struct dpu_hw_pipe *ctx, 137 int s_id, 138 u32 *idx) 139 { 140 int rc = 0; 141 const struct dpu_sspp_sub_blks *sblk; 142 143 if (!ctx || !ctx->cap || !ctx->cap->sblk) 144 return -EINVAL; 145 146 sblk = ctx->cap->sblk; 147 148 switch (s_id) { 149 case DPU_SSPP_SRC: 150 *idx = sblk->src_blk.base; 151 break; 152 case DPU_SSPP_SCALER_QSEED2: 153 case DPU_SSPP_SCALER_QSEED3: 154 case DPU_SSPP_SCALER_RGB: 155 *idx = sblk->scaler_blk.base; 156 break; 157 case DPU_SSPP_CSC: 158 case DPU_SSPP_CSC_10BIT: 159 *idx = sblk->csc_blk.base; 160 break; 161 default: 162 rc = -EINVAL; 163 } 164 165 return rc; 166 } 167 168 static void dpu_hw_sspp_setup_multirect(struct dpu_hw_pipe *ctx, 169 enum dpu_sspp_multirect_index index, 170 enum dpu_sspp_multirect_mode mode) 171 { 172 u32 mode_mask; 173 u32 idx; 174 175 if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx)) 176 return; 177 178 if (index == DPU_SSPP_RECT_SOLO) { 179 /** 180 * if rect index is RECT_SOLO, we cannot expect a 181 * virtual plane sharing the same SSPP id. So we go 182 * and disable multirect 183 */ 184 mode_mask = 0; 185 } else { 186 mode_mask = DPU_REG_READ(&ctx->hw, SSPP_MULTIRECT_OPMODE + idx); 187 mode_mask |= index; 188 if (mode == DPU_SSPP_MULTIRECT_TIME_MX) 189 mode_mask |= BIT(2); 190 else 191 mode_mask &= ~BIT(2); 192 } 193 194 DPU_REG_WRITE(&ctx->hw, SSPP_MULTIRECT_OPMODE + idx, mode_mask); 195 } 196 197 static void _sspp_setup_opmode(struct dpu_hw_pipe *ctx, 198 u32 mask, u8 en) 199 { 200 u32 idx; 201 u32 opmode; 202 203 if (!test_bit(DPU_SSPP_SCALER_QSEED2, &ctx->cap->features) || 204 _sspp_subblk_offset(ctx, DPU_SSPP_SCALER_QSEED2, &idx) || 205 !test_bit(DPU_SSPP_CSC, &ctx->cap->features)) 206 return; 207 208 opmode = DPU_REG_READ(&ctx->hw, SSPP_VIG_OP_MODE + idx); 209 210 if (en) 211 opmode |= mask; 212 else 213 opmode &= ~mask; 214 215 DPU_REG_WRITE(&ctx->hw, SSPP_VIG_OP_MODE + idx, opmode); 216 } 217 218 static void _sspp_setup_csc10_opmode(struct dpu_hw_pipe *ctx, 219 u32 mask, u8 en) 220 { 221 u32 idx; 222 u32 opmode; 223 224 if (_sspp_subblk_offset(ctx, DPU_SSPP_CSC_10BIT, &idx)) 225 return; 226 227 opmode = DPU_REG_READ(&ctx->hw, SSPP_VIG_CSC_10_OP_MODE + idx); 228 if (en) 229 opmode |= mask; 230 else 231 opmode &= ~mask; 232 233 DPU_REG_WRITE(&ctx->hw, SSPP_VIG_CSC_10_OP_MODE + idx, opmode); 234 } 235 236 /* 237 * Setup source pixel format, flip, 238 */ 239 static void dpu_hw_sspp_setup_format(struct dpu_hw_pipe *ctx, 240 const struct dpu_format *fmt, u32 flags, 241 enum dpu_sspp_multirect_index rect_mode) 242 { 243 struct dpu_hw_blk_reg_map *c; 244 u32 chroma_samp, unpack, src_format; 245 u32 opmode = 0; 246 u32 fast_clear = 0; 247 u32 op_mode_off, unpack_pat_off, format_off; 248 u32 idx; 249 250 if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx) || !fmt) 251 return; 252 253 if (rect_mode == DPU_SSPP_RECT_SOLO || rect_mode == DPU_SSPP_RECT_0) { 254 op_mode_off = SSPP_SRC_OP_MODE; 255 unpack_pat_off = SSPP_SRC_UNPACK_PATTERN; 256 format_off = SSPP_SRC_FORMAT; 257 } else { 258 op_mode_off = SSPP_SRC_OP_MODE_REC1; 259 unpack_pat_off = SSPP_SRC_UNPACK_PATTERN_REC1; 260 format_off = SSPP_SRC_FORMAT_REC1; 261 } 262 263 c = &ctx->hw; 264 opmode = DPU_REG_READ(c, op_mode_off + idx); 265 opmode &= ~(MDSS_MDP_OP_FLIP_LR | MDSS_MDP_OP_FLIP_UD | 266 MDSS_MDP_OP_BWC_EN | MDSS_MDP_OP_PE_OVERRIDE); 267 268 if (flags & DPU_SSPP_FLIP_LR) 269 opmode |= MDSS_MDP_OP_FLIP_LR; 270 if (flags & DPU_SSPP_FLIP_UD) 271 opmode |= MDSS_MDP_OP_FLIP_UD; 272 273 chroma_samp = fmt->chroma_sample; 274 if (flags & DPU_SSPP_SOURCE_ROTATED_90) { 275 if (chroma_samp == DPU_CHROMA_H2V1) 276 chroma_samp = DPU_CHROMA_H1V2; 277 else if (chroma_samp == DPU_CHROMA_H1V2) 278 chroma_samp = DPU_CHROMA_H2V1; 279 } 280 281 src_format = (chroma_samp << 23) | (fmt->fetch_planes << 19) | 282 (fmt->bits[C3_ALPHA] << 6) | (fmt->bits[C2_R_Cr] << 4) | 283 (fmt->bits[C1_B_Cb] << 2) | (fmt->bits[C0_G_Y] << 0); 284 285 if (flags & DPU_SSPP_ROT_90) 286 src_format |= BIT(11); /* ROT90 */ 287 288 if (fmt->alpha_enable && fmt->fetch_planes == DPU_PLANE_INTERLEAVED) 289 src_format |= BIT(8); /* SRCC3_EN */ 290 291 if (flags & DPU_SSPP_SOLID_FILL) 292 src_format |= BIT(22); 293 294 unpack = (fmt->element[3] << 24) | (fmt->element[2] << 16) | 295 (fmt->element[1] << 8) | (fmt->element[0] << 0); 296 src_format |= ((fmt->unpack_count - 1) << 12) | 297 (fmt->unpack_tight << 17) | 298 (fmt->unpack_align_msb << 18) | 299 ((fmt->bpp - 1) << 9); 300 301 if (fmt->fetch_mode != DPU_FETCH_LINEAR) { 302 if (DPU_FORMAT_IS_UBWC(fmt)) 303 opmode |= MDSS_MDP_OP_BWC_EN; 304 src_format |= (fmt->fetch_mode & 3) << 30; /*FRAME_FORMAT */ 305 DPU_REG_WRITE(c, SSPP_FETCH_CONFIG, 306 DPU_FETCH_CONFIG_RESET_VALUE | 307 ctx->mdp->highest_bank_bit << 18); 308 switch (ctx->catalog->caps->ubwc_version) { 309 case DPU_HW_UBWC_VER_10: 310 /* TODO: UBWC v1 case */ 311 break; 312 case DPU_HW_UBWC_VER_20: 313 fast_clear = fmt->alpha_enable ? BIT(31) : 0; 314 DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, 315 fast_clear | (ctx->mdp->ubwc_swizzle) | 316 (ctx->mdp->highest_bank_bit << 4)); 317 break; 318 case DPU_HW_UBWC_VER_30: 319 DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, 320 BIT(30) | (ctx->mdp->ubwc_swizzle) | 321 (ctx->mdp->highest_bank_bit << 4)); 322 break; 323 case DPU_HW_UBWC_VER_40: 324 DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, 325 DPU_FORMAT_IS_YUV(fmt) ? 0 : BIT(30)); 326 break; 327 } 328 } 329 330 opmode |= MDSS_MDP_OP_PE_OVERRIDE; 331 332 /* if this is YUV pixel format, enable CSC */ 333 if (DPU_FORMAT_IS_YUV(fmt)) 334 src_format |= BIT(15); 335 336 if (DPU_FORMAT_IS_DX(fmt)) 337 src_format |= BIT(14); 338 339 /* update scaler opmode, if appropriate */ 340 if (test_bit(DPU_SSPP_CSC, &ctx->cap->features)) 341 _sspp_setup_opmode(ctx, VIG_OP_CSC_EN | VIG_OP_CSC_SRC_DATAFMT, 342 DPU_FORMAT_IS_YUV(fmt)); 343 else if (test_bit(DPU_SSPP_CSC_10BIT, &ctx->cap->features)) 344 _sspp_setup_csc10_opmode(ctx, 345 VIG_CSC_10_EN | VIG_CSC_10_SRC_DATAFMT, 346 DPU_FORMAT_IS_YUV(fmt)); 347 348 DPU_REG_WRITE(c, format_off + idx, src_format); 349 DPU_REG_WRITE(c, unpack_pat_off + idx, unpack); 350 DPU_REG_WRITE(c, op_mode_off + idx, opmode); 351 352 /* clear previous UBWC error */ 353 DPU_REG_WRITE(c, SSPP_UBWC_ERROR_STATUS + idx, BIT(31)); 354 } 355 356 static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_pipe *ctx, 357 struct dpu_hw_pixel_ext *pe_ext) 358 { 359 struct dpu_hw_blk_reg_map *c; 360 u8 color; 361 u32 lr_pe[4], tb_pe[4], tot_req_pixels[4]; 362 const u32 bytemask = 0xff; 363 const u32 shortmask = 0xffff; 364 u32 idx; 365 366 if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx) || !pe_ext) 367 return; 368 369 c = &ctx->hw; 370 371 /* program SW pixel extension override for all pipes*/ 372 for (color = 0; color < DPU_MAX_PLANES; color++) { 373 /* color 2 has the same set of registers as color 1 */ 374 if (color == 2) 375 continue; 376 377 lr_pe[color] = ((pe_ext->right_ftch[color] & bytemask) << 24)| 378 ((pe_ext->right_rpt[color] & bytemask) << 16)| 379 ((pe_ext->left_ftch[color] & bytemask) << 8)| 380 (pe_ext->left_rpt[color] & bytemask); 381 382 tb_pe[color] = ((pe_ext->btm_ftch[color] & bytemask) << 24)| 383 ((pe_ext->btm_rpt[color] & bytemask) << 16)| 384 ((pe_ext->top_ftch[color] & bytemask) << 8)| 385 (pe_ext->top_rpt[color] & bytemask); 386 387 tot_req_pixels[color] = (((pe_ext->roi_h[color] + 388 pe_ext->num_ext_pxls_top[color] + 389 pe_ext->num_ext_pxls_btm[color]) & shortmask) << 16) | 390 ((pe_ext->roi_w[color] + 391 pe_ext->num_ext_pxls_left[color] + 392 pe_ext->num_ext_pxls_right[color]) & shortmask); 393 } 394 395 /* color 0 */ 396 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C0_LR + idx, lr_pe[0]); 397 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C0_TB + idx, tb_pe[0]); 398 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C0_REQ_PIXELS + idx, 399 tot_req_pixels[0]); 400 401 /* color 1 and color 2 */ 402 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C1C2_LR + idx, lr_pe[1]); 403 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C1C2_TB + idx, tb_pe[1]); 404 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C1C2_REQ_PIXELS + idx, 405 tot_req_pixels[1]); 406 407 /* color 3 */ 408 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C3_LR + idx, lr_pe[3]); 409 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C3_TB + idx, lr_pe[3]); 410 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C3_REQ_PIXELS + idx, 411 tot_req_pixels[3]); 412 } 413 414 static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_pipe *ctx, 415 struct dpu_hw_pipe_cfg *sspp, 416 struct dpu_hw_pixel_ext *pe, 417 void *scaler_cfg) 418 { 419 u32 idx; 420 struct dpu_hw_scaler3_cfg *scaler3_cfg = scaler_cfg; 421 422 (void)pe; 423 if (_sspp_subblk_offset(ctx, DPU_SSPP_SCALER_QSEED3, &idx) || !sspp 424 || !scaler3_cfg) 425 return; 426 427 dpu_hw_setup_scaler3(&ctx->hw, scaler3_cfg, idx, 428 ctx->cap->sblk->scaler_blk.version, 429 sspp->layout.format); 430 } 431 432 static u32 _dpu_hw_sspp_get_scaler3_ver(struct dpu_hw_pipe *ctx) 433 { 434 u32 idx; 435 436 if (!ctx || _sspp_subblk_offset(ctx, DPU_SSPP_SCALER_QSEED3, &idx)) 437 return 0; 438 439 return dpu_hw_get_scaler3_ver(&ctx->hw, idx); 440 } 441 442 /* 443 * dpu_hw_sspp_setup_rects() 444 */ 445 static void dpu_hw_sspp_setup_rects(struct dpu_hw_pipe *ctx, 446 struct dpu_hw_pipe_cfg *cfg, 447 enum dpu_sspp_multirect_index rect_index) 448 { 449 struct dpu_hw_blk_reg_map *c; 450 u32 src_size, src_xy, dst_size, dst_xy, ystride0, ystride1; 451 u32 src_size_off, src_xy_off, out_size_off, out_xy_off; 452 u32 idx; 453 454 if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx) || !cfg) 455 return; 456 457 c = &ctx->hw; 458 459 if (rect_index == DPU_SSPP_RECT_SOLO || rect_index == DPU_SSPP_RECT_0) { 460 src_size_off = SSPP_SRC_SIZE; 461 src_xy_off = SSPP_SRC_XY; 462 out_size_off = SSPP_OUT_SIZE; 463 out_xy_off = SSPP_OUT_XY; 464 } else { 465 src_size_off = SSPP_SRC_SIZE_REC1; 466 src_xy_off = SSPP_SRC_XY_REC1; 467 out_size_off = SSPP_OUT_SIZE_REC1; 468 out_xy_off = SSPP_OUT_XY_REC1; 469 } 470 471 472 /* src and dest rect programming */ 473 src_xy = (cfg->src_rect.y1 << 16) | cfg->src_rect.x1; 474 src_size = (drm_rect_height(&cfg->src_rect) << 16) | 475 drm_rect_width(&cfg->src_rect); 476 dst_xy = (cfg->dst_rect.y1 << 16) | cfg->dst_rect.x1; 477 dst_size = (drm_rect_height(&cfg->dst_rect) << 16) | 478 drm_rect_width(&cfg->dst_rect); 479 480 if (rect_index == DPU_SSPP_RECT_SOLO) { 481 ystride0 = (cfg->layout.plane_pitch[0]) | 482 (cfg->layout.plane_pitch[1] << 16); 483 ystride1 = (cfg->layout.plane_pitch[2]) | 484 (cfg->layout.plane_pitch[3] << 16); 485 } else { 486 ystride0 = DPU_REG_READ(c, SSPP_SRC_YSTRIDE0 + idx); 487 ystride1 = DPU_REG_READ(c, SSPP_SRC_YSTRIDE1 + idx); 488 489 if (rect_index == DPU_SSPP_RECT_0) { 490 ystride0 = (ystride0 & 0xFFFF0000) | 491 (cfg->layout.plane_pitch[0] & 0x0000FFFF); 492 ystride1 = (ystride1 & 0xFFFF0000)| 493 (cfg->layout.plane_pitch[2] & 0x0000FFFF); 494 } else { 495 ystride0 = (ystride0 & 0x0000FFFF) | 496 ((cfg->layout.plane_pitch[0] << 16) & 497 0xFFFF0000); 498 ystride1 = (ystride1 & 0x0000FFFF) | 499 ((cfg->layout.plane_pitch[2] << 16) & 500 0xFFFF0000); 501 } 502 } 503 504 /* rectangle register programming */ 505 DPU_REG_WRITE(c, src_size_off + idx, src_size); 506 DPU_REG_WRITE(c, src_xy_off + idx, src_xy); 507 DPU_REG_WRITE(c, out_size_off + idx, dst_size); 508 DPU_REG_WRITE(c, out_xy_off + idx, dst_xy); 509 510 DPU_REG_WRITE(c, SSPP_SRC_YSTRIDE0 + idx, ystride0); 511 DPU_REG_WRITE(c, SSPP_SRC_YSTRIDE1 + idx, ystride1); 512 } 513 514 static void dpu_hw_sspp_setup_sourceaddress(struct dpu_hw_pipe *ctx, 515 struct dpu_hw_pipe_cfg *cfg, 516 enum dpu_sspp_multirect_index rect_mode) 517 { 518 int i; 519 u32 idx; 520 521 if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx)) 522 return; 523 524 if (rect_mode == DPU_SSPP_RECT_SOLO) { 525 for (i = 0; i < ARRAY_SIZE(cfg->layout.plane_addr); i++) 526 DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx + i * 0x4, 527 cfg->layout.plane_addr[i]); 528 } else if (rect_mode == DPU_SSPP_RECT_0) { 529 DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx, 530 cfg->layout.plane_addr[0]); 531 DPU_REG_WRITE(&ctx->hw, SSPP_SRC2_ADDR + idx, 532 cfg->layout.plane_addr[2]); 533 } else { 534 DPU_REG_WRITE(&ctx->hw, SSPP_SRC1_ADDR + idx, 535 cfg->layout.plane_addr[0]); 536 DPU_REG_WRITE(&ctx->hw, SSPP_SRC3_ADDR + idx, 537 cfg->layout.plane_addr[2]); 538 } 539 } 540 541 static void dpu_hw_sspp_setup_csc(struct dpu_hw_pipe *ctx, 542 struct dpu_csc_cfg *data) 543 { 544 u32 idx; 545 bool csc10 = false; 546 547 if (_sspp_subblk_offset(ctx, DPU_SSPP_CSC, &idx) || !data) 548 return; 549 550 if (test_bit(DPU_SSPP_CSC_10BIT, &ctx->cap->features)) { 551 idx += CSC_10BIT_OFFSET; 552 csc10 = true; 553 } 554 555 dpu_hw_csc_setup(&ctx->hw, idx, data, csc10); 556 } 557 558 static void dpu_hw_sspp_setup_solidfill(struct dpu_hw_pipe *ctx, u32 color, enum 559 dpu_sspp_multirect_index rect_index) 560 { 561 u32 idx; 562 563 if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx)) 564 return; 565 566 if (rect_index == DPU_SSPP_RECT_SOLO || rect_index == DPU_SSPP_RECT_0) 567 DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR + idx, color); 568 else 569 DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR_REC1 + idx, 570 color); 571 } 572 573 static void dpu_hw_sspp_setup_danger_safe_lut(struct dpu_hw_pipe *ctx, 574 struct dpu_hw_pipe_qos_cfg *cfg) 575 { 576 u32 idx; 577 578 if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx)) 579 return; 580 581 DPU_REG_WRITE(&ctx->hw, SSPP_DANGER_LUT + idx, cfg->danger_lut); 582 DPU_REG_WRITE(&ctx->hw, SSPP_SAFE_LUT + idx, cfg->safe_lut); 583 } 584 585 static void dpu_hw_sspp_setup_creq_lut(struct dpu_hw_pipe *ctx, 586 struct dpu_hw_pipe_qos_cfg *cfg) 587 { 588 u32 idx; 589 590 if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx)) 591 return; 592 593 if (ctx->cap && test_bit(DPU_SSPP_QOS_8LVL, &ctx->cap->features)) { 594 DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT_0 + idx, cfg->creq_lut); 595 DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT_1 + idx, 596 cfg->creq_lut >> 32); 597 } else { 598 DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT + idx, cfg->creq_lut); 599 } 600 } 601 602 static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_pipe *ctx, 603 struct dpu_hw_pipe_qos_cfg *cfg) 604 { 605 u32 idx; 606 u32 qos_ctrl = 0; 607 608 if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx)) 609 return; 610 611 if (cfg->vblank_en) { 612 qos_ctrl |= ((cfg->creq_vblank & 613 SSPP_QOS_CTRL_CREQ_VBLANK_MASK) << 614 SSPP_QOS_CTRL_CREQ_VBLANK_OFF); 615 qos_ctrl |= ((cfg->danger_vblank & 616 SSPP_QOS_CTRL_DANGER_VBLANK_MASK) << 617 SSPP_QOS_CTRL_DANGER_VBLANK_OFF); 618 qos_ctrl |= SSPP_QOS_CTRL_VBLANK_EN; 619 } 620 621 if (cfg->danger_safe_en) 622 qos_ctrl |= SSPP_QOS_CTRL_DANGER_SAFE_EN; 623 624 DPU_REG_WRITE(&ctx->hw, SSPP_QOS_CTRL + idx, qos_ctrl); 625 } 626 627 static void dpu_hw_sspp_setup_cdp(struct dpu_hw_pipe *ctx, 628 struct dpu_hw_pipe_cdp_cfg *cfg) 629 { 630 u32 idx; 631 u32 cdp_cntl = 0; 632 633 if (!ctx || !cfg) 634 return; 635 636 if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx)) 637 return; 638 639 if (cfg->enable) 640 cdp_cntl |= BIT(0); 641 if (cfg->ubwc_meta_enable) 642 cdp_cntl |= BIT(1); 643 if (cfg->tile_amortize_enable) 644 cdp_cntl |= BIT(2); 645 if (cfg->preload_ahead == DPU_SSPP_CDP_PRELOAD_AHEAD_64) 646 cdp_cntl |= BIT(3); 647 648 DPU_REG_WRITE(&ctx->hw, SSPP_CDP_CNTL, cdp_cntl); 649 } 650 651 static void _setup_layer_ops(struct dpu_hw_pipe *c, 652 unsigned long features) 653 { 654 if (test_bit(DPU_SSPP_SRC, &features)) { 655 c->ops.setup_format = dpu_hw_sspp_setup_format; 656 c->ops.setup_rects = dpu_hw_sspp_setup_rects; 657 c->ops.setup_sourceaddress = dpu_hw_sspp_setup_sourceaddress; 658 c->ops.setup_solidfill = dpu_hw_sspp_setup_solidfill; 659 c->ops.setup_pe = dpu_hw_sspp_setup_pe_config; 660 } 661 662 if (test_bit(DPU_SSPP_QOS, &features)) { 663 c->ops.setup_danger_safe_lut = 664 dpu_hw_sspp_setup_danger_safe_lut; 665 c->ops.setup_creq_lut = dpu_hw_sspp_setup_creq_lut; 666 c->ops.setup_qos_ctrl = dpu_hw_sspp_setup_qos_ctrl; 667 } 668 669 if (test_bit(DPU_SSPP_CSC, &features) || 670 test_bit(DPU_SSPP_CSC_10BIT, &features)) 671 c->ops.setup_csc = dpu_hw_sspp_setup_csc; 672 673 if (test_bit(DPU_SSPP_SMART_DMA_V1, &c->cap->features) || 674 test_bit(DPU_SSPP_SMART_DMA_V2, &c->cap->features)) 675 c->ops.setup_multirect = dpu_hw_sspp_setup_multirect; 676 677 if (test_bit(DPU_SSPP_SCALER_QSEED3, &features) || 678 test_bit(DPU_SSPP_SCALER_QSEED3LITE, &features) || 679 test_bit(DPU_SSPP_SCALER_QSEED4, &features)) { 680 c->ops.setup_scaler = _dpu_hw_sspp_setup_scaler3; 681 c->ops.get_scaler_ver = _dpu_hw_sspp_get_scaler3_ver; 682 } 683 684 if (test_bit(DPU_SSPP_CDP, &features)) 685 c->ops.setup_cdp = dpu_hw_sspp_setup_cdp; 686 } 687 688 static const struct dpu_sspp_cfg *_sspp_offset(enum dpu_sspp sspp, 689 void __iomem *addr, 690 struct dpu_mdss_cfg *catalog, 691 struct dpu_hw_blk_reg_map *b) 692 { 693 int i; 694 695 if ((sspp < SSPP_MAX) && catalog && addr && b) { 696 for (i = 0; i < catalog->sspp_count; i++) { 697 if (sspp == catalog->sspp[i].id) { 698 b->base_off = addr; 699 b->blk_off = catalog->sspp[i].base; 700 b->length = catalog->sspp[i].len; 701 b->hwversion = catalog->hwversion; 702 b->log_mask = DPU_DBG_MASK_SSPP; 703 return &catalog->sspp[i]; 704 } 705 } 706 } 707 708 return ERR_PTR(-ENOMEM); 709 } 710 711 struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx, 712 void __iomem *addr, struct dpu_mdss_cfg *catalog, 713 bool is_virtual_pipe) 714 { 715 struct dpu_hw_pipe *hw_pipe; 716 const struct dpu_sspp_cfg *cfg; 717 718 if (!addr || !catalog) 719 return ERR_PTR(-EINVAL); 720 721 hw_pipe = kzalloc(sizeof(*hw_pipe), GFP_KERNEL); 722 if (!hw_pipe) 723 return ERR_PTR(-ENOMEM); 724 725 cfg = _sspp_offset(idx, addr, catalog, &hw_pipe->hw); 726 if (IS_ERR_OR_NULL(cfg)) { 727 kfree(hw_pipe); 728 return ERR_PTR(-EINVAL); 729 } 730 731 /* Assign ops */ 732 hw_pipe->catalog = catalog; 733 hw_pipe->mdp = &catalog->mdp[0]; 734 hw_pipe->idx = idx; 735 hw_pipe->cap = cfg; 736 _setup_layer_ops(hw_pipe, hw_pipe->cap->features); 737 738 return hw_pipe; 739 } 740 741 void dpu_hw_sspp_destroy(struct dpu_hw_pipe *ctx) 742 { 743 kfree(ctx); 744 } 745 746