1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
3  */
4 
5 #include "dpu_hwio.h"
6 #include "dpu_hw_catalog.h"
7 #include "dpu_hw_lm.h"
8 #include "dpu_hw_sspp.h"
9 #include "dpu_kms.h"
10 
11 #include <drm/drm_file.h>
12 
13 #define DPU_FETCH_CONFIG_RESET_VALUE   0x00000087
14 
15 /* SSPP registers */
16 #define SSPP_SRC_SIZE                      0x00
17 #define SSPP_SRC_XY                        0x08
18 #define SSPP_OUT_SIZE                      0x0c
19 #define SSPP_OUT_XY                        0x10
20 #define SSPP_SRC0_ADDR                     0x14
21 #define SSPP_SRC1_ADDR                     0x18
22 #define SSPP_SRC2_ADDR                     0x1C
23 #define SSPP_SRC3_ADDR                     0x20
24 #define SSPP_SRC_YSTRIDE0                  0x24
25 #define SSPP_SRC_YSTRIDE1                  0x28
26 #define SSPP_SRC_FORMAT                    0x30
27 #define SSPP_SRC_UNPACK_PATTERN            0x34
28 #define SSPP_SRC_OP_MODE                   0x38
29 #define SSPP_SRC_CONSTANT_COLOR            0x3c
30 #define SSPP_EXCL_REC_CTL                  0x40
31 #define SSPP_UBWC_STATIC_CTRL              0x44
32 #define SSPP_FETCH_CONFIG                  0x48
33 #define SSPP_DANGER_LUT                    0x60
34 #define SSPP_SAFE_LUT                      0x64
35 #define SSPP_CREQ_LUT                      0x68
36 #define SSPP_QOS_CTRL                      0x6C
37 #define SSPP_SRC_ADDR_SW_STATUS            0x70
38 #define SSPP_CREQ_LUT_0                    0x74
39 #define SSPP_CREQ_LUT_1                    0x78
40 #define SSPP_DECIMATION_CONFIG             0xB4
41 #define SSPP_SW_PIX_EXT_C0_LR              0x100
42 #define SSPP_SW_PIX_EXT_C0_TB              0x104
43 #define SSPP_SW_PIX_EXT_C0_REQ_PIXELS      0x108
44 #define SSPP_SW_PIX_EXT_C1C2_LR            0x110
45 #define SSPP_SW_PIX_EXT_C1C2_TB            0x114
46 #define SSPP_SW_PIX_EXT_C1C2_REQ_PIXELS    0x118
47 #define SSPP_SW_PIX_EXT_C3_LR              0x120
48 #define SSPP_SW_PIX_EXT_C3_TB              0x124
49 #define SSPP_SW_PIX_EXT_C3_REQ_PIXELS      0x128
50 #define SSPP_TRAFFIC_SHAPER                0x130
51 #define SSPP_CDP_CNTL                      0x134
52 #define SSPP_UBWC_ERROR_STATUS             0x138
53 #define SSPP_CDP_CNTL_REC1                 0x13c
54 #define SSPP_TRAFFIC_SHAPER_PREFILL        0x150
55 #define SSPP_TRAFFIC_SHAPER_REC1_PREFILL   0x154
56 #define SSPP_TRAFFIC_SHAPER_REC1           0x158
57 #define SSPP_OUT_SIZE_REC1                 0x160
58 #define SSPP_OUT_XY_REC1                   0x164
59 #define SSPP_SRC_XY_REC1                   0x168
60 #define SSPP_SRC_SIZE_REC1                 0x16C
61 #define SSPP_MULTIRECT_OPMODE              0x170
62 #define SSPP_SRC_FORMAT_REC1               0x174
63 #define SSPP_SRC_UNPACK_PATTERN_REC1       0x178
64 #define SSPP_SRC_OP_MODE_REC1              0x17C
65 #define SSPP_SRC_CONSTANT_COLOR_REC1       0x180
66 #define SSPP_EXCL_REC_SIZE_REC1            0x184
67 #define SSPP_EXCL_REC_XY_REC1              0x188
68 #define SSPP_EXCL_REC_SIZE                 0x1B4
69 #define SSPP_EXCL_REC_XY                   0x1B8
70 
71 /* SSPP_SRC_OP_MODE & OP_MODE_REC1 */
72 #define MDSS_MDP_OP_DEINTERLACE            BIT(22)
73 #define MDSS_MDP_OP_DEINTERLACE_ODD        BIT(23)
74 #define MDSS_MDP_OP_IGC_ROM_1              BIT(18)
75 #define MDSS_MDP_OP_IGC_ROM_0              BIT(17)
76 #define MDSS_MDP_OP_IGC_EN                 BIT(16)
77 #define MDSS_MDP_OP_FLIP_UD                BIT(14)
78 #define MDSS_MDP_OP_FLIP_LR                BIT(13)
79 #define MDSS_MDP_OP_BWC_EN                 BIT(0)
80 #define MDSS_MDP_OP_PE_OVERRIDE            BIT(31)
81 #define MDSS_MDP_OP_BWC_LOSSLESS           (0 << 1)
82 #define MDSS_MDP_OP_BWC_Q_HIGH             (1 << 1)
83 #define MDSS_MDP_OP_BWC_Q_MED              (2 << 1)
84 
85 /* SSPP_QOS_CTRL */
86 #define SSPP_QOS_CTRL_VBLANK_EN            BIT(16)
87 #define SSPP_QOS_CTRL_DANGER_SAFE_EN       BIT(0)
88 #define SSPP_QOS_CTRL_DANGER_VBLANK_MASK   0x3
89 #define SSPP_QOS_CTRL_DANGER_VBLANK_OFF    4
90 #define SSPP_QOS_CTRL_CREQ_VBLANK_MASK     0x3
91 #define SSPP_QOS_CTRL_CREQ_VBLANK_OFF      20
92 
93 /* DPU_SSPP_SCALER_QSEED2 */
94 #define SSPP_VIG_OP_MODE                   0x0
95 #define SCALE_CONFIG                       0x04
96 #define COMP0_3_PHASE_STEP_X               0x10
97 #define COMP0_3_PHASE_STEP_Y               0x14
98 #define COMP1_2_PHASE_STEP_X               0x18
99 #define COMP1_2_PHASE_STEP_Y               0x1c
100 #define COMP0_3_INIT_PHASE_X               0x20
101 #define COMP0_3_INIT_PHASE_Y               0x24
102 #define COMP1_2_INIT_PHASE_X               0x28
103 #define COMP1_2_INIT_PHASE_Y               0x2C
104 #define VIG_0_QSEED2_SHARP                 0x30
105 
106 /* SSPP_TRAFFIC_SHAPER and _REC1 */
107 #define SSPP_TRAFFIC_SHAPER_BPC_MAX        0xFF
108 
109 /*
110  * Definitions for ViG op modes
111  */
112 #define VIG_OP_CSC_DST_DATAFMT BIT(19)
113 #define VIG_OP_CSC_SRC_DATAFMT BIT(18)
114 #define VIG_OP_CSC_EN          BIT(17)
115 #define VIG_OP_MEM_PROT_CONT   BIT(15)
116 #define VIG_OP_MEM_PROT_VAL    BIT(14)
117 #define VIG_OP_MEM_PROT_SAT    BIT(13)
118 #define VIG_OP_MEM_PROT_HUE    BIT(12)
119 #define VIG_OP_HIST            BIT(8)
120 #define VIG_OP_SKY_COL         BIT(7)
121 #define VIG_OP_FOIL            BIT(6)
122 #define VIG_OP_SKIN_COL        BIT(5)
123 #define VIG_OP_PA_EN           BIT(4)
124 #define VIG_OP_PA_SAT_ZERO_EXP BIT(2)
125 #define VIG_OP_MEM_PROT_BLEND  BIT(1)
126 
127 /*
128  * Definitions for CSC 10 op modes
129  */
130 #define SSPP_VIG_CSC_10_OP_MODE            0x0
131 #define VIG_CSC_10_SRC_DATAFMT BIT(1)
132 #define VIG_CSC_10_EN          BIT(0)
133 #define CSC_10BIT_OFFSET       4
134 
135 /* traffic shaper clock in Hz */
136 #define TS_CLK			19200000
137 
138 
139 static void dpu_hw_sspp_setup_multirect(struct dpu_sw_pipe *pipe)
140 {
141 	struct dpu_hw_sspp *ctx = pipe->sspp;
142 	u32 mode_mask;
143 
144 	if (!ctx)
145 		return;
146 
147 	if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
148 		/**
149 		 * if rect index is RECT_SOLO, we cannot expect a
150 		 * virtual plane sharing the same SSPP id. So we go
151 		 * and disable multirect
152 		 */
153 		mode_mask = 0;
154 	} else {
155 		mode_mask = DPU_REG_READ(&ctx->hw, SSPP_MULTIRECT_OPMODE);
156 		mode_mask |= pipe->multirect_index;
157 		if (pipe->multirect_mode == DPU_SSPP_MULTIRECT_TIME_MX)
158 			mode_mask |= BIT(2);
159 		else
160 			mode_mask &= ~BIT(2);
161 	}
162 
163 	DPU_REG_WRITE(&ctx->hw, SSPP_MULTIRECT_OPMODE, mode_mask);
164 }
165 
166 static void _sspp_setup_opmode(struct dpu_hw_sspp *ctx,
167 		u32 mask, u8 en)
168 {
169 	const struct dpu_sspp_sub_blks *sblk = ctx->cap->sblk;
170 	u32 opmode;
171 
172 	if (!test_bit(DPU_SSPP_SCALER_QSEED2, &ctx->cap->features) ||
173 		!test_bit(DPU_SSPP_CSC, &ctx->cap->features))
174 		return;
175 
176 	opmode = DPU_REG_READ(&ctx->hw, sblk->scaler_blk.base + SSPP_VIG_OP_MODE);
177 
178 	if (en)
179 		opmode |= mask;
180 	else
181 		opmode &= ~mask;
182 
183 	DPU_REG_WRITE(&ctx->hw, sblk->scaler_blk.base + SSPP_VIG_OP_MODE, opmode);
184 }
185 
186 static void _sspp_setup_csc10_opmode(struct dpu_hw_sspp *ctx,
187 		u32 mask, u8 en)
188 {
189 	const struct dpu_sspp_sub_blks *sblk = ctx->cap->sblk;
190 	u32 opmode;
191 
192 	opmode = DPU_REG_READ(&ctx->hw, sblk->csc_blk.base + SSPP_VIG_CSC_10_OP_MODE);
193 	if (en)
194 		opmode |= mask;
195 	else
196 		opmode &= ~mask;
197 
198 	DPU_REG_WRITE(&ctx->hw, sblk->csc_blk.base + SSPP_VIG_CSC_10_OP_MODE, opmode);
199 }
200 
201 /*
202  * Setup source pixel format, flip,
203  */
204 static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
205 		const struct dpu_format *fmt, u32 flags)
206 {
207 	struct dpu_hw_sspp *ctx = pipe->sspp;
208 	struct dpu_hw_blk_reg_map *c;
209 	u32 chroma_samp, unpack, src_format;
210 	u32 opmode = 0;
211 	u32 fast_clear = 0;
212 	u32 op_mode_off, unpack_pat_off, format_off;
213 
214 	if (!ctx || !fmt)
215 		return;
216 
217 	if (pipe->multirect_index == DPU_SSPP_RECT_SOLO ||
218 	    pipe->multirect_index == DPU_SSPP_RECT_0) {
219 		op_mode_off = SSPP_SRC_OP_MODE;
220 		unpack_pat_off = SSPP_SRC_UNPACK_PATTERN;
221 		format_off = SSPP_SRC_FORMAT;
222 	} else {
223 		op_mode_off = SSPP_SRC_OP_MODE_REC1;
224 		unpack_pat_off = SSPP_SRC_UNPACK_PATTERN_REC1;
225 		format_off = SSPP_SRC_FORMAT_REC1;
226 	}
227 
228 	c = &ctx->hw;
229 	opmode = DPU_REG_READ(c, op_mode_off);
230 	opmode &= ~(MDSS_MDP_OP_FLIP_LR | MDSS_MDP_OP_FLIP_UD |
231 			MDSS_MDP_OP_BWC_EN | MDSS_MDP_OP_PE_OVERRIDE);
232 
233 	if (flags & DPU_SSPP_FLIP_LR)
234 		opmode |= MDSS_MDP_OP_FLIP_LR;
235 	if (flags & DPU_SSPP_FLIP_UD)
236 		opmode |= MDSS_MDP_OP_FLIP_UD;
237 
238 	chroma_samp = fmt->chroma_sample;
239 	if (flags & DPU_SSPP_SOURCE_ROTATED_90) {
240 		if (chroma_samp == DPU_CHROMA_H2V1)
241 			chroma_samp = DPU_CHROMA_H1V2;
242 		else if (chroma_samp == DPU_CHROMA_H1V2)
243 			chroma_samp = DPU_CHROMA_H2V1;
244 	}
245 
246 	src_format = (chroma_samp << 23) | (fmt->fetch_planes << 19) |
247 		(fmt->bits[C3_ALPHA] << 6) | (fmt->bits[C2_R_Cr] << 4) |
248 		(fmt->bits[C1_B_Cb] << 2) | (fmt->bits[C0_G_Y] << 0);
249 
250 	if (flags & DPU_SSPP_ROT_90)
251 		src_format |= BIT(11); /* ROT90 */
252 
253 	if (fmt->alpha_enable && fmt->fetch_planes == DPU_PLANE_INTERLEAVED)
254 		src_format |= BIT(8); /* SRCC3_EN */
255 
256 	if (flags & DPU_SSPP_SOLID_FILL)
257 		src_format |= BIT(22);
258 
259 	unpack = (fmt->element[3] << 24) | (fmt->element[2] << 16) |
260 		(fmt->element[1] << 8) | (fmt->element[0] << 0);
261 	src_format |= ((fmt->unpack_count - 1) << 12) |
262 		(fmt->unpack_tight << 17) |
263 		(fmt->unpack_align_msb << 18) |
264 		((fmt->bpp - 1) << 9);
265 
266 	if (fmt->fetch_mode != DPU_FETCH_LINEAR) {
267 		if (DPU_FORMAT_IS_UBWC(fmt))
268 			opmode |= MDSS_MDP_OP_BWC_EN;
269 		src_format |= (fmt->fetch_mode & 3) << 30; /*FRAME_FORMAT */
270 		DPU_REG_WRITE(c, SSPP_FETCH_CONFIG,
271 			DPU_FETCH_CONFIG_RESET_VALUE |
272 			ctx->ubwc->highest_bank_bit << 18);
273 		switch (ctx->ubwc->ubwc_version) {
274 		case DPU_HW_UBWC_VER_10:
275 			fast_clear = fmt->alpha_enable ? BIT(31) : 0;
276 			DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
277 					fast_clear | (ctx->ubwc->ubwc_swizzle & 0x1) |
278 					BIT(8) |
279 					(ctx->ubwc->highest_bank_bit << 4));
280 			break;
281 		case DPU_HW_UBWC_VER_20:
282 			fast_clear = fmt->alpha_enable ? BIT(31) : 0;
283 			DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
284 					fast_clear | (ctx->ubwc->ubwc_swizzle) |
285 					(ctx->ubwc->highest_bank_bit << 4));
286 			break;
287 		case DPU_HW_UBWC_VER_30:
288 			DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
289 					BIT(30) | (ctx->ubwc->ubwc_swizzle) |
290 					(ctx->ubwc->highest_bank_bit << 4));
291 			break;
292 		case DPU_HW_UBWC_VER_40:
293 			DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
294 					DPU_FORMAT_IS_YUV(fmt) ? 0 : BIT(30));
295 			break;
296 		}
297 	}
298 
299 	opmode |= MDSS_MDP_OP_PE_OVERRIDE;
300 
301 	/* if this is YUV pixel format, enable CSC */
302 	if (DPU_FORMAT_IS_YUV(fmt))
303 		src_format |= BIT(15);
304 
305 	if (DPU_FORMAT_IS_DX(fmt))
306 		src_format |= BIT(14);
307 
308 	/* update scaler opmode, if appropriate */
309 	if (test_bit(DPU_SSPP_CSC, &ctx->cap->features))
310 		_sspp_setup_opmode(ctx, VIG_OP_CSC_EN | VIG_OP_CSC_SRC_DATAFMT,
311 			DPU_FORMAT_IS_YUV(fmt));
312 	else if (test_bit(DPU_SSPP_CSC_10BIT, &ctx->cap->features))
313 		_sspp_setup_csc10_opmode(ctx,
314 			VIG_CSC_10_EN | VIG_CSC_10_SRC_DATAFMT,
315 			DPU_FORMAT_IS_YUV(fmt));
316 
317 	DPU_REG_WRITE(c, format_off, src_format);
318 	DPU_REG_WRITE(c, unpack_pat_off, unpack);
319 	DPU_REG_WRITE(c, op_mode_off, opmode);
320 
321 	/* clear previous UBWC error */
322 	DPU_REG_WRITE(c, SSPP_UBWC_ERROR_STATUS, BIT(31));
323 }
324 
325 static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_sspp *ctx,
326 		struct dpu_hw_pixel_ext *pe_ext)
327 {
328 	struct dpu_hw_blk_reg_map *c;
329 	u8 color;
330 	u32 lr_pe[4], tb_pe[4], tot_req_pixels[4];
331 	const u32 bytemask = 0xff;
332 	const u32 shortmask = 0xffff;
333 
334 	if (!ctx || !pe_ext)
335 		return;
336 
337 	c = &ctx->hw;
338 
339 	/* program SW pixel extension override for all pipes*/
340 	for (color = 0; color < DPU_MAX_PLANES; color++) {
341 		/* color 2 has the same set of registers as color 1 */
342 		if (color == 2)
343 			continue;
344 
345 		lr_pe[color] = ((pe_ext->right_ftch[color] & bytemask) << 24)|
346 			((pe_ext->right_rpt[color] & bytemask) << 16)|
347 			((pe_ext->left_ftch[color] & bytemask) << 8)|
348 			(pe_ext->left_rpt[color] & bytemask);
349 
350 		tb_pe[color] = ((pe_ext->btm_ftch[color] & bytemask) << 24)|
351 			((pe_ext->btm_rpt[color] & bytemask) << 16)|
352 			((pe_ext->top_ftch[color] & bytemask) << 8)|
353 			(pe_ext->top_rpt[color] & bytemask);
354 
355 		tot_req_pixels[color] = (((pe_ext->roi_h[color] +
356 			pe_ext->num_ext_pxls_top[color] +
357 			pe_ext->num_ext_pxls_btm[color]) & shortmask) << 16) |
358 			((pe_ext->roi_w[color] +
359 			pe_ext->num_ext_pxls_left[color] +
360 			pe_ext->num_ext_pxls_right[color]) & shortmask);
361 	}
362 
363 	/* color 0 */
364 	DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C0_LR, lr_pe[0]);
365 	DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C0_TB, tb_pe[0]);
366 	DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C0_REQ_PIXELS,
367 			tot_req_pixels[0]);
368 
369 	/* color 1 and color 2 */
370 	DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C1C2_LR, lr_pe[1]);
371 	DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C1C2_TB, tb_pe[1]);
372 	DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C1C2_REQ_PIXELS,
373 			tot_req_pixels[1]);
374 
375 	/* color 3 */
376 	DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C3_LR, lr_pe[3]);
377 	DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C3_TB, lr_pe[3]);
378 	DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C3_REQ_PIXELS,
379 			tot_req_pixels[3]);
380 }
381 
382 static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx,
383 		struct dpu_hw_scaler3_cfg *scaler3_cfg,
384 		const struct dpu_format *format)
385 {
386 	if (!ctx || !scaler3_cfg)
387 		return;
388 
389 	dpu_hw_setup_scaler3(&ctx->hw, scaler3_cfg,
390 			ctx->cap->sblk->scaler_blk.base,
391 			ctx->cap->sblk->scaler_blk.version,
392 			format);
393 }
394 
395 static u32 _dpu_hw_sspp_get_scaler3_ver(struct dpu_hw_sspp *ctx)
396 {
397 	if (!ctx)
398 		return 0;
399 
400 	return dpu_hw_get_scaler3_ver(&ctx->hw,
401 				      ctx->cap->sblk->scaler_blk.base);
402 }
403 
404 /*
405  * dpu_hw_sspp_setup_rects()
406  */
407 static void dpu_hw_sspp_setup_rects(struct dpu_sw_pipe *pipe,
408 		struct dpu_sw_pipe_cfg *cfg)
409 {
410 	struct dpu_hw_sspp *ctx = pipe->sspp;
411 	struct dpu_hw_blk_reg_map *c;
412 	u32 src_size, src_xy, dst_size, dst_xy;
413 	u32 src_size_off, src_xy_off, out_size_off, out_xy_off;
414 
415 	if (!ctx || !cfg)
416 		return;
417 
418 	c = &ctx->hw;
419 
420 	if (pipe->multirect_index == DPU_SSPP_RECT_SOLO ||
421 	    pipe->multirect_index == DPU_SSPP_RECT_0) {
422 		src_size_off = SSPP_SRC_SIZE;
423 		src_xy_off = SSPP_SRC_XY;
424 		out_size_off = SSPP_OUT_SIZE;
425 		out_xy_off = SSPP_OUT_XY;
426 	} else {
427 		src_size_off = SSPP_SRC_SIZE_REC1;
428 		src_xy_off = SSPP_SRC_XY_REC1;
429 		out_size_off = SSPP_OUT_SIZE_REC1;
430 		out_xy_off = SSPP_OUT_XY_REC1;
431 	}
432 
433 
434 	/* src and dest rect programming */
435 	src_xy = (cfg->src_rect.y1 << 16) | cfg->src_rect.x1;
436 	src_size = (drm_rect_height(&cfg->src_rect) << 16) |
437 		   drm_rect_width(&cfg->src_rect);
438 	dst_xy = (cfg->dst_rect.y1 << 16) | cfg->dst_rect.x1;
439 	dst_size = (drm_rect_height(&cfg->dst_rect) << 16) |
440 		drm_rect_width(&cfg->dst_rect);
441 
442 	/* rectangle register programming */
443 	DPU_REG_WRITE(c, src_size_off, src_size);
444 	DPU_REG_WRITE(c, src_xy_off, src_xy);
445 	DPU_REG_WRITE(c, out_size_off, dst_size);
446 	DPU_REG_WRITE(c, out_xy_off, dst_xy);
447 }
448 
449 static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe,
450 		struct dpu_hw_fmt_layout *layout)
451 {
452 	struct dpu_hw_sspp *ctx = pipe->sspp;
453 	u32 ystride0, ystride1;
454 	int i;
455 
456 	if (!ctx)
457 		return;
458 
459 	if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
460 		for (i = 0; i < ARRAY_SIZE(layout->plane_addr); i++)
461 			DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + i * 0x4,
462 					layout->plane_addr[i]);
463 	} else if (pipe->multirect_index == DPU_SSPP_RECT_0) {
464 		DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR,
465 				layout->plane_addr[0]);
466 		DPU_REG_WRITE(&ctx->hw, SSPP_SRC2_ADDR,
467 				layout->plane_addr[2]);
468 	} else {
469 		DPU_REG_WRITE(&ctx->hw, SSPP_SRC1_ADDR,
470 				layout->plane_addr[0]);
471 		DPU_REG_WRITE(&ctx->hw, SSPP_SRC3_ADDR,
472 				layout->plane_addr[2]);
473 	}
474 
475 	if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
476 		ystride0 = (layout->plane_pitch[0]) |
477 			(layout->plane_pitch[1] << 16);
478 		ystride1 = (layout->plane_pitch[2]) |
479 			(layout->plane_pitch[3] << 16);
480 	} else {
481 		ystride0 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE0);
482 		ystride1 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE1);
483 
484 		if (pipe->multirect_index == DPU_SSPP_RECT_0) {
485 			ystride0 = (ystride0 & 0xFFFF0000) |
486 				(layout->plane_pitch[0] & 0x0000FFFF);
487 			ystride1 = (ystride1 & 0xFFFF0000)|
488 				(layout->plane_pitch[2] & 0x0000FFFF);
489 		} else {
490 			ystride0 = (ystride0 & 0x0000FFFF) |
491 				((layout->plane_pitch[0] << 16) &
492 				 0xFFFF0000);
493 			ystride1 = (ystride1 & 0x0000FFFF) |
494 				((layout->plane_pitch[2] << 16) &
495 				 0xFFFF0000);
496 		}
497 	}
498 
499 	DPU_REG_WRITE(&ctx->hw, SSPP_SRC_YSTRIDE0, ystride0);
500 	DPU_REG_WRITE(&ctx->hw, SSPP_SRC_YSTRIDE1, ystride1);
501 }
502 
503 static void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx,
504 		const struct dpu_csc_cfg *data)
505 {
506 	u32 offset;
507 	bool csc10 = false;
508 
509 	if (!ctx || !data)
510 		return;
511 
512 	offset = ctx->cap->sblk->csc_blk.base;
513 
514 	if (test_bit(DPU_SSPP_CSC_10BIT, &ctx->cap->features)) {
515 		offset += CSC_10BIT_OFFSET;
516 		csc10 = true;
517 	}
518 
519 	dpu_hw_csc_setup(&ctx->hw, offset, data, csc10);
520 }
521 
522 static void dpu_hw_sspp_setup_solidfill(struct dpu_sw_pipe *pipe, u32 color)
523 {
524 	struct dpu_hw_sspp *ctx = pipe->sspp;
525 	struct dpu_hw_fmt_layout cfg;
526 
527 	if (!ctx)
528 		return;
529 
530 	/* cleanup source addresses */
531 	memset(&cfg, 0, sizeof(cfg));
532 	ctx->ops.setup_sourceaddress(pipe, &cfg);
533 
534 	if (pipe->multirect_index == DPU_SSPP_RECT_SOLO ||
535 	    pipe->multirect_index == DPU_SSPP_RECT_0)
536 		DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR, color);
537 	else
538 		DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR_REC1,
539 				color);
540 }
541 
542 static void dpu_hw_sspp_setup_qos_lut(struct dpu_hw_sspp *ctx,
543 				      struct dpu_hw_qos_cfg *cfg)
544 {
545 	if (!ctx || !cfg)
546 		return;
547 
548 	_dpu_hw_setup_qos_lut(&ctx->hw, SSPP_DANGER_LUT,
549 			      test_bit(DPU_SSPP_QOS_8LVL, &ctx->cap->features),
550 			      cfg);
551 }
552 
553 static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_sspp *ctx,
554 				       bool danger_safe_en)
555 {
556 	if (!ctx)
557 		return;
558 
559 	DPU_REG_WRITE(&ctx->hw, SSPP_QOS_CTRL,
560 		      danger_safe_en ? SSPP_QOS_CTRL_DANGER_SAFE_EN : 0);
561 }
562 
563 static void dpu_hw_sspp_setup_cdp(struct dpu_sw_pipe *pipe,
564 				  const struct dpu_format *fmt,
565 				  bool enable)
566 {
567 	struct dpu_hw_sspp *ctx = pipe->sspp;
568 	u32 cdp_cntl_offset = 0;
569 
570 	if (!ctx)
571 		return;
572 
573 	if (pipe->multirect_index == DPU_SSPP_RECT_SOLO ||
574 	    pipe->multirect_index == DPU_SSPP_RECT_0)
575 		cdp_cntl_offset = SSPP_CDP_CNTL;
576 	else
577 		cdp_cntl_offset = SSPP_CDP_CNTL_REC1;
578 
579 	dpu_setup_cdp(&ctx->hw, cdp_cntl_offset, fmt, enable);
580 }
581 
582 static void _setup_layer_ops(struct dpu_hw_sspp *c,
583 		unsigned long features)
584 {
585 	c->ops.setup_format = dpu_hw_sspp_setup_format;
586 	c->ops.setup_rects = dpu_hw_sspp_setup_rects;
587 	c->ops.setup_sourceaddress = dpu_hw_sspp_setup_sourceaddress;
588 	c->ops.setup_solidfill = dpu_hw_sspp_setup_solidfill;
589 	c->ops.setup_pe = dpu_hw_sspp_setup_pe_config;
590 
591 	if (test_bit(DPU_SSPP_QOS, &features)) {
592 		c->ops.setup_qos_lut = dpu_hw_sspp_setup_qos_lut;
593 		c->ops.setup_qos_ctrl = dpu_hw_sspp_setup_qos_ctrl;
594 	}
595 
596 	if (test_bit(DPU_SSPP_CSC, &features) ||
597 		test_bit(DPU_SSPP_CSC_10BIT, &features))
598 		c->ops.setup_csc = dpu_hw_sspp_setup_csc;
599 
600 	if (test_bit(DPU_SSPP_SMART_DMA_V1, &c->cap->features) ||
601 		test_bit(DPU_SSPP_SMART_DMA_V2, &c->cap->features))
602 		c->ops.setup_multirect = dpu_hw_sspp_setup_multirect;
603 
604 	if (test_bit(DPU_SSPP_SCALER_QSEED3, &features) ||
605 			test_bit(DPU_SSPP_SCALER_QSEED3LITE, &features) ||
606 			test_bit(DPU_SSPP_SCALER_QSEED4, &features)) {
607 		c->ops.setup_scaler = _dpu_hw_sspp_setup_scaler3;
608 		c->ops.get_scaler_ver = _dpu_hw_sspp_get_scaler3_ver;
609 	}
610 
611 	if (test_bit(DPU_SSPP_CDP, &features))
612 		c->ops.setup_cdp = dpu_hw_sspp_setup_cdp;
613 }
614 
615 #ifdef CONFIG_DEBUG_FS
616 int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pipe, struct dpu_kms *kms,
617 			      struct dentry *entry)
618 {
619 	const struct dpu_sspp_cfg *cfg = hw_pipe->cap;
620 	const struct dpu_sspp_sub_blks *sblk = cfg->sblk;
621 	struct dentry *debugfs_root;
622 	char sspp_name[32];
623 
624 	snprintf(sspp_name, sizeof(sspp_name), "%d", hw_pipe->idx);
625 
626 	/* create overall sub-directory for the pipe */
627 	debugfs_root =
628 		debugfs_create_dir(sspp_name, entry);
629 
630 	/* don't error check these */
631 	debugfs_create_xul("features", 0600,
632 			debugfs_root, (unsigned long *)&hw_pipe->cap->features);
633 
634 	/* add register dump support */
635 	dpu_debugfs_create_regset32("src_blk", 0400,
636 			debugfs_root,
637 			cfg->base,
638 			cfg->len,
639 			kms);
640 
641 	if (cfg->features & BIT(DPU_SSPP_SCALER_QSEED3) ||
642 			cfg->features & BIT(DPU_SSPP_SCALER_QSEED3LITE) ||
643 			cfg->features & BIT(DPU_SSPP_SCALER_QSEED2) ||
644 			cfg->features & BIT(DPU_SSPP_SCALER_QSEED4))
645 		dpu_debugfs_create_regset32("scaler_blk", 0400,
646 				debugfs_root,
647 				sblk->scaler_blk.base + cfg->base,
648 				sblk->scaler_blk.len,
649 				kms);
650 
651 	if (cfg->features & BIT(DPU_SSPP_CSC) ||
652 			cfg->features & BIT(DPU_SSPP_CSC_10BIT))
653 		dpu_debugfs_create_regset32("csc_blk", 0400,
654 				debugfs_root,
655 				sblk->csc_blk.base + cfg->base,
656 				sblk->csc_blk.len,
657 				kms);
658 
659 	debugfs_create_u32("xin_id",
660 			0400,
661 			debugfs_root,
662 			(u32 *) &cfg->xin_id);
663 	debugfs_create_u32("clk_ctrl",
664 			0400,
665 			debugfs_root,
666 			(u32 *) &cfg->clk_ctrl);
667 
668 	return 0;
669 }
670 #endif
671 
672 struct dpu_hw_sspp *dpu_hw_sspp_init(const struct dpu_sspp_cfg *cfg,
673 		void __iomem *addr, const struct dpu_ubwc_cfg *ubwc)
674 {
675 	struct dpu_hw_sspp *hw_pipe;
676 
677 	if (!addr || !ubwc)
678 		return ERR_PTR(-EINVAL);
679 
680 	hw_pipe = kzalloc(sizeof(*hw_pipe), GFP_KERNEL);
681 	if (!hw_pipe)
682 		return ERR_PTR(-ENOMEM);
683 
684 	hw_pipe->hw.blk_addr = addr + cfg->base;
685 	hw_pipe->hw.log_mask = DPU_DBG_MASK_SSPP;
686 
687 	/* Assign ops */
688 	hw_pipe->ubwc = ubwc;
689 	hw_pipe->idx = cfg->id;
690 	hw_pipe->cap = cfg;
691 	_setup_layer_ops(hw_pipe, hw_pipe->cap->features);
692 
693 	return hw_pipe;
694 }
695 
696 void dpu_hw_sspp_destroy(struct dpu_hw_sspp *ctx)
697 {
698 	kfree(ctx);
699 }
700 
701