1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 3 */ 4 5 #include <linux/iopoll.h> 6 7 #include "dpu_hw_mdss.h" 8 #include "dpu_hwio.h" 9 #include "dpu_hw_catalog.h" 10 #include "dpu_hw_pingpong.h" 11 #include "dpu_kms.h" 12 #include "dpu_trace.h" 13 14 #define PP_TEAR_CHECK_EN 0x000 15 #define PP_SYNC_CONFIG_VSYNC 0x004 16 #define PP_SYNC_CONFIG_HEIGHT 0x008 17 #define PP_SYNC_WRCOUNT 0x00C 18 #define PP_VSYNC_INIT_VAL 0x010 19 #define PP_INT_COUNT_VAL 0x014 20 #define PP_SYNC_THRESH 0x018 21 #define PP_START_POS 0x01C 22 #define PP_RD_PTR_IRQ 0x020 23 #define PP_WR_PTR_IRQ 0x024 24 #define PP_OUT_LINE_COUNT 0x028 25 #define PP_LINE_COUNT 0x02C 26 #define PP_AUTOREFRESH_CONFIG 0x030 27 28 #define PP_FBC_MODE 0x034 29 #define PP_FBC_BUDGET_CTL 0x038 30 #define PP_FBC_LOSSY_MODE 0x03C 31 #define PP_DSC_MODE 0x0a0 32 #define PP_DCE_DATA_IN_SWAP 0x0ac 33 #define PP_DCE_DATA_OUT_SWAP 0x0c8 34 35 #define PP_DITHER_EN 0x000 36 #define PP_DITHER_BITDEPTH 0x004 37 #define PP_DITHER_MATRIX 0x008 38 39 #define DITHER_DEPTH_MAP_INDEX 9 40 41 static u32 dither_depth_map[DITHER_DEPTH_MAP_INDEX] = { 42 0, 0, 0, 0, 0, 0, 0, 1, 2 43 }; 44 45 static const struct dpu_pingpong_cfg *_pingpong_offset(enum dpu_pingpong pp, 46 const struct dpu_mdss_cfg *m, 47 void __iomem *addr, 48 struct dpu_hw_blk_reg_map *b) 49 { 50 int i; 51 52 for (i = 0; i < m->pingpong_count; i++) { 53 if (pp == m->pingpong[i].id) { 54 b->blk_addr = addr + m->pingpong[i].base; 55 b->log_mask = DPU_DBG_MASK_PINGPONG; 56 return &m->pingpong[i]; 57 } 58 } 59 60 return ERR_PTR(-EINVAL); 61 } 62 63 static void dpu_hw_pp_setup_dither(struct dpu_hw_pingpong *pp, 64 struct dpu_hw_dither_cfg *cfg) 65 { 66 struct dpu_hw_blk_reg_map *c; 67 u32 i, base, data = 0; 68 69 c = &pp->hw; 70 base = pp->caps->sblk->dither.base; 71 if (!cfg) { 72 DPU_REG_WRITE(c, base + PP_DITHER_EN, 0); 73 return; 74 } 75 76 data = dither_depth_map[cfg->c0_bitdepth] & REG_MASK(2); 77 data |= (dither_depth_map[cfg->c1_bitdepth] & REG_MASK(2)) << 2; 78 data |= (dither_depth_map[cfg->c2_bitdepth] & REG_MASK(2)) << 4; 79 data |= (dither_depth_map[cfg->c3_bitdepth] & REG_MASK(2)) << 6; 80 data |= (cfg->temporal_en) ? (1 << 8) : 0; 81 82 DPU_REG_WRITE(c, base + PP_DITHER_BITDEPTH, data); 83 84 for (i = 0; i < DITHER_MATRIX_SZ - 3; i += 4) { 85 data = (cfg->matrix[i] & REG_MASK(4)) | 86 ((cfg->matrix[i + 1] & REG_MASK(4)) << 4) | 87 ((cfg->matrix[i + 2] & REG_MASK(4)) << 8) | 88 ((cfg->matrix[i + 3] & REG_MASK(4)) << 12); 89 DPU_REG_WRITE(c, base + PP_DITHER_MATRIX + i, data); 90 } 91 DPU_REG_WRITE(c, base + PP_DITHER_EN, 1); 92 } 93 94 static int dpu_hw_pp_setup_te_config(struct dpu_hw_pingpong *pp, 95 struct dpu_hw_tear_check *te) 96 { 97 struct dpu_hw_blk_reg_map *c; 98 int cfg; 99 100 if (!pp || !te) 101 return -EINVAL; 102 c = &pp->hw; 103 104 cfg = BIT(19); /*VSYNC_COUNTER_EN */ 105 if (te->hw_vsync_mode) 106 cfg |= BIT(20); 107 108 cfg |= te->vsync_count; 109 110 DPU_REG_WRITE(c, PP_SYNC_CONFIG_VSYNC, cfg); 111 DPU_REG_WRITE(c, PP_SYNC_CONFIG_HEIGHT, te->sync_cfg_height); 112 DPU_REG_WRITE(c, PP_VSYNC_INIT_VAL, te->vsync_init_val); 113 DPU_REG_WRITE(c, PP_RD_PTR_IRQ, te->rd_ptr_irq); 114 DPU_REG_WRITE(c, PP_START_POS, te->start_pos); 115 DPU_REG_WRITE(c, PP_SYNC_THRESH, 116 ((te->sync_threshold_continue << 16) | 117 te->sync_threshold_start)); 118 DPU_REG_WRITE(c, PP_SYNC_WRCOUNT, 119 (te->start_pos + te->sync_threshold_start + 1)); 120 121 return 0; 122 } 123 124 static void dpu_hw_pp_setup_autorefresh_config(struct dpu_hw_pingpong *pp, 125 u32 frame_count, bool enable) 126 { 127 DPU_REG_WRITE(&pp->hw, PP_AUTOREFRESH_CONFIG, 128 enable ? (BIT(31) | frame_count) : 0); 129 } 130 131 /* 132 * dpu_hw_pp_get_autorefresh_config - Get autorefresh config from HW 133 * @pp: DPU pingpong structure 134 * @frame_count: Used to return the current frame count from hw 135 * 136 * Returns: True if autorefresh enabled, false if disabled. 137 */ 138 static bool dpu_hw_pp_get_autorefresh_config(struct dpu_hw_pingpong *pp, 139 u32 *frame_count) 140 { 141 u32 val = DPU_REG_READ(&pp->hw, PP_AUTOREFRESH_CONFIG); 142 if (frame_count != NULL) 143 *frame_count = val & 0xffff; 144 return !!((val & BIT(31)) >> 31); 145 } 146 147 static int dpu_hw_pp_poll_timeout_wr_ptr(struct dpu_hw_pingpong *pp, 148 u32 timeout_us) 149 { 150 struct dpu_hw_blk_reg_map *c; 151 u32 val; 152 int rc; 153 154 if (!pp) 155 return -EINVAL; 156 157 c = &pp->hw; 158 rc = readl_poll_timeout(c->blk_addr + PP_LINE_COUNT, 159 val, (val & 0xffff) >= 1, 10, timeout_us); 160 161 return rc; 162 } 163 164 static int dpu_hw_pp_enable_te(struct dpu_hw_pingpong *pp, bool enable) 165 { 166 struct dpu_hw_blk_reg_map *c; 167 168 if (!pp) 169 return -EINVAL; 170 c = &pp->hw; 171 172 DPU_REG_WRITE(c, PP_TEAR_CHECK_EN, enable); 173 return 0; 174 } 175 176 static int dpu_hw_pp_connect_external_te(struct dpu_hw_pingpong *pp, 177 bool enable_external_te) 178 { 179 struct dpu_hw_blk_reg_map *c = &pp->hw; 180 u32 cfg; 181 int orig; 182 183 if (!pp) 184 return -EINVAL; 185 186 c = &pp->hw; 187 cfg = DPU_REG_READ(c, PP_SYNC_CONFIG_VSYNC); 188 orig = (bool)(cfg & BIT(20)); 189 if (enable_external_te) 190 cfg |= BIT(20); 191 else 192 cfg &= ~BIT(20); 193 DPU_REG_WRITE(c, PP_SYNC_CONFIG_VSYNC, cfg); 194 trace_dpu_pp_connect_ext_te(pp->idx - PINGPONG_0, cfg); 195 196 return orig; 197 } 198 199 static int dpu_hw_pp_get_vsync_info(struct dpu_hw_pingpong *pp, 200 struct dpu_hw_pp_vsync_info *info) 201 { 202 struct dpu_hw_blk_reg_map *c; 203 u32 val; 204 205 if (!pp || !info) 206 return -EINVAL; 207 c = &pp->hw; 208 209 val = DPU_REG_READ(c, PP_VSYNC_INIT_VAL); 210 info->rd_ptr_init_val = val & 0xffff; 211 212 val = DPU_REG_READ(c, PP_INT_COUNT_VAL); 213 info->rd_ptr_frame_count = (val & 0xffff0000) >> 16; 214 info->rd_ptr_line_count = val & 0xffff; 215 216 val = DPU_REG_READ(c, PP_LINE_COUNT); 217 info->wr_ptr_line_count = val & 0xffff; 218 219 return 0; 220 } 221 222 static u32 dpu_hw_pp_get_line_count(struct dpu_hw_pingpong *pp) 223 { 224 struct dpu_hw_blk_reg_map *c = &pp->hw; 225 u32 height, init; 226 u32 line = 0xFFFF; 227 228 if (!pp) 229 return 0; 230 c = &pp->hw; 231 232 init = DPU_REG_READ(c, PP_VSYNC_INIT_VAL) & 0xFFFF; 233 height = DPU_REG_READ(c, PP_SYNC_CONFIG_HEIGHT) & 0xFFFF; 234 235 if (height < init) 236 return line; 237 238 line = DPU_REG_READ(c, PP_INT_COUNT_VAL) & 0xFFFF; 239 240 if (line < init) 241 line += (0xFFFF - init); 242 else 243 line -= init; 244 245 return line; 246 } 247 248 static int dpu_hw_pp_dsc_enable(struct dpu_hw_pingpong *pp) 249 { 250 struct dpu_hw_blk_reg_map *c = &pp->hw; 251 252 DPU_REG_WRITE(c, PP_DSC_MODE, 1); 253 return 0; 254 } 255 256 static void dpu_hw_pp_dsc_disable(struct dpu_hw_pingpong *pp) 257 { 258 struct dpu_hw_blk_reg_map *c = &pp->hw; 259 260 DPU_REG_WRITE(c, PP_DSC_MODE, 0); 261 } 262 263 static int dpu_hw_pp_setup_dsc(struct dpu_hw_pingpong *pp) 264 { 265 struct dpu_hw_blk_reg_map *pp_c = &pp->hw; 266 int data; 267 268 data = DPU_REG_READ(pp_c, PP_DCE_DATA_OUT_SWAP); 269 data |= BIT(18); /* endian flip */ 270 DPU_REG_WRITE(pp_c, PP_DCE_DATA_OUT_SWAP, data); 271 return 0; 272 } 273 274 static void _setup_pingpong_ops(struct dpu_hw_pingpong *c, 275 unsigned long features) 276 { 277 c->ops.setup_tearcheck = dpu_hw_pp_setup_te_config; 278 c->ops.enable_tearcheck = dpu_hw_pp_enable_te; 279 c->ops.connect_external_te = dpu_hw_pp_connect_external_te; 280 c->ops.get_vsync_info = dpu_hw_pp_get_vsync_info; 281 c->ops.setup_autorefresh = dpu_hw_pp_setup_autorefresh_config; 282 c->ops.get_autorefresh = dpu_hw_pp_get_autorefresh_config; 283 c->ops.poll_timeout_wr_ptr = dpu_hw_pp_poll_timeout_wr_ptr; 284 c->ops.get_line_count = dpu_hw_pp_get_line_count; 285 c->ops.setup_dsc = dpu_hw_pp_setup_dsc; 286 c->ops.enable_dsc = dpu_hw_pp_dsc_enable; 287 c->ops.disable_dsc = dpu_hw_pp_dsc_disable; 288 289 if (test_bit(DPU_PINGPONG_DITHER, &features)) 290 c->ops.setup_dither = dpu_hw_pp_setup_dither; 291 }; 292 293 struct dpu_hw_pingpong *dpu_hw_pingpong_init(enum dpu_pingpong idx, 294 void __iomem *addr, 295 const struct dpu_mdss_cfg *m) 296 { 297 struct dpu_hw_pingpong *c; 298 const struct dpu_pingpong_cfg *cfg; 299 300 c = kzalloc(sizeof(*c), GFP_KERNEL); 301 if (!c) 302 return ERR_PTR(-ENOMEM); 303 304 cfg = _pingpong_offset(idx, m, addr, &c->hw); 305 if (IS_ERR_OR_NULL(cfg)) { 306 kfree(c); 307 return ERR_PTR(-EINVAL); 308 } 309 310 c->idx = idx; 311 c->caps = cfg; 312 _setup_pingpong_ops(c, c->caps->features); 313 314 return c; 315 } 316 317 void dpu_hw_pingpong_destroy(struct dpu_hw_pingpong *pp) 318 { 319 kfree(pp); 320 } 321