1 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 2 * 3 * This program is free software; you can redistribute it and/or modify 4 * it under the terms of the GNU General Public License version 2 and 5 * only version 2 as published by the Free Software Foundation. 6 * 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 */ 12 13 #include <linux/iopoll.h> 14 15 #include "dpu_hw_mdss.h" 16 #include "dpu_hwio.h" 17 #include "dpu_hw_catalog.h" 18 #include "dpu_hw_pingpong.h" 19 #include "dpu_dbg.h" 20 #include "dpu_kms.h" 21 #include "dpu_trace.h" 22 23 #define PP_TEAR_CHECK_EN 0x000 24 #define PP_SYNC_CONFIG_VSYNC 0x004 25 #define PP_SYNC_CONFIG_HEIGHT 0x008 26 #define PP_SYNC_WRCOUNT 0x00C 27 #define PP_VSYNC_INIT_VAL 0x010 28 #define PP_INT_COUNT_VAL 0x014 29 #define PP_SYNC_THRESH 0x018 30 #define PP_START_POS 0x01C 31 #define PP_RD_PTR_IRQ 0x020 32 #define PP_WR_PTR_IRQ 0x024 33 #define PP_OUT_LINE_COUNT 0x028 34 #define PP_LINE_COUNT 0x02C 35 36 #define PP_FBC_MODE 0x034 37 #define PP_FBC_BUDGET_CTL 0x038 38 #define PP_FBC_LOSSY_MODE 0x03C 39 40 static struct dpu_pingpong_cfg *_pingpong_offset(enum dpu_pingpong pp, 41 struct dpu_mdss_cfg *m, 42 void __iomem *addr, 43 struct dpu_hw_blk_reg_map *b) 44 { 45 int i; 46 47 for (i = 0; i < m->pingpong_count; i++) { 48 if (pp == m->pingpong[i].id) { 49 b->base_off = addr; 50 b->blk_off = m->pingpong[i].base; 51 b->length = m->pingpong[i].len; 52 b->hwversion = m->hwversion; 53 b->log_mask = DPU_DBG_MASK_PINGPONG; 54 return &m->pingpong[i]; 55 } 56 } 57 58 return ERR_PTR(-EINVAL); 59 } 60 61 static int dpu_hw_pp_setup_te_config(struct dpu_hw_pingpong *pp, 62 struct dpu_hw_tear_check *te) 63 { 64 struct dpu_hw_blk_reg_map *c; 65 int cfg; 66 67 if (!pp || !te) 68 return -EINVAL; 69 c = &pp->hw; 70 71 cfg = BIT(19); /*VSYNC_COUNTER_EN */ 72 if (te->hw_vsync_mode) 73 cfg |= BIT(20); 74 75 cfg |= te->vsync_count; 76 77 DPU_REG_WRITE(c, PP_SYNC_CONFIG_VSYNC, cfg); 78 DPU_REG_WRITE(c, PP_SYNC_CONFIG_HEIGHT, te->sync_cfg_height); 79 DPU_REG_WRITE(c, PP_VSYNC_INIT_VAL, te->vsync_init_val); 80 DPU_REG_WRITE(c, PP_RD_PTR_IRQ, te->rd_ptr_irq); 81 DPU_REG_WRITE(c, PP_START_POS, te->start_pos); 82 DPU_REG_WRITE(c, PP_SYNC_THRESH, 83 ((te->sync_threshold_continue << 16) | 84 te->sync_threshold_start)); 85 DPU_REG_WRITE(c, PP_SYNC_WRCOUNT, 86 (te->start_pos + te->sync_threshold_start + 1)); 87 88 return 0; 89 } 90 91 static int dpu_hw_pp_poll_timeout_wr_ptr(struct dpu_hw_pingpong *pp, 92 u32 timeout_us) 93 { 94 struct dpu_hw_blk_reg_map *c; 95 u32 val; 96 int rc; 97 98 if (!pp) 99 return -EINVAL; 100 101 c = &pp->hw; 102 rc = readl_poll_timeout(c->base_off + c->blk_off + PP_LINE_COUNT, 103 val, (val & 0xffff) >= 1, 10, timeout_us); 104 105 return rc; 106 } 107 108 static int dpu_hw_pp_enable_te(struct dpu_hw_pingpong *pp, bool enable) 109 { 110 struct dpu_hw_blk_reg_map *c; 111 112 if (!pp) 113 return -EINVAL; 114 c = &pp->hw; 115 116 DPU_REG_WRITE(c, PP_TEAR_CHECK_EN, enable); 117 return 0; 118 } 119 120 static int dpu_hw_pp_connect_external_te(struct dpu_hw_pingpong *pp, 121 bool enable_external_te) 122 { 123 struct dpu_hw_blk_reg_map *c = &pp->hw; 124 u32 cfg; 125 int orig; 126 127 if (!pp) 128 return -EINVAL; 129 130 c = &pp->hw; 131 cfg = DPU_REG_READ(c, PP_SYNC_CONFIG_VSYNC); 132 orig = (bool)(cfg & BIT(20)); 133 if (enable_external_te) 134 cfg |= BIT(20); 135 else 136 cfg &= ~BIT(20); 137 DPU_REG_WRITE(c, PP_SYNC_CONFIG_VSYNC, cfg); 138 trace_dpu_pp_connect_ext_te(pp->idx - PINGPONG_0, cfg); 139 140 return orig; 141 } 142 143 static int dpu_hw_pp_get_vsync_info(struct dpu_hw_pingpong *pp, 144 struct dpu_hw_pp_vsync_info *info) 145 { 146 struct dpu_hw_blk_reg_map *c; 147 u32 val; 148 149 if (!pp || !info) 150 return -EINVAL; 151 c = &pp->hw; 152 153 val = DPU_REG_READ(c, PP_VSYNC_INIT_VAL); 154 info->rd_ptr_init_val = val & 0xffff; 155 156 val = DPU_REG_READ(c, PP_INT_COUNT_VAL); 157 info->rd_ptr_frame_count = (val & 0xffff0000) >> 16; 158 info->rd_ptr_line_count = val & 0xffff; 159 160 val = DPU_REG_READ(c, PP_LINE_COUNT); 161 info->wr_ptr_line_count = val & 0xffff; 162 163 return 0; 164 } 165 166 static u32 dpu_hw_pp_get_line_count(struct dpu_hw_pingpong *pp) 167 { 168 struct dpu_hw_blk_reg_map *c = &pp->hw; 169 u32 height, init; 170 u32 line = 0xFFFF; 171 172 if (!pp) 173 return 0; 174 c = &pp->hw; 175 176 init = DPU_REG_READ(c, PP_VSYNC_INIT_VAL) & 0xFFFF; 177 height = DPU_REG_READ(c, PP_SYNC_CONFIG_HEIGHT) & 0xFFFF; 178 179 if (height < init) 180 goto line_count_exit; 181 182 line = DPU_REG_READ(c, PP_INT_COUNT_VAL) & 0xFFFF; 183 184 if (line < init) 185 line += (0xFFFF - init); 186 else 187 line -= init; 188 189 line_count_exit: 190 return line; 191 } 192 193 static void _setup_pingpong_ops(struct dpu_hw_pingpong_ops *ops, 194 const struct dpu_pingpong_cfg *hw_cap) 195 { 196 ops->setup_tearcheck = dpu_hw_pp_setup_te_config; 197 ops->enable_tearcheck = dpu_hw_pp_enable_te; 198 ops->connect_external_te = dpu_hw_pp_connect_external_te; 199 ops->get_vsync_info = dpu_hw_pp_get_vsync_info; 200 ops->poll_timeout_wr_ptr = dpu_hw_pp_poll_timeout_wr_ptr; 201 ops->get_line_count = dpu_hw_pp_get_line_count; 202 }; 203 204 static struct dpu_hw_blk_ops dpu_hw_ops = { 205 .start = NULL, 206 .stop = NULL, 207 }; 208 209 struct dpu_hw_pingpong *dpu_hw_pingpong_init(enum dpu_pingpong idx, 210 void __iomem *addr, 211 struct dpu_mdss_cfg *m) 212 { 213 struct dpu_hw_pingpong *c; 214 struct dpu_pingpong_cfg *cfg; 215 int rc; 216 217 c = kzalloc(sizeof(*c), GFP_KERNEL); 218 if (!c) 219 return ERR_PTR(-ENOMEM); 220 221 cfg = _pingpong_offset(idx, m, addr, &c->hw); 222 if (IS_ERR_OR_NULL(cfg)) { 223 kfree(c); 224 return ERR_PTR(-EINVAL); 225 } 226 227 c->idx = idx; 228 c->caps = cfg; 229 _setup_pingpong_ops(&c->ops, c->caps); 230 231 rc = dpu_hw_blk_init(&c->base, DPU_HW_BLK_PINGPONG, idx, &dpu_hw_ops); 232 if (rc) { 233 DPU_ERROR("failed to init hw blk %d\n", rc); 234 goto blk_init_error; 235 } 236 237 return c; 238 239 blk_init_error: 240 kzfree(c); 241 242 return ERR_PTR(rc); 243 } 244 245 void dpu_hw_pingpong_destroy(struct dpu_hw_pingpong *pp) 246 { 247 if (pp) 248 dpu_hw_blk_destroy(&pp->base); 249 kfree(pp); 250 } 251