1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
3  */
4 
5 #ifndef _DPU_HW_MDSS_H
6 #define _DPU_HW_MDSS_H
7 
8 #include <linux/kernel.h>
9 #include <linux/err.h>
10 
11 #include "msm_drv.h"
12 
13 #define DPU_DBG_NAME			"dpu"
14 
15 #define DPU_NONE                        0
16 
17 #ifndef DPU_CSC_MATRIX_COEFF_SIZE
18 #define DPU_CSC_MATRIX_COEFF_SIZE	9
19 #endif
20 
21 #ifndef DPU_CSC_CLAMP_SIZE
22 #define DPU_CSC_CLAMP_SIZE		6
23 #endif
24 
25 #ifndef DPU_CSC_BIAS_SIZE
26 #define DPU_CSC_BIAS_SIZE		3
27 #endif
28 
29 #ifndef DPU_MAX_PLANES
30 #define DPU_MAX_PLANES			4
31 #endif
32 
33 #define PIPES_PER_STAGE			2
34 #ifndef DPU_MAX_DE_CURVES
35 #define DPU_MAX_DE_CURVES		3
36 #endif
37 
38 enum dpu_format_flags {
39 	DPU_FORMAT_FLAG_YUV_BIT,
40 	DPU_FORMAT_FLAG_DX_BIT,
41 	DPU_FORMAT_FLAG_COMPRESSED_BIT,
42 	DPU_FORMAT_FLAG_BIT_MAX,
43 };
44 
45 #define DPU_FORMAT_FLAG_YUV		BIT(DPU_FORMAT_FLAG_YUV_BIT)
46 #define DPU_FORMAT_FLAG_DX		BIT(DPU_FORMAT_FLAG_DX_BIT)
47 #define DPU_FORMAT_FLAG_COMPRESSED	BIT(DPU_FORMAT_FLAG_COMPRESSED_BIT)
48 #define DPU_FORMAT_IS_YUV(X)		\
49 	(test_bit(DPU_FORMAT_FLAG_YUV_BIT, (X)->flag))
50 #define DPU_FORMAT_IS_DX(X)		\
51 	(test_bit(DPU_FORMAT_FLAG_DX_BIT, (X)->flag))
52 #define DPU_FORMAT_IS_LINEAR(X)		((X)->fetch_mode == DPU_FETCH_LINEAR)
53 #define DPU_FORMAT_IS_TILE(X) \
54 	(((X)->fetch_mode == DPU_FETCH_UBWC) && \
55 			!test_bit(DPU_FORMAT_FLAG_COMPRESSED_BIT, (X)->flag))
56 #define DPU_FORMAT_IS_UBWC(X) \
57 	(((X)->fetch_mode == DPU_FETCH_UBWC) && \
58 			test_bit(DPU_FORMAT_FLAG_COMPRESSED_BIT, (X)->flag))
59 
60 #define DPU_BLEND_FG_ALPHA_FG_CONST	(0 << 0)
61 #define DPU_BLEND_FG_ALPHA_BG_CONST	(1 << 0)
62 #define DPU_BLEND_FG_ALPHA_FG_PIXEL	(2 << 0)
63 #define DPU_BLEND_FG_ALPHA_BG_PIXEL	(3 << 0)
64 #define DPU_BLEND_FG_INV_ALPHA		(1 << 2)
65 #define DPU_BLEND_FG_MOD_ALPHA		(1 << 3)
66 #define DPU_BLEND_FG_INV_MOD_ALPHA	(1 << 4)
67 #define DPU_BLEND_FG_TRANSP_EN		(1 << 5)
68 #define DPU_BLEND_BG_ALPHA_FG_CONST	(0 << 8)
69 #define DPU_BLEND_BG_ALPHA_BG_CONST	(1 << 8)
70 #define DPU_BLEND_BG_ALPHA_FG_PIXEL	(2 << 8)
71 #define DPU_BLEND_BG_ALPHA_BG_PIXEL	(3 << 8)
72 #define DPU_BLEND_BG_INV_ALPHA		(1 << 10)
73 #define DPU_BLEND_BG_MOD_ALPHA		(1 << 11)
74 #define DPU_BLEND_BG_INV_MOD_ALPHA	(1 << 12)
75 #define DPU_BLEND_BG_TRANSP_EN		(1 << 13)
76 
77 #define DPU_VSYNC0_SOURCE_GPIO		0
78 #define DPU_VSYNC1_SOURCE_GPIO		1
79 #define DPU_VSYNC2_SOURCE_GPIO		2
80 #define DPU_VSYNC_SOURCE_INTF_0		3
81 #define DPU_VSYNC_SOURCE_INTF_1		4
82 #define DPU_VSYNC_SOURCE_INTF_2		5
83 #define DPU_VSYNC_SOURCE_INTF_3		6
84 #define DPU_VSYNC_SOURCE_WD_TIMER_4	11
85 #define DPU_VSYNC_SOURCE_WD_TIMER_3	12
86 #define DPU_VSYNC_SOURCE_WD_TIMER_2	13
87 #define DPU_VSYNC_SOURCE_WD_TIMER_1	14
88 #define DPU_VSYNC_SOURCE_WD_TIMER_0	15
89 
90 enum dpu_hw_blk_type {
91 	DPU_HW_BLK_TOP = 0,
92 	DPU_HW_BLK_SSPP,
93 	DPU_HW_BLK_LM,
94 	DPU_HW_BLK_CTL,
95 	DPU_HW_BLK_PINGPONG,
96 	DPU_HW_BLK_INTF,
97 	DPU_HW_BLK_WB,
98 	DPU_HW_BLK_DSPP,
99 	DPU_HW_BLK_MERGE_3D,
100 	DPU_HW_BLK_DSC,
101 	DPU_HW_BLK_MAX,
102 };
103 
104 enum dpu_mdp {
105 	MDP_TOP = 0x1,
106 	MDP_MAX,
107 };
108 
109 enum dpu_sspp {
110 	SSPP_NONE,
111 	SSPP_VIG0,
112 	SSPP_VIG1,
113 	SSPP_VIG2,
114 	SSPP_VIG3,
115 	SSPP_RGB0,
116 	SSPP_RGB1,
117 	SSPP_RGB2,
118 	SSPP_RGB3,
119 	SSPP_DMA0,
120 	SSPP_DMA1,
121 	SSPP_DMA2,
122 	SSPP_DMA3,
123 	SSPP_CURSOR0,
124 	SSPP_CURSOR1,
125 	SSPP_MAX
126 };
127 
128 enum dpu_sspp_type {
129 	SSPP_TYPE_VIG,
130 	SSPP_TYPE_RGB,
131 	SSPP_TYPE_DMA,
132 	SSPP_TYPE_CURSOR,
133 	SSPP_TYPE_MAX
134 };
135 
136 enum dpu_lm {
137 	LM_0 = 1,
138 	LM_1,
139 	LM_2,
140 	LM_3,
141 	LM_4,
142 	LM_5,
143 	LM_6,
144 	LM_MAX
145 };
146 
147 enum dpu_stage {
148 	DPU_STAGE_BASE = 0,
149 	DPU_STAGE_0,
150 	DPU_STAGE_1,
151 	DPU_STAGE_2,
152 	DPU_STAGE_3,
153 	DPU_STAGE_4,
154 	DPU_STAGE_5,
155 	DPU_STAGE_6,
156 	DPU_STAGE_7,
157 	DPU_STAGE_8,
158 	DPU_STAGE_9,
159 	DPU_STAGE_10,
160 	DPU_STAGE_MAX
161 };
162 enum dpu_dspp {
163 	DSPP_0 = 1,
164 	DSPP_1,
165 	DSPP_2,
166 	DSPP_3,
167 	DSPP_MAX
168 };
169 
170 enum dpu_ctl {
171 	CTL_0 = 1,
172 	CTL_1,
173 	CTL_2,
174 	CTL_3,
175 	CTL_4,
176 	CTL_5,
177 	CTL_MAX
178 };
179 
180 enum dpu_dsc {
181 	DSC_NONE = 0,
182 	DSC_0,
183 	DSC_1,
184 	DSC_2,
185 	DSC_3,
186 	DSC_4,
187 	DSC_5,
188 	DSC_MAX
189 };
190 
191 enum dpu_pingpong {
192 	PINGPONG_0 = 1,
193 	PINGPONG_1,
194 	PINGPONG_2,
195 	PINGPONG_3,
196 	PINGPONG_4,
197 	PINGPONG_5,
198 	PINGPONG_S0,
199 	PINGPONG_MAX
200 };
201 
202 enum dpu_merge_3d {
203 	MERGE_3D_0 = 1,
204 	MERGE_3D_1,
205 	MERGE_3D_2,
206 	MERGE_3D_MAX
207 };
208 
209 enum dpu_intf {
210 	INTF_0 = 1,
211 	INTF_1,
212 	INTF_2,
213 	INTF_3,
214 	INTF_4,
215 	INTF_5,
216 	INTF_6,
217 	INTF_MAX
218 };
219 
220 /*
221  * Historically these values correspond to the values written to the
222  * DISP_INTF_SEL register, which had to programmed manually. On newer MDP
223  * generations this register is NOP, but we keep the values for historical
224  * reasons.
225  */
226 enum dpu_intf_type {
227 	INTF_NONE = 0x0,
228 	INTF_DSI = 0x1,
229 	INTF_HDMI = 0x3,
230 	INTF_LCDC = 0x5,
231 	/* old eDP found on 8x74 and 8x84 */
232 	INTF_EDP = 0x9,
233 	/* both DP and eDP,  handled by the new DP driver */
234 	INTF_DP = 0xa,
235 
236 	/* virtual interfaces */
237 	INTF_WB = 0x100,
238 };
239 
240 enum dpu_intf_mode {
241 	INTF_MODE_NONE = 0,
242 	INTF_MODE_CMD,
243 	INTF_MODE_VIDEO,
244 	INTF_MODE_WB_BLOCK,
245 	INTF_MODE_WB_LINE,
246 	INTF_MODE_MAX
247 };
248 
249 enum dpu_wb {
250 	WB_0 = 1,
251 	WB_1,
252 	WB_2,
253 	WB_3,
254 	WB_MAX
255 };
256 
257 enum dpu_cwb {
258 	CWB_0 = 0x1,
259 	CWB_1,
260 	CWB_2,
261 	CWB_3,
262 	CWB_MAX
263 };
264 
265 enum dpu_wd_timer {
266 	WD_TIMER_0 = 0x1,
267 	WD_TIMER_1,
268 	WD_TIMER_2,
269 	WD_TIMER_3,
270 	WD_TIMER_4,
271 	WD_TIMER_5,
272 	WD_TIMER_MAX
273 };
274 
275 enum dpu_vbif {
276 	VBIF_0,
277 	VBIF_1,
278 	VBIF_MAX,
279 	VBIF_RT = VBIF_0,
280 	VBIF_NRT = VBIF_1
281 };
282 
283 /**
284  * DPU HW,Component order color map
285  */
286 enum {
287 	C0_G_Y = 0,
288 	C1_B_Cb = 1,
289 	C2_R_Cr = 2,
290 	C3_ALPHA = 3
291 };
292 
293 /**
294  * enum dpu_plane_type - defines how the color component pixel packing
295  * @DPU_PLANE_INTERLEAVED   : Color components in single plane
296  * @DPU_PLANE_PLANAR        : Color component in separate planes
297  * @DPU_PLANE_PSEUDO_PLANAR : Chroma components interleaved in separate plane
298  */
299 enum dpu_plane_type {
300 	DPU_PLANE_INTERLEAVED,
301 	DPU_PLANE_PLANAR,
302 	DPU_PLANE_PSEUDO_PLANAR,
303 };
304 
305 /**
306  * enum dpu_chroma_samp_type - chroma sub-samplng type
307  * @DPU_CHROMA_RGB   : No chroma subsampling
308  * @DPU_CHROMA_H2V1  : Chroma pixels are horizontally subsampled
309  * @DPU_CHROMA_H1V2  : Chroma pixels are vertically subsampled
310  * @DPU_CHROMA_420   : 420 subsampling
311  */
312 enum dpu_chroma_samp_type {
313 	DPU_CHROMA_RGB,
314 	DPU_CHROMA_H2V1,
315 	DPU_CHROMA_H1V2,
316 	DPU_CHROMA_420
317 };
318 
319 /**
320  * dpu_fetch_type - Defines How DPU HW fetches data
321  * @DPU_FETCH_LINEAR   : fetch is line by line
322  * @DPU_FETCH_TILE     : fetches data in Z order from a tile
323  * @DPU_FETCH_UBWC     : fetch and decompress data
324  */
325 enum dpu_fetch_type {
326 	DPU_FETCH_LINEAR,
327 	DPU_FETCH_TILE,
328 	DPU_FETCH_UBWC
329 };
330 
331 /**
332  * Value of enum chosen to fit the number of bits
333  * expected by the HW programming.
334  */
335 enum {
336 	COLOR_ALPHA_1BIT = 0,
337 	COLOR_ALPHA_4BIT = 1,
338 	COLOR_4BIT = 0,
339 	COLOR_5BIT = 1, /* No 5-bit Alpha */
340 	COLOR_6BIT = 2, /* 6-Bit Alpha also = 2 */
341 	COLOR_8BIT = 3, /* 8-Bit Alpha also = 3 */
342 };
343 
344 /**
345  * enum dpu_3d_blend_mode
346  * Desribes how the 3d data is blended
347  * @BLEND_3D_NONE      : 3d blending not enabled
348  * @BLEND_3D_FRAME_INT : Frame interleaving
349  * @BLEND_3D_H_ROW_INT : Horizontal row interleaving
350  * @BLEND_3D_V_ROW_INT : vertical row interleaving
351  * @BLEND_3D_COL_INT   : column interleaving
352  * @BLEND_3D_MAX       :
353  */
354 enum dpu_3d_blend_mode {
355 	BLEND_3D_NONE = 0,
356 	BLEND_3D_FRAME_INT,
357 	BLEND_3D_H_ROW_INT,
358 	BLEND_3D_V_ROW_INT,
359 	BLEND_3D_COL_INT,
360 	BLEND_3D_MAX
361 };
362 
363 /** struct dpu_format - defines the format configuration which
364  * allows DPU HW to correctly fetch and decode the format
365  * @base: base msm_format structure containing fourcc code
366  * @fetch_planes: how the color components are packed in pixel format
367  * @element: element color ordering
368  * @bits: element bit widths
369  * @chroma_sample: chroma sub-samplng type
370  * @unpack_align_msb: unpack aligned, 0 to LSB, 1 to MSB
371  * @unpack_tight: 0 for loose, 1 for tight
372  * @unpack_count: 0 = 1 component, 1 = 2 component
373  * @bpp: bytes per pixel
374  * @alpha_enable: whether the format has an alpha channel
375  * @num_planes: number of planes (including meta data planes)
376  * @fetch_mode: linear, tiled, or ubwc hw fetch behavior
377  * @flag: usage bit flags
378  * @tile_width: format tile width
379  * @tile_height: format tile height
380  */
381 struct dpu_format {
382 	struct msm_format base;
383 	enum dpu_plane_type fetch_planes;
384 	u8 element[DPU_MAX_PLANES];
385 	u8 bits[DPU_MAX_PLANES];
386 	enum dpu_chroma_samp_type chroma_sample;
387 	u8 unpack_align_msb;
388 	u8 unpack_tight;
389 	u8 unpack_count;
390 	u8 bpp;
391 	u8 alpha_enable;
392 	u8 num_planes;
393 	enum dpu_fetch_type fetch_mode;
394 	DECLARE_BITMAP(flag, DPU_FORMAT_FLAG_BIT_MAX);
395 	u16 tile_width;
396 	u16 tile_height;
397 };
398 #define to_dpu_format(x) container_of(x, struct dpu_format, base)
399 
400 /**
401  * struct dpu_hw_fmt_layout - format information of the source pixel data
402  * @format: pixel format parameters
403  * @num_planes: number of planes (including meta data planes)
404  * @width: image width
405  * @height: image height
406  * @total_size: total size in bytes
407  * @plane_addr: address of each plane
408  * @plane_size: length of each plane
409  * @plane_pitch: pitch of each plane
410  */
411 struct dpu_hw_fmt_layout {
412 	const struct dpu_format *format;
413 	uint32_t num_planes;
414 	uint32_t width;
415 	uint32_t height;
416 	uint32_t total_size;
417 	uint32_t plane_addr[DPU_MAX_PLANES];
418 	uint32_t plane_size[DPU_MAX_PLANES];
419 	uint32_t plane_pitch[DPU_MAX_PLANES];
420 };
421 
422 struct dpu_csc_cfg {
423 	/* matrix coefficients in S15.16 format */
424 	uint32_t csc_mv[DPU_CSC_MATRIX_COEFF_SIZE];
425 	uint32_t csc_pre_bv[DPU_CSC_BIAS_SIZE];
426 	uint32_t csc_post_bv[DPU_CSC_BIAS_SIZE];
427 	uint32_t csc_pre_lv[DPU_CSC_CLAMP_SIZE];
428 	uint32_t csc_post_lv[DPU_CSC_CLAMP_SIZE];
429 };
430 
431 /**
432  * struct dpu_mdss_color - mdss color description
433  * color 0 : green
434  * color 1 : blue
435  * color 2 : red
436  * color 3 : alpha
437  */
438 struct dpu_mdss_color {
439 	u32 color_0;
440 	u32 color_1;
441 	u32 color_2;
442 	u32 color_3;
443 };
444 
445 /*
446  * Define bit masks for h/w logging.
447  */
448 #define DPU_DBG_MASK_NONE     (1 << 0)
449 #define DPU_DBG_MASK_INTF     (1 << 1)
450 #define DPU_DBG_MASK_LM       (1 << 2)
451 #define DPU_DBG_MASK_CTL      (1 << 3)
452 #define DPU_DBG_MASK_PINGPONG (1 << 4)
453 #define DPU_DBG_MASK_SSPP     (1 << 5)
454 #define DPU_DBG_MASK_WB       (1 << 6)
455 #define DPU_DBG_MASK_TOP      (1 << 7)
456 #define DPU_DBG_MASK_VBIF     (1 << 8)
457 #define DPU_DBG_MASK_ROT      (1 << 9)
458 #define DPU_DBG_MASK_DSPP     (1 << 10)
459 #define DPU_DBG_MASK_DSC      (1 << 11)
460 
461 #endif  /* _DPU_HW_MDSS_H */
462