1 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 2 * 3 * This program is free software; you can redistribute it and/or modify 4 * it under the terms of the GNU General Public License version 2 and 5 * only version 2 as published by the Free Software Foundation. 6 * 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 */ 12 13 #ifndef _DPU_HW_MDSS_H 14 #define _DPU_HW_MDSS_H 15 16 #include <linux/kernel.h> 17 #include <linux/err.h> 18 19 #include "msm_drv.h" 20 21 #define DPU_DBG_NAME "dpu" 22 23 #define DPU_NONE 0 24 25 #ifndef DPU_CSC_MATRIX_COEFF_SIZE 26 #define DPU_CSC_MATRIX_COEFF_SIZE 9 27 #endif 28 29 #ifndef DPU_CSC_CLAMP_SIZE 30 #define DPU_CSC_CLAMP_SIZE 6 31 #endif 32 33 #ifndef DPU_CSC_BIAS_SIZE 34 #define DPU_CSC_BIAS_SIZE 3 35 #endif 36 37 #ifndef DPU_MAX_PLANES 38 #define DPU_MAX_PLANES 4 39 #endif 40 41 #define PIPES_PER_STAGE 2 42 #ifndef DPU_MAX_DE_CURVES 43 #define DPU_MAX_DE_CURVES 3 44 #endif 45 46 enum dpu_format_flags { 47 DPU_FORMAT_FLAG_YUV_BIT, 48 DPU_FORMAT_FLAG_DX_BIT, 49 DPU_FORMAT_FLAG_COMPRESSED_BIT, 50 DPU_FORMAT_FLAG_BIT_MAX, 51 }; 52 53 #define DPU_FORMAT_FLAG_YUV BIT(DPU_FORMAT_FLAG_YUV_BIT) 54 #define DPU_FORMAT_FLAG_DX BIT(DPU_FORMAT_FLAG_DX_BIT) 55 #define DPU_FORMAT_FLAG_COMPRESSED BIT(DPU_FORMAT_FLAG_COMPRESSED_BIT) 56 #define DPU_FORMAT_IS_YUV(X) \ 57 (test_bit(DPU_FORMAT_FLAG_YUV_BIT, (X)->flag)) 58 #define DPU_FORMAT_IS_DX(X) \ 59 (test_bit(DPU_FORMAT_FLAG_DX_BIT, (X)->flag)) 60 #define DPU_FORMAT_IS_LINEAR(X) ((X)->fetch_mode == DPU_FETCH_LINEAR) 61 #define DPU_FORMAT_IS_TILE(X) \ 62 (((X)->fetch_mode == DPU_FETCH_UBWC) && \ 63 !test_bit(DPU_FORMAT_FLAG_COMPRESSED_BIT, (X)->flag)) 64 #define DPU_FORMAT_IS_UBWC(X) \ 65 (((X)->fetch_mode == DPU_FETCH_UBWC) && \ 66 test_bit(DPU_FORMAT_FLAG_COMPRESSED_BIT, (X)->flag)) 67 68 #define DPU_BLEND_FG_ALPHA_FG_CONST (0 << 0) 69 #define DPU_BLEND_FG_ALPHA_BG_CONST (1 << 0) 70 #define DPU_BLEND_FG_ALPHA_FG_PIXEL (2 << 0) 71 #define DPU_BLEND_FG_ALPHA_BG_PIXEL (3 << 0) 72 #define DPU_BLEND_FG_INV_ALPHA (1 << 2) 73 #define DPU_BLEND_FG_MOD_ALPHA (1 << 3) 74 #define DPU_BLEND_FG_INV_MOD_ALPHA (1 << 4) 75 #define DPU_BLEND_FG_TRANSP_EN (1 << 5) 76 #define DPU_BLEND_BG_ALPHA_FG_CONST (0 << 8) 77 #define DPU_BLEND_BG_ALPHA_BG_CONST (1 << 8) 78 #define DPU_BLEND_BG_ALPHA_FG_PIXEL (2 << 8) 79 #define DPU_BLEND_BG_ALPHA_BG_PIXEL (3 << 8) 80 #define DPU_BLEND_BG_INV_ALPHA (1 << 10) 81 #define DPU_BLEND_BG_MOD_ALPHA (1 << 11) 82 #define DPU_BLEND_BG_INV_MOD_ALPHA (1 << 12) 83 #define DPU_BLEND_BG_TRANSP_EN (1 << 13) 84 85 #define DPU_VSYNC0_SOURCE_GPIO 0 86 #define DPU_VSYNC1_SOURCE_GPIO 1 87 #define DPU_VSYNC2_SOURCE_GPIO 2 88 #define DPU_VSYNC_SOURCE_INTF_0 3 89 #define DPU_VSYNC_SOURCE_INTF_1 4 90 #define DPU_VSYNC_SOURCE_INTF_2 5 91 #define DPU_VSYNC_SOURCE_INTF_3 6 92 #define DPU_VSYNC_SOURCE_WD_TIMER_4 11 93 #define DPU_VSYNC_SOURCE_WD_TIMER_3 12 94 #define DPU_VSYNC_SOURCE_WD_TIMER_2 13 95 #define DPU_VSYNC_SOURCE_WD_TIMER_1 14 96 #define DPU_VSYNC_SOURCE_WD_TIMER_0 15 97 98 enum dpu_hw_blk_type { 99 DPU_HW_BLK_TOP = 0, 100 DPU_HW_BLK_SSPP, 101 DPU_HW_BLK_LM, 102 DPU_HW_BLK_CTL, 103 DPU_HW_BLK_PINGPONG, 104 DPU_HW_BLK_INTF, 105 DPU_HW_BLK_WB, 106 DPU_HW_BLK_MAX, 107 }; 108 109 enum dpu_mdp { 110 MDP_TOP = 0x1, 111 MDP_MAX, 112 }; 113 114 enum dpu_sspp { 115 SSPP_NONE, 116 SSPP_VIG0, 117 SSPP_VIG1, 118 SSPP_VIG2, 119 SSPP_VIG3, 120 SSPP_RGB0, 121 SSPP_RGB1, 122 SSPP_RGB2, 123 SSPP_RGB3, 124 SSPP_DMA0, 125 SSPP_DMA1, 126 SSPP_DMA2, 127 SSPP_DMA3, 128 SSPP_CURSOR0, 129 SSPP_CURSOR1, 130 SSPP_MAX 131 }; 132 133 enum dpu_sspp_type { 134 SSPP_TYPE_VIG, 135 SSPP_TYPE_RGB, 136 SSPP_TYPE_DMA, 137 SSPP_TYPE_CURSOR, 138 SSPP_TYPE_MAX 139 }; 140 141 enum dpu_lm { 142 LM_0 = 1, 143 LM_1, 144 LM_2, 145 LM_3, 146 LM_4, 147 LM_5, 148 LM_6, 149 LM_MAX 150 }; 151 152 enum dpu_stage { 153 DPU_STAGE_BASE = 0, 154 DPU_STAGE_0, 155 DPU_STAGE_1, 156 DPU_STAGE_2, 157 DPU_STAGE_3, 158 DPU_STAGE_4, 159 DPU_STAGE_5, 160 DPU_STAGE_6, 161 DPU_STAGE_7, 162 DPU_STAGE_8, 163 DPU_STAGE_9, 164 DPU_STAGE_10, 165 DPU_STAGE_MAX 166 }; 167 enum dpu_dspp { 168 DSPP_0 = 1, 169 DSPP_1, 170 DSPP_2, 171 DSPP_3, 172 DSPP_MAX 173 }; 174 175 enum dpu_ctl { 176 CTL_0 = 1, 177 CTL_1, 178 CTL_2, 179 CTL_3, 180 CTL_4, 181 CTL_MAX 182 }; 183 184 enum dpu_pingpong { 185 PINGPONG_0 = 1, 186 PINGPONG_1, 187 PINGPONG_2, 188 PINGPONG_3, 189 PINGPONG_4, 190 PINGPONG_S0, 191 PINGPONG_MAX 192 }; 193 194 enum dpu_intf { 195 INTF_0 = 1, 196 INTF_1, 197 INTF_2, 198 INTF_3, 199 INTF_4, 200 INTF_5, 201 INTF_6, 202 INTF_MAX 203 }; 204 205 enum dpu_intf_type { 206 INTF_NONE = 0x0, 207 INTF_DSI = 0x1, 208 INTF_HDMI = 0x3, 209 INTF_LCDC = 0x5, 210 INTF_EDP = 0x9, 211 INTF_DP = 0xa, 212 INTF_TYPE_MAX, 213 214 /* virtual interfaces */ 215 INTF_WB = 0x100, 216 }; 217 218 enum dpu_intf_mode { 219 INTF_MODE_NONE = 0, 220 INTF_MODE_CMD, 221 INTF_MODE_VIDEO, 222 INTF_MODE_WB_BLOCK, 223 INTF_MODE_WB_LINE, 224 INTF_MODE_MAX 225 }; 226 227 enum dpu_wb { 228 WB_0 = 1, 229 WB_1, 230 WB_2, 231 WB_3, 232 WB_MAX 233 }; 234 235 enum dpu_cwb { 236 CWB_0 = 0x1, 237 CWB_1, 238 CWB_2, 239 CWB_3, 240 CWB_MAX 241 }; 242 243 enum dpu_wd_timer { 244 WD_TIMER_0 = 0x1, 245 WD_TIMER_1, 246 WD_TIMER_2, 247 WD_TIMER_3, 248 WD_TIMER_4, 249 WD_TIMER_5, 250 WD_TIMER_MAX 251 }; 252 253 enum dpu_vbif { 254 VBIF_0, 255 VBIF_1, 256 VBIF_MAX, 257 VBIF_RT = VBIF_0, 258 VBIF_NRT = VBIF_1 259 }; 260 261 enum dpu_iommu_domain { 262 DPU_IOMMU_DOMAIN_UNSECURE, 263 DPU_IOMMU_DOMAIN_SECURE, 264 DPU_IOMMU_DOMAIN_MAX 265 }; 266 267 /** 268 * DPU HW,Component order color map 269 */ 270 enum { 271 C0_G_Y = 0, 272 C1_B_Cb = 1, 273 C2_R_Cr = 2, 274 C3_ALPHA = 3 275 }; 276 277 /** 278 * enum dpu_plane_type - defines how the color component pixel packing 279 * @DPU_PLANE_INTERLEAVED : Color components in single plane 280 * @DPU_PLANE_PLANAR : Color component in separate planes 281 * @DPU_PLANE_PSEUDO_PLANAR : Chroma components interleaved in separate plane 282 */ 283 enum dpu_plane_type { 284 DPU_PLANE_INTERLEAVED, 285 DPU_PLANE_PLANAR, 286 DPU_PLANE_PSEUDO_PLANAR, 287 }; 288 289 /** 290 * enum dpu_chroma_samp_type - chroma sub-samplng type 291 * @DPU_CHROMA_RGB : No chroma subsampling 292 * @DPU_CHROMA_H2V1 : Chroma pixels are horizontally subsampled 293 * @DPU_CHROMA_H1V2 : Chroma pixels are vertically subsampled 294 * @DPU_CHROMA_420 : 420 subsampling 295 */ 296 enum dpu_chroma_samp_type { 297 DPU_CHROMA_RGB, 298 DPU_CHROMA_H2V1, 299 DPU_CHROMA_H1V2, 300 DPU_CHROMA_420 301 }; 302 303 /** 304 * dpu_fetch_type - Defines How DPU HW fetches data 305 * @DPU_FETCH_LINEAR : fetch is line by line 306 * @DPU_FETCH_TILE : fetches data in Z order from a tile 307 * @DPU_FETCH_UBWC : fetch and decompress data 308 */ 309 enum dpu_fetch_type { 310 DPU_FETCH_LINEAR, 311 DPU_FETCH_TILE, 312 DPU_FETCH_UBWC 313 }; 314 315 /** 316 * Value of enum chosen to fit the number of bits 317 * expected by the HW programming. 318 */ 319 enum { 320 COLOR_ALPHA_1BIT = 0, 321 COLOR_ALPHA_4BIT = 1, 322 COLOR_4BIT = 0, 323 COLOR_5BIT = 1, /* No 5-bit Alpha */ 324 COLOR_6BIT = 2, /* 6-Bit Alpha also = 2 */ 325 COLOR_8BIT = 3, /* 8-Bit Alpha also = 3 */ 326 }; 327 328 /** 329 * enum dpu_3d_blend_mode 330 * Desribes how the 3d data is blended 331 * @BLEND_3D_NONE : 3d blending not enabled 332 * @BLEND_3D_FRAME_INT : Frame interleaving 333 * @BLEND_3D_H_ROW_INT : Horizontal row interleaving 334 * @BLEND_3D_V_ROW_INT : vertical row interleaving 335 * @BLEND_3D_COL_INT : column interleaving 336 * @BLEND_3D_MAX : 337 */ 338 enum dpu_3d_blend_mode { 339 BLEND_3D_NONE = 0, 340 BLEND_3D_FRAME_INT, 341 BLEND_3D_H_ROW_INT, 342 BLEND_3D_V_ROW_INT, 343 BLEND_3D_COL_INT, 344 BLEND_3D_MAX 345 }; 346 347 /** struct dpu_format - defines the format configuration which 348 * allows DPU HW to correctly fetch and decode the format 349 * @base: base msm_format struture containing fourcc code 350 * @fetch_planes: how the color components are packed in pixel format 351 * @element: element color ordering 352 * @bits: element bit widths 353 * @chroma_sample: chroma sub-samplng type 354 * @unpack_align_msb: unpack aligned, 0 to LSB, 1 to MSB 355 * @unpack_tight: 0 for loose, 1 for tight 356 * @unpack_count: 0 = 1 component, 1 = 2 component 357 * @bpp: bytes per pixel 358 * @alpha_enable: whether the format has an alpha channel 359 * @num_planes: number of planes (including meta data planes) 360 * @fetch_mode: linear, tiled, or ubwc hw fetch behavior 361 * @is_yuv: is format a yuv variant 362 * @flag: usage bit flags 363 * @tile_width: format tile width 364 * @tile_height: format tile height 365 */ 366 struct dpu_format { 367 struct msm_format base; 368 enum dpu_plane_type fetch_planes; 369 u8 element[DPU_MAX_PLANES]; 370 u8 bits[DPU_MAX_PLANES]; 371 enum dpu_chroma_samp_type chroma_sample; 372 u8 unpack_align_msb; 373 u8 unpack_tight; 374 u8 unpack_count; 375 u8 bpp; 376 u8 alpha_enable; 377 u8 num_planes; 378 enum dpu_fetch_type fetch_mode; 379 DECLARE_BITMAP(flag, DPU_FORMAT_FLAG_BIT_MAX); 380 u16 tile_width; 381 u16 tile_height; 382 }; 383 #define to_dpu_format(x) container_of(x, struct dpu_format, base) 384 385 /** 386 * struct dpu_hw_fmt_layout - format information of the source pixel data 387 * @format: pixel format parameters 388 * @num_planes: number of planes (including meta data planes) 389 * @width: image width 390 * @height: image height 391 * @total_size: total size in bytes 392 * @plane_addr: address of each plane 393 * @plane_size: length of each plane 394 * @plane_pitch: pitch of each plane 395 */ 396 struct dpu_hw_fmt_layout { 397 const struct dpu_format *format; 398 uint32_t num_planes; 399 uint32_t width; 400 uint32_t height; 401 uint32_t total_size; 402 uint32_t plane_addr[DPU_MAX_PLANES]; 403 uint32_t plane_size[DPU_MAX_PLANES]; 404 uint32_t plane_pitch[DPU_MAX_PLANES]; 405 }; 406 407 struct dpu_csc_cfg { 408 /* matrix coefficients in S15.16 format */ 409 uint32_t csc_mv[DPU_CSC_MATRIX_COEFF_SIZE]; 410 uint32_t csc_pre_bv[DPU_CSC_BIAS_SIZE]; 411 uint32_t csc_post_bv[DPU_CSC_BIAS_SIZE]; 412 uint32_t csc_pre_lv[DPU_CSC_CLAMP_SIZE]; 413 uint32_t csc_post_lv[DPU_CSC_CLAMP_SIZE]; 414 }; 415 416 /** 417 * struct dpu_mdss_color - mdss color description 418 * color 0 : green 419 * color 1 : blue 420 * color 2 : red 421 * color 3 : alpha 422 */ 423 struct dpu_mdss_color { 424 u32 color_0; 425 u32 color_1; 426 u32 color_2; 427 u32 color_3; 428 }; 429 430 /* 431 * Define bit masks for h/w logging. 432 */ 433 #define DPU_DBG_MASK_NONE (1 << 0) 434 #define DPU_DBG_MASK_INTF (1 << 1) 435 #define DPU_DBG_MASK_LM (1 << 2) 436 #define DPU_DBG_MASK_CTL (1 << 3) 437 #define DPU_DBG_MASK_PINGPONG (1 << 4) 438 #define DPU_DBG_MASK_SSPP (1 << 5) 439 #define DPU_DBG_MASK_WB (1 << 6) 440 #define DPU_DBG_MASK_TOP (1 << 7) 441 #define DPU_DBG_MASK_VBIF (1 << 8) 442 #define DPU_DBG_MASK_ROT (1 << 9) 443 444 #endif /* _DPU_HW_MDSS_H */ 445