197fb5e8dSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */
278d9b458SJessica Zhang /*
3*173b2472SJessica Zhang * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
478d9b458SJessica Zhang * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
525fdd593SJeykumar Sankaran */
625fdd593SJeykumar Sankaran
725fdd593SJeykumar Sankaran #ifndef _DPU_HW_LM_H
825fdd593SJeykumar Sankaran #define _DPU_HW_LM_H
925fdd593SJeykumar Sankaran
1025fdd593SJeykumar Sankaran #include "dpu_hw_mdss.h"
1125fdd593SJeykumar Sankaran #include "dpu_hw_util.h"
1225fdd593SJeykumar Sankaran
1325fdd593SJeykumar Sankaran struct dpu_hw_mixer;
1425fdd593SJeykumar Sankaran
1525fdd593SJeykumar Sankaran struct dpu_hw_mixer_cfg {
1625fdd593SJeykumar Sankaran u32 out_width;
1725fdd593SJeykumar Sankaran u32 out_height;
1825fdd593SJeykumar Sankaran bool right_mixer;
1925fdd593SJeykumar Sankaran int flags;
2025fdd593SJeykumar Sankaran };
2125fdd593SJeykumar Sankaran
2225fdd593SJeykumar Sankaran struct dpu_hw_color3_cfg {
2325fdd593SJeykumar Sankaran u8 keep_fg[DPU_STAGE_MAX];
2425fdd593SJeykumar Sankaran };
2525fdd593SJeykumar Sankaran
2625fdd593SJeykumar Sankaran /**
2725fdd593SJeykumar Sankaran *
2825fdd593SJeykumar Sankaran * struct dpu_hw_lm_ops : Interface to the mixer Hw driver functions
2925fdd593SJeykumar Sankaran * Assumption is these functions will be called after clocks are enabled
3025fdd593SJeykumar Sankaran */
3125fdd593SJeykumar Sankaran struct dpu_hw_lm_ops {
3225fdd593SJeykumar Sankaran /*
3325fdd593SJeykumar Sankaran * Sets up mixer output width and height
3425fdd593SJeykumar Sankaran * and border color if enabled
3525fdd593SJeykumar Sankaran */
3625fdd593SJeykumar Sankaran void (*setup_mixer_out)(struct dpu_hw_mixer *ctx,
3725fdd593SJeykumar Sankaran struct dpu_hw_mixer_cfg *cfg);
3825fdd593SJeykumar Sankaran
3925fdd593SJeykumar Sankaran /*
4025fdd593SJeykumar Sankaran * Alpha blending configuration
4125fdd593SJeykumar Sankaran * for the specified stage
4225fdd593SJeykumar Sankaran */
4325fdd593SJeykumar Sankaran void (*setup_blend_config)(struct dpu_hw_mixer *ctx, uint32_t stage,
4425fdd593SJeykumar Sankaran uint32_t fg_alpha, uint32_t bg_alpha, uint32_t blend_op);
4525fdd593SJeykumar Sankaran
4625fdd593SJeykumar Sankaran /*
4725fdd593SJeykumar Sankaran * Alpha color component selection from either fg or bg
4825fdd593SJeykumar Sankaran */
4925fdd593SJeykumar Sankaran void (*setup_alpha_out)(struct dpu_hw_mixer *ctx, uint32_t mixer_op);
5025fdd593SJeykumar Sankaran
5125fdd593SJeykumar Sankaran /**
5225fdd593SJeykumar Sankaran * setup_border_color : enable/disable border color
5325fdd593SJeykumar Sankaran */
5425fdd593SJeykumar Sankaran void (*setup_border_color)(struct dpu_hw_mixer *ctx,
5525fdd593SJeykumar Sankaran struct dpu_mdss_color *color,
5625fdd593SJeykumar Sankaran u8 border_en);
5778d9b458SJessica Zhang
5878d9b458SJessica Zhang /**
5978d9b458SJessica Zhang * setup_misr: Enable/disable MISR
6078d9b458SJessica Zhang */
61*173b2472SJessica Zhang void (*setup_misr)(struct dpu_hw_mixer *ctx);
6278d9b458SJessica Zhang
6378d9b458SJessica Zhang /**
6478d9b458SJessica Zhang * collect_misr: Read MISR signature
6578d9b458SJessica Zhang */
6678d9b458SJessica Zhang int (*collect_misr)(struct dpu_hw_mixer *ctx, u32 *misr_value);
6725fdd593SJeykumar Sankaran };
6825fdd593SJeykumar Sankaran
6925fdd593SJeykumar Sankaran struct dpu_hw_mixer {
7025fdd593SJeykumar Sankaran struct dpu_hw_blk base;
7125fdd593SJeykumar Sankaran struct dpu_hw_blk_reg_map hw;
7225fdd593SJeykumar Sankaran
7325fdd593SJeykumar Sankaran /* lm */
7425fdd593SJeykumar Sankaran enum dpu_lm idx;
7525fdd593SJeykumar Sankaran const struct dpu_lm_cfg *cap;
7625fdd593SJeykumar Sankaran const struct dpu_mdp_cfg *mdp;
7725fdd593SJeykumar Sankaran const struct dpu_ctl_cfg *ctl;
7825fdd593SJeykumar Sankaran
7925fdd593SJeykumar Sankaran /* ops */
8025fdd593SJeykumar Sankaran struct dpu_hw_lm_ops ops;
8125fdd593SJeykumar Sankaran
8225fdd593SJeykumar Sankaran /* store mixer info specific to display */
8325fdd593SJeykumar Sankaran struct dpu_hw_mixer_cfg cfg;
8425fdd593SJeykumar Sankaran };
8525fdd593SJeykumar Sankaran
8625fdd593SJeykumar Sankaran /**
8725fdd593SJeykumar Sankaran * to_dpu_hw_mixer - convert base object dpu_hw_base to container
8825fdd593SJeykumar Sankaran * @hw: Pointer to base hardware block
8925fdd593SJeykumar Sankaran * return: Pointer to hardware block container
9025fdd593SJeykumar Sankaran */
to_dpu_hw_mixer(struct dpu_hw_blk * hw)9125fdd593SJeykumar Sankaran static inline struct dpu_hw_mixer *to_dpu_hw_mixer(struct dpu_hw_blk *hw)
9225fdd593SJeykumar Sankaran {
9325fdd593SJeykumar Sankaran return container_of(hw, struct dpu_hw_mixer, base);
9425fdd593SJeykumar Sankaran }
9525fdd593SJeykumar Sankaran
9625fdd593SJeykumar Sankaran /**
97babdb815SMarijn Suijten * dpu_hw_lm_init() - Initializes the mixer hw driver object.
9825fdd593SJeykumar Sankaran * should be called once before accessing every mixer.
99babdb815SMarijn Suijten * @cfg: mixer catalog entry for which driver object is required
10025fdd593SJeykumar Sankaran * @addr: mapped register io address of MDP
10125fdd593SJeykumar Sankaran */
102babdb815SMarijn Suijten struct dpu_hw_mixer *dpu_hw_lm_init(const struct dpu_lm_cfg *cfg,
103babdb815SMarijn Suijten void __iomem *addr);
10425fdd593SJeykumar Sankaran
10525fdd593SJeykumar Sankaran /**
10625fdd593SJeykumar Sankaran * dpu_hw_lm_destroy(): Destroys layer mixer driver context
10725fdd593SJeykumar Sankaran * @lm: Pointer to LM driver context
10825fdd593SJeykumar Sankaran */
10925fdd593SJeykumar Sankaran void dpu_hw_lm_destroy(struct dpu_hw_mixer *lm);
11025fdd593SJeykumar Sankaran
11125fdd593SJeykumar Sankaran #endif /*_DPU_HW_LM_H */
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