1 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 2 * 3 * This program is free software; you can redistribute it and/or modify 4 * it under the terms of the GNU General Public License version 2 and 5 * only version 2 as published by the Free Software Foundation. 6 * 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 */ 12 13 #include "dpu_kms.h" 14 #include "dpu_hw_catalog.h" 15 #include "dpu_hwio.h" 16 #include "dpu_hw_lm.h" 17 #include "dpu_hw_mdss.h" 18 #include "dpu_dbg.h" 19 #include "dpu_kms.h" 20 21 #define LM_OP_MODE 0x00 22 #define LM_OUT_SIZE 0x04 23 #define LM_BORDER_COLOR_0 0x08 24 #define LM_BORDER_COLOR_1 0x010 25 26 /* These register are offset to mixer base + stage base */ 27 #define LM_BLEND0_OP 0x00 28 #define LM_BLEND0_CONST_ALPHA 0x04 29 #define LM_FG_COLOR_FILL_COLOR_0 0x08 30 #define LM_FG_COLOR_FILL_COLOR_1 0x0C 31 #define LM_FG_COLOR_FILL_SIZE 0x10 32 #define LM_FG_COLOR_FILL_XY 0x14 33 34 #define LM_BLEND0_FG_ALPHA 0x04 35 #define LM_BLEND0_BG_ALPHA 0x08 36 37 static struct dpu_lm_cfg *_lm_offset(enum dpu_lm mixer, 38 struct dpu_mdss_cfg *m, 39 void __iomem *addr, 40 struct dpu_hw_blk_reg_map *b) 41 { 42 int i; 43 44 for (i = 0; i < m->mixer_count; i++) { 45 if (mixer == m->mixer[i].id) { 46 b->base_off = addr; 47 b->blk_off = m->mixer[i].base; 48 b->length = m->mixer[i].len; 49 b->hwversion = m->hwversion; 50 b->log_mask = DPU_DBG_MASK_LM; 51 return &m->mixer[i]; 52 } 53 } 54 55 return ERR_PTR(-ENOMEM); 56 } 57 58 /** 59 * _stage_offset(): returns the relative offset of the blend registers 60 * for the stage to be setup 61 * @c: mixer ctx contains the mixer to be programmed 62 * @stage: stage index to setup 63 */ 64 static inline int _stage_offset(struct dpu_hw_mixer *ctx, enum dpu_stage stage) 65 { 66 const struct dpu_lm_sub_blks *sblk = ctx->cap->sblk; 67 int rc; 68 69 if (stage == DPU_STAGE_BASE) 70 rc = -EINVAL; 71 else if (stage <= sblk->maxblendstages) 72 rc = sblk->blendstage_base[stage - DPU_STAGE_0]; 73 else 74 rc = -EINVAL; 75 76 return rc; 77 } 78 79 static void dpu_hw_lm_setup_out(struct dpu_hw_mixer *ctx, 80 struct dpu_hw_mixer_cfg *mixer) 81 { 82 struct dpu_hw_blk_reg_map *c = &ctx->hw; 83 u32 outsize; 84 u32 op_mode; 85 86 op_mode = DPU_REG_READ(c, LM_OP_MODE); 87 88 outsize = mixer->out_height << 16 | mixer->out_width; 89 DPU_REG_WRITE(c, LM_OUT_SIZE, outsize); 90 91 /* SPLIT_LEFT_RIGHT */ 92 if (mixer->right_mixer) 93 op_mode |= BIT(31); 94 else 95 op_mode &= ~BIT(31); 96 DPU_REG_WRITE(c, LM_OP_MODE, op_mode); 97 } 98 99 static void dpu_hw_lm_setup_border_color(struct dpu_hw_mixer *ctx, 100 struct dpu_mdss_color *color, 101 u8 border_en) 102 { 103 struct dpu_hw_blk_reg_map *c = &ctx->hw; 104 105 if (border_en) { 106 DPU_REG_WRITE(c, LM_BORDER_COLOR_0, 107 (color->color_0 & 0xFFF) | 108 ((color->color_1 & 0xFFF) << 0x10)); 109 DPU_REG_WRITE(c, LM_BORDER_COLOR_1, 110 (color->color_2 & 0xFFF) | 111 ((color->color_3 & 0xFFF) << 0x10)); 112 } 113 } 114 115 static void dpu_hw_lm_setup_blend_config_sdm845(struct dpu_hw_mixer *ctx, 116 u32 stage, u32 fg_alpha, u32 bg_alpha, u32 blend_op) 117 { 118 struct dpu_hw_blk_reg_map *c = &ctx->hw; 119 int stage_off; 120 u32 const_alpha; 121 122 if (stage == DPU_STAGE_BASE) 123 return; 124 125 stage_off = _stage_offset(ctx, stage); 126 if (WARN_ON(stage_off < 0)) 127 return; 128 129 const_alpha = (bg_alpha & 0xFF) | ((fg_alpha & 0xFF) << 16); 130 DPU_REG_WRITE(c, LM_BLEND0_CONST_ALPHA + stage_off, const_alpha); 131 DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op); 132 } 133 134 static void dpu_hw_lm_setup_blend_config(struct dpu_hw_mixer *ctx, 135 u32 stage, u32 fg_alpha, u32 bg_alpha, u32 blend_op) 136 { 137 struct dpu_hw_blk_reg_map *c = &ctx->hw; 138 int stage_off; 139 140 if (stage == DPU_STAGE_BASE) 141 return; 142 143 stage_off = _stage_offset(ctx, stage); 144 if (WARN_ON(stage_off < 0)) 145 return; 146 147 DPU_REG_WRITE(c, LM_BLEND0_FG_ALPHA + stage_off, fg_alpha); 148 DPU_REG_WRITE(c, LM_BLEND0_BG_ALPHA + stage_off, bg_alpha); 149 DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op); 150 } 151 152 static void dpu_hw_lm_setup_color3(struct dpu_hw_mixer *ctx, 153 uint32_t mixer_op_mode) 154 { 155 struct dpu_hw_blk_reg_map *c = &ctx->hw; 156 int op_mode; 157 158 /* read the existing op_mode configuration */ 159 op_mode = DPU_REG_READ(c, LM_OP_MODE); 160 161 op_mode = (op_mode & (BIT(31) | BIT(30))) | mixer_op_mode; 162 163 DPU_REG_WRITE(c, LM_OP_MODE, op_mode); 164 } 165 166 static void dpu_hw_lm_gc(struct dpu_hw_mixer *mixer, 167 void *cfg) 168 { 169 } 170 171 static void _setup_mixer_ops(struct dpu_mdss_cfg *m, 172 struct dpu_hw_lm_ops *ops, 173 unsigned long features) 174 { 175 ops->setup_mixer_out = dpu_hw_lm_setup_out; 176 if (IS_SDM845_TARGET(m->hwversion) || IS_SDM670_TARGET(m->hwversion)) 177 ops->setup_blend_config = dpu_hw_lm_setup_blend_config_sdm845; 178 else 179 ops->setup_blend_config = dpu_hw_lm_setup_blend_config; 180 ops->setup_alpha_out = dpu_hw_lm_setup_color3; 181 ops->setup_border_color = dpu_hw_lm_setup_border_color; 182 ops->setup_gc = dpu_hw_lm_gc; 183 }; 184 185 static struct dpu_hw_blk_ops dpu_hw_ops = { 186 .start = NULL, 187 .stop = NULL, 188 }; 189 190 struct dpu_hw_mixer *dpu_hw_lm_init(enum dpu_lm idx, 191 void __iomem *addr, 192 struct dpu_mdss_cfg *m) 193 { 194 struct dpu_hw_mixer *c; 195 struct dpu_lm_cfg *cfg; 196 int rc; 197 198 c = kzalloc(sizeof(*c), GFP_KERNEL); 199 if (!c) 200 return ERR_PTR(-ENOMEM); 201 202 cfg = _lm_offset(idx, m, addr, &c->hw); 203 if (IS_ERR_OR_NULL(cfg)) { 204 kfree(c); 205 return ERR_PTR(-EINVAL); 206 } 207 208 /* Assign ops */ 209 c->idx = idx; 210 c->cap = cfg; 211 _setup_mixer_ops(m, &c->ops, c->cap->features); 212 213 rc = dpu_hw_blk_init(&c->base, DPU_HW_BLK_LM, idx, &dpu_hw_ops); 214 if (rc) { 215 DPU_ERROR("failed to init hw blk %d\n", rc); 216 goto blk_init_error; 217 } 218 219 return c; 220 221 blk_init_error: 222 kzfree(c); 223 224 return ERR_PTR(rc); 225 } 226 227 void dpu_hw_lm_destroy(struct dpu_hw_mixer *lm) 228 { 229 if (lm) 230 dpu_hw_blk_destroy(&lm->base); 231 kfree(lm); 232 } 233