1 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 2 * 3 * This program is free software; you can redistribute it and/or modify 4 * it under the terms of the GNU General Public License version 2 and 5 * only version 2 as published by the Free Software Foundation. 6 * 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 */ 12 13 #include "dpu_kms.h" 14 #include "dpu_hw_catalog.h" 15 #include "dpu_hwio.h" 16 #include "dpu_hw_lm.h" 17 #include "dpu_hw_mdss.h" 18 #include "dpu_kms.h" 19 20 #define LM_OP_MODE 0x00 21 #define LM_OUT_SIZE 0x04 22 #define LM_BORDER_COLOR_0 0x08 23 #define LM_BORDER_COLOR_1 0x010 24 25 /* These register are offset to mixer base + stage base */ 26 #define LM_BLEND0_OP 0x00 27 #define LM_BLEND0_CONST_ALPHA 0x04 28 #define LM_FG_COLOR_FILL_COLOR_0 0x08 29 #define LM_FG_COLOR_FILL_COLOR_1 0x0C 30 #define LM_FG_COLOR_FILL_SIZE 0x10 31 #define LM_FG_COLOR_FILL_XY 0x14 32 33 #define LM_BLEND0_FG_ALPHA 0x04 34 #define LM_BLEND0_BG_ALPHA 0x08 35 36 static struct dpu_lm_cfg *_lm_offset(enum dpu_lm mixer, 37 struct dpu_mdss_cfg *m, 38 void __iomem *addr, 39 struct dpu_hw_blk_reg_map *b) 40 { 41 int i; 42 43 for (i = 0; i < m->mixer_count; i++) { 44 if (mixer == m->mixer[i].id) { 45 b->base_off = addr; 46 b->blk_off = m->mixer[i].base; 47 b->length = m->mixer[i].len; 48 b->hwversion = m->hwversion; 49 b->log_mask = DPU_DBG_MASK_LM; 50 return &m->mixer[i]; 51 } 52 } 53 54 return ERR_PTR(-ENOMEM); 55 } 56 57 /** 58 * _stage_offset(): returns the relative offset of the blend registers 59 * for the stage to be setup 60 * @c: mixer ctx contains the mixer to be programmed 61 * @stage: stage index to setup 62 */ 63 static inline int _stage_offset(struct dpu_hw_mixer *ctx, enum dpu_stage stage) 64 { 65 const struct dpu_lm_sub_blks *sblk = ctx->cap->sblk; 66 if (stage != DPU_STAGE_BASE && stage <= sblk->maxblendstages) 67 return sblk->blendstage_base[stage - DPU_STAGE_0]; 68 69 return -EINVAL; 70 } 71 72 static void dpu_hw_lm_setup_out(struct dpu_hw_mixer *ctx, 73 struct dpu_hw_mixer_cfg *mixer) 74 { 75 struct dpu_hw_blk_reg_map *c = &ctx->hw; 76 u32 outsize; 77 u32 op_mode; 78 79 op_mode = DPU_REG_READ(c, LM_OP_MODE); 80 81 outsize = mixer->out_height << 16 | mixer->out_width; 82 DPU_REG_WRITE(c, LM_OUT_SIZE, outsize); 83 84 /* SPLIT_LEFT_RIGHT */ 85 if (mixer->right_mixer) 86 op_mode |= BIT(31); 87 else 88 op_mode &= ~BIT(31); 89 DPU_REG_WRITE(c, LM_OP_MODE, op_mode); 90 } 91 92 static void dpu_hw_lm_setup_border_color(struct dpu_hw_mixer *ctx, 93 struct dpu_mdss_color *color, 94 u8 border_en) 95 { 96 struct dpu_hw_blk_reg_map *c = &ctx->hw; 97 98 if (border_en) { 99 DPU_REG_WRITE(c, LM_BORDER_COLOR_0, 100 (color->color_0 & 0xFFF) | 101 ((color->color_1 & 0xFFF) << 0x10)); 102 DPU_REG_WRITE(c, LM_BORDER_COLOR_1, 103 (color->color_2 & 0xFFF) | 104 ((color->color_3 & 0xFFF) << 0x10)); 105 } 106 } 107 108 static void dpu_hw_lm_setup_blend_config_sdm845(struct dpu_hw_mixer *ctx, 109 u32 stage, u32 fg_alpha, u32 bg_alpha, u32 blend_op) 110 { 111 struct dpu_hw_blk_reg_map *c = &ctx->hw; 112 int stage_off; 113 u32 const_alpha; 114 115 if (stage == DPU_STAGE_BASE) 116 return; 117 118 stage_off = _stage_offset(ctx, stage); 119 if (WARN_ON(stage_off < 0)) 120 return; 121 122 const_alpha = (bg_alpha & 0xFF) | ((fg_alpha & 0xFF) << 16); 123 DPU_REG_WRITE(c, LM_BLEND0_CONST_ALPHA + stage_off, const_alpha); 124 DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op); 125 } 126 127 static void dpu_hw_lm_setup_blend_config(struct dpu_hw_mixer *ctx, 128 u32 stage, u32 fg_alpha, u32 bg_alpha, u32 blend_op) 129 { 130 struct dpu_hw_blk_reg_map *c = &ctx->hw; 131 int stage_off; 132 133 if (stage == DPU_STAGE_BASE) 134 return; 135 136 stage_off = _stage_offset(ctx, stage); 137 if (WARN_ON(stage_off < 0)) 138 return; 139 140 DPU_REG_WRITE(c, LM_BLEND0_FG_ALPHA + stage_off, fg_alpha); 141 DPU_REG_WRITE(c, LM_BLEND0_BG_ALPHA + stage_off, bg_alpha); 142 DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op); 143 } 144 145 static void dpu_hw_lm_setup_color3(struct dpu_hw_mixer *ctx, 146 uint32_t mixer_op_mode) 147 { 148 struct dpu_hw_blk_reg_map *c = &ctx->hw; 149 int op_mode; 150 151 /* read the existing op_mode configuration */ 152 op_mode = DPU_REG_READ(c, LM_OP_MODE); 153 154 op_mode = (op_mode & (BIT(31) | BIT(30))) | mixer_op_mode; 155 156 DPU_REG_WRITE(c, LM_OP_MODE, op_mode); 157 } 158 159 static void _setup_mixer_ops(struct dpu_mdss_cfg *m, 160 struct dpu_hw_lm_ops *ops, 161 unsigned long features) 162 { 163 ops->setup_mixer_out = dpu_hw_lm_setup_out; 164 if (IS_SDM845_TARGET(m->hwversion) || IS_SDM670_TARGET(m->hwversion)) 165 ops->setup_blend_config = dpu_hw_lm_setup_blend_config_sdm845; 166 else 167 ops->setup_blend_config = dpu_hw_lm_setup_blend_config; 168 ops->setup_alpha_out = dpu_hw_lm_setup_color3; 169 ops->setup_border_color = dpu_hw_lm_setup_border_color; 170 }; 171 172 static struct dpu_hw_blk_ops dpu_hw_ops; 173 174 struct dpu_hw_mixer *dpu_hw_lm_init(enum dpu_lm idx, 175 void __iomem *addr, 176 struct dpu_mdss_cfg *m) 177 { 178 struct dpu_hw_mixer *c; 179 struct dpu_lm_cfg *cfg; 180 181 c = kzalloc(sizeof(*c), GFP_KERNEL); 182 if (!c) 183 return ERR_PTR(-ENOMEM); 184 185 cfg = _lm_offset(idx, m, addr, &c->hw); 186 if (IS_ERR_OR_NULL(cfg)) { 187 kfree(c); 188 return ERR_PTR(-EINVAL); 189 } 190 191 /* Assign ops */ 192 c->idx = idx; 193 c->cap = cfg; 194 _setup_mixer_ops(m, &c->ops, c->cap->features); 195 196 dpu_hw_blk_init(&c->base, DPU_HW_BLK_LM, idx, &dpu_hw_ops); 197 198 return c; 199 } 200 201 void dpu_hw_lm_destroy(struct dpu_hw_mixer *lm) 202 { 203 if (lm) 204 dpu_hw_blk_destroy(&lm->base); 205 kfree(lm); 206 } 207