1 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 2 * 3 * This program is free software; you can redistribute it and/or modify 4 * it under the terms of the GNU General Public License version 2 and 5 * only version 2 as published by the Free Software Foundation. 6 * 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 */ 12 13 #include "dpu_kms.h" 14 #include "dpu_hw_catalog.h" 15 #include "dpu_hwio.h" 16 #include "dpu_hw_lm.h" 17 #include "dpu_hw_mdss.h" 18 19 #define LM_OP_MODE 0x00 20 #define LM_OUT_SIZE 0x04 21 #define LM_BORDER_COLOR_0 0x08 22 #define LM_BORDER_COLOR_1 0x010 23 24 /* These register are offset to mixer base + stage base */ 25 #define LM_BLEND0_OP 0x00 26 #define LM_BLEND0_CONST_ALPHA 0x04 27 #define LM_FG_COLOR_FILL_COLOR_0 0x08 28 #define LM_FG_COLOR_FILL_COLOR_1 0x0C 29 #define LM_FG_COLOR_FILL_SIZE 0x10 30 #define LM_FG_COLOR_FILL_XY 0x14 31 32 #define LM_BLEND0_FG_ALPHA 0x04 33 #define LM_BLEND0_BG_ALPHA 0x08 34 35 static struct dpu_lm_cfg *_lm_offset(enum dpu_lm mixer, 36 struct dpu_mdss_cfg *m, 37 void __iomem *addr, 38 struct dpu_hw_blk_reg_map *b) 39 { 40 int i; 41 42 for (i = 0; i < m->mixer_count; i++) { 43 if (mixer == m->mixer[i].id) { 44 b->base_off = addr; 45 b->blk_off = m->mixer[i].base; 46 b->length = m->mixer[i].len; 47 b->hwversion = m->hwversion; 48 b->log_mask = DPU_DBG_MASK_LM; 49 return &m->mixer[i]; 50 } 51 } 52 53 return ERR_PTR(-ENOMEM); 54 } 55 56 /** 57 * _stage_offset(): returns the relative offset of the blend registers 58 * for the stage to be setup 59 * @c: mixer ctx contains the mixer to be programmed 60 * @stage: stage index to setup 61 */ 62 static inline int _stage_offset(struct dpu_hw_mixer *ctx, enum dpu_stage stage) 63 { 64 const struct dpu_lm_sub_blks *sblk = ctx->cap->sblk; 65 if (stage != DPU_STAGE_BASE && stage <= sblk->maxblendstages) 66 return sblk->blendstage_base[stage - DPU_STAGE_0]; 67 68 return -EINVAL; 69 } 70 71 static void dpu_hw_lm_setup_out(struct dpu_hw_mixer *ctx, 72 struct dpu_hw_mixer_cfg *mixer) 73 { 74 struct dpu_hw_blk_reg_map *c = &ctx->hw; 75 u32 outsize; 76 u32 op_mode; 77 78 op_mode = DPU_REG_READ(c, LM_OP_MODE); 79 80 outsize = mixer->out_height << 16 | mixer->out_width; 81 DPU_REG_WRITE(c, LM_OUT_SIZE, outsize); 82 83 /* SPLIT_LEFT_RIGHT */ 84 if (mixer->right_mixer) 85 op_mode |= BIT(31); 86 else 87 op_mode &= ~BIT(31); 88 DPU_REG_WRITE(c, LM_OP_MODE, op_mode); 89 } 90 91 static void dpu_hw_lm_setup_border_color(struct dpu_hw_mixer *ctx, 92 struct dpu_mdss_color *color, 93 u8 border_en) 94 { 95 struct dpu_hw_blk_reg_map *c = &ctx->hw; 96 97 if (border_en) { 98 DPU_REG_WRITE(c, LM_BORDER_COLOR_0, 99 (color->color_0 & 0xFFF) | 100 ((color->color_1 & 0xFFF) << 0x10)); 101 DPU_REG_WRITE(c, LM_BORDER_COLOR_1, 102 (color->color_2 & 0xFFF) | 103 ((color->color_3 & 0xFFF) << 0x10)); 104 } 105 } 106 107 static void dpu_hw_lm_setup_blend_config_sdm845(struct dpu_hw_mixer *ctx, 108 u32 stage, u32 fg_alpha, u32 bg_alpha, u32 blend_op) 109 { 110 struct dpu_hw_blk_reg_map *c = &ctx->hw; 111 int stage_off; 112 u32 const_alpha; 113 114 if (stage == DPU_STAGE_BASE) 115 return; 116 117 stage_off = _stage_offset(ctx, stage); 118 if (WARN_ON(stage_off < 0)) 119 return; 120 121 const_alpha = (bg_alpha & 0xFF) | ((fg_alpha & 0xFF) << 16); 122 DPU_REG_WRITE(c, LM_BLEND0_CONST_ALPHA + stage_off, const_alpha); 123 DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op); 124 } 125 126 static void dpu_hw_lm_setup_blend_config(struct dpu_hw_mixer *ctx, 127 u32 stage, u32 fg_alpha, u32 bg_alpha, u32 blend_op) 128 { 129 struct dpu_hw_blk_reg_map *c = &ctx->hw; 130 int stage_off; 131 132 if (stage == DPU_STAGE_BASE) 133 return; 134 135 stage_off = _stage_offset(ctx, stage); 136 if (WARN_ON(stage_off < 0)) 137 return; 138 139 DPU_REG_WRITE(c, LM_BLEND0_FG_ALPHA + stage_off, fg_alpha); 140 DPU_REG_WRITE(c, LM_BLEND0_BG_ALPHA + stage_off, bg_alpha); 141 DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op); 142 } 143 144 static void dpu_hw_lm_setup_color3(struct dpu_hw_mixer *ctx, 145 uint32_t mixer_op_mode) 146 { 147 struct dpu_hw_blk_reg_map *c = &ctx->hw; 148 int op_mode; 149 150 /* read the existing op_mode configuration */ 151 op_mode = DPU_REG_READ(c, LM_OP_MODE); 152 153 op_mode = (op_mode & (BIT(31) | BIT(30))) | mixer_op_mode; 154 155 DPU_REG_WRITE(c, LM_OP_MODE, op_mode); 156 } 157 158 static void _setup_mixer_ops(struct dpu_mdss_cfg *m, 159 struct dpu_hw_lm_ops *ops, 160 unsigned long features) 161 { 162 ops->setup_mixer_out = dpu_hw_lm_setup_out; 163 if (IS_SDM845_TARGET(m->hwversion) || IS_SDM670_TARGET(m->hwversion)) 164 ops->setup_blend_config = dpu_hw_lm_setup_blend_config_sdm845; 165 else 166 ops->setup_blend_config = dpu_hw_lm_setup_blend_config; 167 ops->setup_alpha_out = dpu_hw_lm_setup_color3; 168 ops->setup_border_color = dpu_hw_lm_setup_border_color; 169 }; 170 171 static struct dpu_hw_blk_ops dpu_hw_ops; 172 173 struct dpu_hw_mixer *dpu_hw_lm_init(enum dpu_lm idx, 174 void __iomem *addr, 175 struct dpu_mdss_cfg *m) 176 { 177 struct dpu_hw_mixer *c; 178 struct dpu_lm_cfg *cfg; 179 180 c = kzalloc(sizeof(*c), GFP_KERNEL); 181 if (!c) 182 return ERR_PTR(-ENOMEM); 183 184 cfg = _lm_offset(idx, m, addr, &c->hw); 185 if (IS_ERR_OR_NULL(cfg)) { 186 kfree(c); 187 return ERR_PTR(-EINVAL); 188 } 189 190 /* Assign ops */ 191 c->idx = idx; 192 c->cap = cfg; 193 _setup_mixer_ops(m, &c->ops, c->cap->features); 194 195 dpu_hw_blk_init(&c->base, DPU_HW_BLK_LM, idx, &dpu_hw_ops); 196 197 return c; 198 } 199 200 void dpu_hw_lm_destroy(struct dpu_hw_mixer *lm) 201 { 202 if (lm) 203 dpu_hw_blk_destroy(&lm->base); 204 kfree(lm); 205 } 206