1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved. 5 */ 6 7 #include "dpu_kms.h" 8 #include "dpu_hw_catalog.h" 9 #include "dpu_hwio.h" 10 #include "dpu_hw_lm.h" 11 #include "dpu_hw_mdss.h" 12 13 #define LM_OP_MODE 0x00 14 #define LM_OUT_SIZE 0x04 15 #define LM_BORDER_COLOR_0 0x08 16 #define LM_BORDER_COLOR_1 0x010 17 18 /* These register are offset to mixer base + stage base */ 19 #define LM_BLEND0_OP 0x00 20 #define LM_BLEND0_CONST_ALPHA 0x04 21 #define LM_FG_COLOR_FILL_COLOR_0 0x08 22 #define LM_FG_COLOR_FILL_COLOR_1 0x0C 23 #define LM_FG_COLOR_FILL_SIZE 0x10 24 #define LM_FG_COLOR_FILL_XY 0x14 25 26 #define LM_BLEND0_FG_ALPHA 0x04 27 #define LM_BLEND0_BG_ALPHA 0x08 28 29 #define LM_MISR_CTRL 0x310 30 #define LM_MISR_SIGNATURE 0x314 31 32 33 /** 34 * _stage_offset(): returns the relative offset of the blend registers 35 * for the stage to be setup 36 * @ctx: mixer ctx contains the mixer to be programmed 37 * @stage: stage index to setup 38 */ 39 static inline int _stage_offset(struct dpu_hw_mixer *ctx, enum dpu_stage stage) 40 { 41 const struct dpu_lm_sub_blks *sblk = ctx->cap->sblk; 42 if (stage != DPU_STAGE_BASE && stage <= sblk->maxblendstages) 43 return sblk->blendstage_base[stage - DPU_STAGE_0]; 44 45 return -EINVAL; 46 } 47 48 static void dpu_hw_lm_setup_out(struct dpu_hw_mixer *ctx, 49 struct dpu_hw_mixer_cfg *mixer) 50 { 51 struct dpu_hw_blk_reg_map *c = &ctx->hw; 52 u32 outsize; 53 u32 op_mode; 54 55 op_mode = DPU_REG_READ(c, LM_OP_MODE); 56 57 outsize = mixer->out_height << 16 | mixer->out_width; 58 DPU_REG_WRITE(c, LM_OUT_SIZE, outsize); 59 60 /* SPLIT_LEFT_RIGHT */ 61 if (mixer->right_mixer) 62 op_mode |= BIT(31); 63 else 64 op_mode &= ~BIT(31); 65 DPU_REG_WRITE(c, LM_OP_MODE, op_mode); 66 } 67 68 static void dpu_hw_lm_setup_border_color(struct dpu_hw_mixer *ctx, 69 struct dpu_mdss_color *color, 70 u8 border_en) 71 { 72 struct dpu_hw_blk_reg_map *c = &ctx->hw; 73 74 if (border_en) { 75 DPU_REG_WRITE(c, LM_BORDER_COLOR_0, 76 (color->color_0 & 0xFFF) | 77 ((color->color_1 & 0xFFF) << 0x10)); 78 DPU_REG_WRITE(c, LM_BORDER_COLOR_1, 79 (color->color_2 & 0xFFF) | 80 ((color->color_3 & 0xFFF) << 0x10)); 81 } 82 } 83 84 static void dpu_hw_lm_setup_misr(struct dpu_hw_mixer *ctx, bool enable, u32 frame_count) 85 { 86 dpu_hw_setup_misr(&ctx->hw, LM_MISR_CTRL, enable, frame_count); 87 } 88 89 static int dpu_hw_lm_collect_misr(struct dpu_hw_mixer *ctx, u32 *misr_value) 90 { 91 return dpu_hw_collect_misr(&ctx->hw, LM_MISR_CTRL, LM_MISR_SIGNATURE, misr_value); 92 } 93 94 static void dpu_hw_lm_setup_blend_config_combined_alpha(struct dpu_hw_mixer *ctx, 95 u32 stage, u32 fg_alpha, u32 bg_alpha, u32 blend_op) 96 { 97 struct dpu_hw_blk_reg_map *c = &ctx->hw; 98 int stage_off; 99 u32 const_alpha; 100 101 if (stage == DPU_STAGE_BASE) 102 return; 103 104 stage_off = _stage_offset(ctx, stage); 105 if (WARN_ON(stage_off < 0)) 106 return; 107 108 const_alpha = (bg_alpha & 0xFF) | ((fg_alpha & 0xFF) << 16); 109 DPU_REG_WRITE(c, LM_BLEND0_CONST_ALPHA + stage_off, const_alpha); 110 DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op); 111 } 112 113 static void dpu_hw_lm_setup_blend_config(struct dpu_hw_mixer *ctx, 114 u32 stage, u32 fg_alpha, u32 bg_alpha, u32 blend_op) 115 { 116 struct dpu_hw_blk_reg_map *c = &ctx->hw; 117 int stage_off; 118 119 if (stage == DPU_STAGE_BASE) 120 return; 121 122 stage_off = _stage_offset(ctx, stage); 123 if (WARN_ON(stage_off < 0)) 124 return; 125 126 DPU_REG_WRITE(c, LM_BLEND0_FG_ALPHA + stage_off, fg_alpha); 127 DPU_REG_WRITE(c, LM_BLEND0_BG_ALPHA + stage_off, bg_alpha); 128 DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op); 129 } 130 131 static void dpu_hw_lm_setup_color3(struct dpu_hw_mixer *ctx, 132 uint32_t mixer_op_mode) 133 { 134 struct dpu_hw_blk_reg_map *c = &ctx->hw; 135 int op_mode; 136 137 /* read the existing op_mode configuration */ 138 op_mode = DPU_REG_READ(c, LM_OP_MODE); 139 140 op_mode = (op_mode & (BIT(31) | BIT(30))) | mixer_op_mode; 141 142 DPU_REG_WRITE(c, LM_OP_MODE, op_mode); 143 } 144 145 static void _setup_mixer_ops(struct dpu_hw_lm_ops *ops, 146 unsigned long features) 147 { 148 ops->setup_mixer_out = dpu_hw_lm_setup_out; 149 if (test_bit(DPU_MIXER_COMBINED_ALPHA, &features)) 150 ops->setup_blend_config = dpu_hw_lm_setup_blend_config_combined_alpha; 151 else 152 ops->setup_blend_config = dpu_hw_lm_setup_blend_config; 153 ops->setup_alpha_out = dpu_hw_lm_setup_color3; 154 ops->setup_border_color = dpu_hw_lm_setup_border_color; 155 ops->setup_misr = dpu_hw_lm_setup_misr; 156 ops->collect_misr = dpu_hw_lm_collect_misr; 157 } 158 159 struct dpu_hw_mixer *dpu_hw_lm_init(const struct dpu_lm_cfg *cfg, 160 void __iomem *addr) 161 { 162 struct dpu_hw_mixer *c; 163 164 if (cfg->pingpong == PINGPONG_NONE) { 165 DPU_DEBUG("skip mixer %d without pingpong\n", cfg->id); 166 return NULL; 167 } 168 169 c = kzalloc(sizeof(*c), GFP_KERNEL); 170 if (!c) 171 return ERR_PTR(-ENOMEM); 172 173 c->hw.blk_addr = addr + cfg->base; 174 c->hw.log_mask = DPU_DBG_MASK_LM; 175 176 /* Assign ops */ 177 c->idx = cfg->id; 178 c->cap = cfg; 179 _setup_mixer_ops(&c->ops, c->cap->features); 180 181 return c; 182 } 183 184 void dpu_hw_lm_destroy(struct dpu_hw_mixer *lm) 185 { 186 kfree(lm); 187 } 188