197fb5e8dSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 225fdd593SJeykumar Sankaran /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 325fdd593SJeykumar Sankaran */ 425fdd593SJeykumar Sankaran 525fdd593SJeykumar Sankaran #include "dpu_kms.h" 625fdd593SJeykumar Sankaran #include "dpu_hw_catalog.h" 725fdd593SJeykumar Sankaran #include "dpu_hwio.h" 825fdd593SJeykumar Sankaran #include "dpu_hw_lm.h" 925fdd593SJeykumar Sankaran #include "dpu_hw_mdss.h" 1025fdd593SJeykumar Sankaran 1125fdd593SJeykumar Sankaran #define LM_OP_MODE 0x00 1225fdd593SJeykumar Sankaran #define LM_OUT_SIZE 0x04 1325fdd593SJeykumar Sankaran #define LM_BORDER_COLOR_0 0x08 1425fdd593SJeykumar Sankaran #define LM_BORDER_COLOR_1 0x010 1525fdd593SJeykumar Sankaran 1625fdd593SJeykumar Sankaran /* These register are offset to mixer base + stage base */ 1725fdd593SJeykumar Sankaran #define LM_BLEND0_OP 0x00 1825fdd593SJeykumar Sankaran #define LM_BLEND0_CONST_ALPHA 0x04 1925fdd593SJeykumar Sankaran #define LM_FG_COLOR_FILL_COLOR_0 0x08 2025fdd593SJeykumar Sankaran #define LM_FG_COLOR_FILL_COLOR_1 0x0C 2125fdd593SJeykumar Sankaran #define LM_FG_COLOR_FILL_SIZE 0x10 2225fdd593SJeykumar Sankaran #define LM_FG_COLOR_FILL_XY 0x14 2325fdd593SJeykumar Sankaran 2425fdd593SJeykumar Sankaran #define LM_BLEND0_FG_ALPHA 0x04 2525fdd593SJeykumar Sankaran #define LM_BLEND0_BG_ALPHA 0x08 2625fdd593SJeykumar Sankaran 27abda0d92SStephen Boyd static const struct dpu_lm_cfg *_lm_offset(enum dpu_lm mixer, 28abda0d92SStephen Boyd const struct dpu_mdss_cfg *m, 2925fdd593SJeykumar Sankaran void __iomem *addr, 3025fdd593SJeykumar Sankaran struct dpu_hw_blk_reg_map *b) 3125fdd593SJeykumar Sankaran { 3225fdd593SJeykumar Sankaran int i; 3325fdd593SJeykumar Sankaran 3425fdd593SJeykumar Sankaran for (i = 0; i < m->mixer_count; i++) { 3525fdd593SJeykumar Sankaran if (mixer == m->mixer[i].id) { 3625fdd593SJeykumar Sankaran b->base_off = addr; 3725fdd593SJeykumar Sankaran b->blk_off = m->mixer[i].base; 3825fdd593SJeykumar Sankaran b->length = m->mixer[i].len; 3925fdd593SJeykumar Sankaran b->hwversion = m->hwversion; 4025fdd593SJeykumar Sankaran b->log_mask = DPU_DBG_MASK_LM; 4125fdd593SJeykumar Sankaran return &m->mixer[i]; 4225fdd593SJeykumar Sankaran } 4325fdd593SJeykumar Sankaran } 4425fdd593SJeykumar Sankaran 4525fdd593SJeykumar Sankaran return ERR_PTR(-ENOMEM); 4625fdd593SJeykumar Sankaran } 4725fdd593SJeykumar Sankaran 4825fdd593SJeykumar Sankaran /** 4925fdd593SJeykumar Sankaran * _stage_offset(): returns the relative offset of the blend registers 5025fdd593SJeykumar Sankaran * for the stage to be setup 51*0177aef3SLee Jones * @ctx: mixer ctx contains the mixer to be programmed 5225fdd593SJeykumar Sankaran * @stage: stage index to setup 5325fdd593SJeykumar Sankaran */ 5425fdd593SJeykumar Sankaran static inline int _stage_offset(struct dpu_hw_mixer *ctx, enum dpu_stage stage) 5525fdd593SJeykumar Sankaran { 5625fdd593SJeykumar Sankaran const struct dpu_lm_sub_blks *sblk = ctx->cap->sblk; 5758fba464SSean Paul if (stage != DPU_STAGE_BASE && stage <= sblk->maxblendstages) 5858fba464SSean Paul return sblk->blendstage_base[stage - DPU_STAGE_0]; 5925fdd593SJeykumar Sankaran 6058fba464SSean Paul return -EINVAL; 6125fdd593SJeykumar Sankaran } 6225fdd593SJeykumar Sankaran 6325fdd593SJeykumar Sankaran static void dpu_hw_lm_setup_out(struct dpu_hw_mixer *ctx, 6425fdd593SJeykumar Sankaran struct dpu_hw_mixer_cfg *mixer) 6525fdd593SJeykumar Sankaran { 6625fdd593SJeykumar Sankaran struct dpu_hw_blk_reg_map *c = &ctx->hw; 6725fdd593SJeykumar Sankaran u32 outsize; 6825fdd593SJeykumar Sankaran u32 op_mode; 6925fdd593SJeykumar Sankaran 7025fdd593SJeykumar Sankaran op_mode = DPU_REG_READ(c, LM_OP_MODE); 7125fdd593SJeykumar Sankaran 7225fdd593SJeykumar Sankaran outsize = mixer->out_height << 16 | mixer->out_width; 7325fdd593SJeykumar Sankaran DPU_REG_WRITE(c, LM_OUT_SIZE, outsize); 7425fdd593SJeykumar Sankaran 7525fdd593SJeykumar Sankaran /* SPLIT_LEFT_RIGHT */ 7625fdd593SJeykumar Sankaran if (mixer->right_mixer) 7725fdd593SJeykumar Sankaran op_mode |= BIT(31); 7825fdd593SJeykumar Sankaran else 7925fdd593SJeykumar Sankaran op_mode &= ~BIT(31); 8025fdd593SJeykumar Sankaran DPU_REG_WRITE(c, LM_OP_MODE, op_mode); 8125fdd593SJeykumar Sankaran } 8225fdd593SJeykumar Sankaran 8325fdd593SJeykumar Sankaran static void dpu_hw_lm_setup_border_color(struct dpu_hw_mixer *ctx, 8425fdd593SJeykumar Sankaran struct dpu_mdss_color *color, 8525fdd593SJeykumar Sankaran u8 border_en) 8625fdd593SJeykumar Sankaran { 8725fdd593SJeykumar Sankaran struct dpu_hw_blk_reg_map *c = &ctx->hw; 8825fdd593SJeykumar Sankaran 8925fdd593SJeykumar Sankaran if (border_en) { 9025fdd593SJeykumar Sankaran DPU_REG_WRITE(c, LM_BORDER_COLOR_0, 9125fdd593SJeykumar Sankaran (color->color_0 & 0xFFF) | 9225fdd593SJeykumar Sankaran ((color->color_1 & 0xFFF) << 0x10)); 9325fdd593SJeykumar Sankaran DPU_REG_WRITE(c, LM_BORDER_COLOR_1, 9425fdd593SJeykumar Sankaran (color->color_2 & 0xFFF) | 9525fdd593SJeykumar Sankaran ((color->color_3 & 0xFFF) << 0x10)); 9625fdd593SJeykumar Sankaran } 9725fdd593SJeykumar Sankaran } 9825fdd593SJeykumar Sankaran 9925fdd593SJeykumar Sankaran static void dpu_hw_lm_setup_blend_config_sdm845(struct dpu_hw_mixer *ctx, 10025fdd593SJeykumar Sankaran u32 stage, u32 fg_alpha, u32 bg_alpha, u32 blend_op) 10125fdd593SJeykumar Sankaran { 10225fdd593SJeykumar Sankaran struct dpu_hw_blk_reg_map *c = &ctx->hw; 10325fdd593SJeykumar Sankaran int stage_off; 10425fdd593SJeykumar Sankaran u32 const_alpha; 10525fdd593SJeykumar Sankaran 10625fdd593SJeykumar Sankaran if (stage == DPU_STAGE_BASE) 10725fdd593SJeykumar Sankaran return; 10825fdd593SJeykumar Sankaran 10925fdd593SJeykumar Sankaran stage_off = _stage_offset(ctx, stage); 11025fdd593SJeykumar Sankaran if (WARN_ON(stage_off < 0)) 11125fdd593SJeykumar Sankaran return; 11225fdd593SJeykumar Sankaran 11325fdd593SJeykumar Sankaran const_alpha = (bg_alpha & 0xFF) | ((fg_alpha & 0xFF) << 16); 11425fdd593SJeykumar Sankaran DPU_REG_WRITE(c, LM_BLEND0_CONST_ALPHA + stage_off, const_alpha); 11525fdd593SJeykumar Sankaran DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op); 11625fdd593SJeykumar Sankaran } 11725fdd593SJeykumar Sankaran 11825fdd593SJeykumar Sankaran static void dpu_hw_lm_setup_blend_config(struct dpu_hw_mixer *ctx, 11925fdd593SJeykumar Sankaran u32 stage, u32 fg_alpha, u32 bg_alpha, u32 blend_op) 12025fdd593SJeykumar Sankaran { 12125fdd593SJeykumar Sankaran struct dpu_hw_blk_reg_map *c = &ctx->hw; 12225fdd593SJeykumar Sankaran int stage_off; 12325fdd593SJeykumar Sankaran 12425fdd593SJeykumar Sankaran if (stage == DPU_STAGE_BASE) 12525fdd593SJeykumar Sankaran return; 12625fdd593SJeykumar Sankaran 12725fdd593SJeykumar Sankaran stage_off = _stage_offset(ctx, stage); 12825fdd593SJeykumar Sankaran if (WARN_ON(stage_off < 0)) 12925fdd593SJeykumar Sankaran return; 13025fdd593SJeykumar Sankaran 13125fdd593SJeykumar Sankaran DPU_REG_WRITE(c, LM_BLEND0_FG_ALPHA + stage_off, fg_alpha); 13225fdd593SJeykumar Sankaran DPU_REG_WRITE(c, LM_BLEND0_BG_ALPHA + stage_off, bg_alpha); 13325fdd593SJeykumar Sankaran DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op); 13425fdd593SJeykumar Sankaran } 13525fdd593SJeykumar Sankaran 13625fdd593SJeykumar Sankaran static void dpu_hw_lm_setup_color3(struct dpu_hw_mixer *ctx, 13725fdd593SJeykumar Sankaran uint32_t mixer_op_mode) 13825fdd593SJeykumar Sankaran { 13925fdd593SJeykumar Sankaran struct dpu_hw_blk_reg_map *c = &ctx->hw; 14025fdd593SJeykumar Sankaran int op_mode; 14125fdd593SJeykumar Sankaran 14225fdd593SJeykumar Sankaran /* read the existing op_mode configuration */ 14325fdd593SJeykumar Sankaran op_mode = DPU_REG_READ(c, LM_OP_MODE); 14425fdd593SJeykumar Sankaran 14525fdd593SJeykumar Sankaran op_mode = (op_mode & (BIT(31) | BIT(30))) | mixer_op_mode; 14625fdd593SJeykumar Sankaran 14725fdd593SJeykumar Sankaran DPU_REG_WRITE(c, LM_OP_MODE, op_mode); 14825fdd593SJeykumar Sankaran } 14925fdd593SJeykumar Sankaran 150abda0d92SStephen Boyd static void _setup_mixer_ops(const struct dpu_mdss_cfg *m, 15125fdd593SJeykumar Sankaran struct dpu_hw_lm_ops *ops, 15225fdd593SJeykumar Sankaran unsigned long features) 15325fdd593SJeykumar Sankaran { 15425fdd593SJeykumar Sankaran ops->setup_mixer_out = dpu_hw_lm_setup_out; 155de321dccSJonathan Marek if (m->hwversion >= DPU_HW_VER_400) 15625fdd593SJeykumar Sankaran ops->setup_blend_config = dpu_hw_lm_setup_blend_config_sdm845; 15725fdd593SJeykumar Sankaran else 15825fdd593SJeykumar Sankaran ops->setup_blend_config = dpu_hw_lm_setup_blend_config; 15925fdd593SJeykumar Sankaran ops->setup_alpha_out = dpu_hw_lm_setup_color3; 16025fdd593SJeykumar Sankaran ops->setup_border_color = dpu_hw_lm_setup_border_color; 161de321dccSJonathan Marek } 16225fdd593SJeykumar Sankaran 16353edf462SJordan Crouse static struct dpu_hw_blk_ops dpu_hw_ops; 16425fdd593SJeykumar Sankaran 16525fdd593SJeykumar Sankaran struct dpu_hw_mixer *dpu_hw_lm_init(enum dpu_lm idx, 16625fdd593SJeykumar Sankaran void __iomem *addr, 167abda0d92SStephen Boyd const struct dpu_mdss_cfg *m) 16825fdd593SJeykumar Sankaran { 16925fdd593SJeykumar Sankaran struct dpu_hw_mixer *c; 170abda0d92SStephen Boyd const struct dpu_lm_cfg *cfg; 17125fdd593SJeykumar Sankaran 17225fdd593SJeykumar Sankaran c = kzalloc(sizeof(*c), GFP_KERNEL); 17325fdd593SJeykumar Sankaran if (!c) 17425fdd593SJeykumar Sankaran return ERR_PTR(-ENOMEM); 17525fdd593SJeykumar Sankaran 17625fdd593SJeykumar Sankaran cfg = _lm_offset(idx, m, addr, &c->hw); 17725fdd593SJeykumar Sankaran if (IS_ERR_OR_NULL(cfg)) { 17825fdd593SJeykumar Sankaran kfree(c); 17925fdd593SJeykumar Sankaran return ERR_PTR(-EINVAL); 18025fdd593SJeykumar Sankaran } 18125fdd593SJeykumar Sankaran 18225fdd593SJeykumar Sankaran /* Assign ops */ 18325fdd593SJeykumar Sankaran c->idx = idx; 18425fdd593SJeykumar Sankaran c->cap = cfg; 18525fdd593SJeykumar Sankaran _setup_mixer_ops(m, &c->ops, c->cap->features); 18625fdd593SJeykumar Sankaran 18753edf462SJordan Crouse dpu_hw_blk_init(&c->base, DPU_HW_BLK_LM, idx, &dpu_hw_ops); 18825fdd593SJeykumar Sankaran 18925fdd593SJeykumar Sankaran return c; 19025fdd593SJeykumar Sankaran } 19125fdd593SJeykumar Sankaran 19225fdd593SJeykumar Sankaran void dpu_hw_lm_destroy(struct dpu_hw_mixer *lm) 19325fdd593SJeykumar Sankaran { 19425fdd593SJeykumar Sankaran if (lm) 19525fdd593SJeykumar Sankaran dpu_hw_blk_destroy(&lm->base); 19625fdd593SJeykumar Sankaran kfree(lm); 19725fdd593SJeykumar Sankaran } 198