1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 5 */ 6 7 #include "dpu_hwio.h" 8 #include "dpu_hw_catalog.h" 9 #include "dpu_hw_intf.h" 10 #include "dpu_kms.h" 11 12 #define INTF_TIMING_ENGINE_EN 0x000 13 #define INTF_CONFIG 0x004 14 #define INTF_HSYNC_CTL 0x008 15 #define INTF_VSYNC_PERIOD_F0 0x00C 16 #define INTF_VSYNC_PERIOD_F1 0x010 17 #define INTF_VSYNC_PULSE_WIDTH_F0 0x014 18 #define INTF_VSYNC_PULSE_WIDTH_F1 0x018 19 #define INTF_DISPLAY_V_START_F0 0x01C 20 #define INTF_DISPLAY_V_START_F1 0x020 21 #define INTF_DISPLAY_V_END_F0 0x024 22 #define INTF_DISPLAY_V_END_F1 0x028 23 #define INTF_ACTIVE_V_START_F0 0x02C 24 #define INTF_ACTIVE_V_START_F1 0x030 25 #define INTF_ACTIVE_V_END_F0 0x034 26 #define INTF_ACTIVE_V_END_F1 0x038 27 #define INTF_DISPLAY_HCTL 0x03C 28 #define INTF_ACTIVE_HCTL 0x040 29 #define INTF_BORDER_COLOR 0x044 30 #define INTF_UNDERFLOW_COLOR 0x048 31 #define INTF_HSYNC_SKEW 0x04C 32 #define INTF_POLARITY_CTL 0x050 33 #define INTF_TEST_CTL 0x054 34 #define INTF_TP_COLOR0 0x058 35 #define INTF_TP_COLOR1 0x05C 36 #define INTF_CONFIG2 0x060 37 #define INTF_DISPLAY_DATA_HCTL 0x064 38 #define INTF_ACTIVE_DATA_HCTL 0x068 39 #define INTF_FRAME_LINE_COUNT_EN 0x0A8 40 #define INTF_FRAME_COUNT 0x0AC 41 #define INTF_LINE_COUNT 0x0B0 42 43 #define INTF_DEFLICKER_CONFIG 0x0F0 44 #define INTF_DEFLICKER_STRNG_COEFF 0x0F4 45 #define INTF_DEFLICKER_WEAK_COEFF 0x0F8 46 47 #define INTF_DSI_CMD_MODE_TRIGGER_EN 0x084 48 #define INTF_PANEL_FORMAT 0x090 49 #define INTF_TPG_ENABLE 0x100 50 #define INTF_TPG_MAIN_CONTROL 0x104 51 #define INTF_TPG_VIDEO_CONFIG 0x108 52 #define INTF_TPG_COMPONENT_LIMITS 0x10C 53 #define INTF_TPG_RECTANGLE 0x110 54 #define INTF_TPG_INITIAL_VALUE 0x114 55 #define INTF_TPG_BLK_WHITE_PATTERN_FRAMES 0x118 56 #define INTF_TPG_RGB_MAPPING 0x11C 57 #define INTF_PROG_FETCH_START 0x170 58 #define INTF_PROG_ROT_START 0x174 59 #define INTF_MUX 0x25C 60 #define INTF_STATUS 0x26C 61 62 #define INTF_CFG_ACTIVE_H_EN BIT(29) 63 #define INTF_CFG_ACTIVE_V_EN BIT(30) 64 65 #define INTF_CFG2_DATABUS_WIDEN BIT(0) 66 #define INTF_CFG2_DATA_HCTL_EN BIT(4) 67 68 #define INTF_MISR_CTRL 0x180 69 #define INTF_MISR_SIGNATURE 0x184 70 71 static const struct dpu_intf_cfg *_intf_offset(enum dpu_intf intf, 72 const struct dpu_mdss_cfg *m, 73 void __iomem *addr, 74 struct dpu_hw_blk_reg_map *b) 75 { 76 int i; 77 78 for (i = 0; i < m->intf_count; i++) { 79 if ((intf == m->intf[i].id) && 80 (m->intf[i].type != INTF_NONE)) { 81 b->blk_addr = addr + m->intf[i].base; 82 b->log_mask = DPU_DBG_MASK_INTF; 83 return &m->intf[i]; 84 } 85 } 86 87 return ERR_PTR(-EINVAL); 88 } 89 90 static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, 91 const struct intf_timing_params *p, 92 const struct dpu_format *fmt) 93 { 94 struct dpu_hw_blk_reg_map *c = &ctx->hw; 95 u32 hsync_period, vsync_period; 96 u32 display_v_start, display_v_end; 97 u32 hsync_start_x, hsync_end_x; 98 u32 hsync_data_start_x, hsync_data_end_x; 99 u32 active_h_start, active_h_end; 100 u32 active_v_start, active_v_end; 101 u32 active_hctl, display_hctl, hsync_ctl; 102 u32 polarity_ctl, den_polarity, hsync_polarity, vsync_polarity; 103 u32 panel_format; 104 u32 intf_cfg, intf_cfg2 = 0; 105 u32 display_data_hctl = 0, active_data_hctl = 0; 106 u32 data_width; 107 bool dp_intf = false; 108 109 /* read interface_cfg */ 110 intf_cfg = DPU_REG_READ(c, INTF_CONFIG); 111 112 if (ctx->cap->type == INTF_DP) 113 dp_intf = true; 114 115 hsync_period = p->hsync_pulse_width + p->h_back_porch + p->width + 116 p->h_front_porch; 117 vsync_period = p->vsync_pulse_width + p->v_back_porch + p->height + 118 p->v_front_porch; 119 120 display_v_start = ((p->vsync_pulse_width + p->v_back_porch) * 121 hsync_period) + p->hsync_skew; 122 display_v_end = ((vsync_period - p->v_front_porch) * hsync_period) + 123 p->hsync_skew - 1; 124 125 hsync_start_x = p->h_back_porch + p->hsync_pulse_width; 126 hsync_end_x = hsync_period - p->h_front_porch - 1; 127 128 if (p->width != p->xres) { /* border fill added */ 129 active_h_start = hsync_start_x; 130 active_h_end = active_h_start + p->xres - 1; 131 } else { 132 active_h_start = 0; 133 active_h_end = 0; 134 } 135 136 if (p->height != p->yres) { /* border fill added */ 137 active_v_start = display_v_start; 138 active_v_end = active_v_start + (p->yres * hsync_period) - 1; 139 } else { 140 active_v_start = 0; 141 active_v_end = 0; 142 } 143 144 if (active_h_end) { 145 active_hctl = (active_h_end << 16) | active_h_start; 146 intf_cfg |= INTF_CFG_ACTIVE_H_EN; 147 } else { 148 active_hctl = 0; 149 } 150 151 if (active_v_end) 152 intf_cfg |= INTF_CFG_ACTIVE_V_EN; 153 154 hsync_ctl = (hsync_period << 16) | p->hsync_pulse_width; 155 display_hctl = (hsync_end_x << 16) | hsync_start_x; 156 157 /* 158 * DATA_HCTL_EN controls data timing which can be different from 159 * video timing. It is recommended to enable it for all cases, except 160 * if compression is enabled in 1 pixel per clock mode 161 */ 162 if (p->wide_bus_en) 163 intf_cfg2 |= INTF_CFG2_DATABUS_WIDEN | INTF_CFG2_DATA_HCTL_EN; 164 165 data_width = p->width; 166 167 hsync_data_start_x = hsync_start_x; 168 hsync_data_end_x = hsync_start_x + data_width - 1; 169 170 display_data_hctl = (hsync_data_end_x << 16) | hsync_data_start_x; 171 172 if (dp_intf) { 173 /* DP timing adjustment */ 174 display_v_start += p->hsync_pulse_width + p->h_back_porch; 175 display_v_end -= p->h_front_porch; 176 177 active_h_start = hsync_start_x; 178 active_h_end = active_h_start + p->xres - 1; 179 active_v_start = display_v_start; 180 active_v_end = active_v_start + (p->yres * hsync_period) - 1; 181 182 active_hctl = (active_h_end << 16) | active_h_start; 183 display_hctl = active_hctl; 184 185 intf_cfg |= INTF_CFG_ACTIVE_H_EN | INTF_CFG_ACTIVE_V_EN; 186 } 187 188 den_polarity = 0; 189 if (ctx->cap->type == INTF_HDMI) { 190 hsync_polarity = p->yres >= 720 ? 0 : 1; 191 vsync_polarity = p->yres >= 720 ? 0 : 1; 192 } else if (ctx->cap->type == INTF_DP) { 193 hsync_polarity = p->hsync_polarity; 194 vsync_polarity = p->vsync_polarity; 195 } else { 196 hsync_polarity = 0; 197 vsync_polarity = 0; 198 } 199 polarity_ctl = (den_polarity << 2) | /* DEN Polarity */ 200 (vsync_polarity << 1) | /* VSYNC Polarity */ 201 (hsync_polarity << 0); /* HSYNC Polarity */ 202 203 if (!DPU_FORMAT_IS_YUV(fmt)) 204 panel_format = (fmt->bits[C0_G_Y] | 205 (fmt->bits[C1_B_Cb] << 2) | 206 (fmt->bits[C2_R_Cr] << 4) | 207 (0x21 << 8)); 208 else 209 /* Interface treats all the pixel data in RGB888 format */ 210 panel_format = (COLOR_8BIT | 211 (COLOR_8BIT << 2) | 212 (COLOR_8BIT << 4) | 213 (0x21 << 8)); 214 215 DPU_REG_WRITE(c, INTF_HSYNC_CTL, hsync_ctl); 216 DPU_REG_WRITE(c, INTF_VSYNC_PERIOD_F0, vsync_period * hsync_period); 217 DPU_REG_WRITE(c, INTF_VSYNC_PULSE_WIDTH_F0, 218 p->vsync_pulse_width * hsync_period); 219 DPU_REG_WRITE(c, INTF_DISPLAY_HCTL, display_hctl); 220 DPU_REG_WRITE(c, INTF_DISPLAY_V_START_F0, display_v_start); 221 DPU_REG_WRITE(c, INTF_DISPLAY_V_END_F0, display_v_end); 222 DPU_REG_WRITE(c, INTF_ACTIVE_HCTL, active_hctl); 223 DPU_REG_WRITE(c, INTF_ACTIVE_V_START_F0, active_v_start); 224 DPU_REG_WRITE(c, INTF_ACTIVE_V_END_F0, active_v_end); 225 DPU_REG_WRITE(c, INTF_BORDER_COLOR, p->border_clr); 226 DPU_REG_WRITE(c, INTF_UNDERFLOW_COLOR, p->underflow_clr); 227 DPU_REG_WRITE(c, INTF_HSYNC_SKEW, p->hsync_skew); 228 DPU_REG_WRITE(c, INTF_POLARITY_CTL, polarity_ctl); 229 DPU_REG_WRITE(c, INTF_FRAME_LINE_COUNT_EN, 0x3); 230 DPU_REG_WRITE(c, INTF_CONFIG, intf_cfg); 231 DPU_REG_WRITE(c, INTF_PANEL_FORMAT, panel_format); 232 if (ctx->cap->features & BIT(DPU_DATA_HCTL_EN)) { 233 DPU_REG_WRITE(c, INTF_CONFIG2, intf_cfg2); 234 DPU_REG_WRITE(c, INTF_DISPLAY_DATA_HCTL, display_data_hctl); 235 DPU_REG_WRITE(c, INTF_ACTIVE_DATA_HCTL, active_data_hctl); 236 } 237 } 238 239 static void dpu_hw_intf_enable_timing_engine( 240 struct dpu_hw_intf *intf, 241 u8 enable) 242 { 243 struct dpu_hw_blk_reg_map *c = &intf->hw; 244 /* Note: Display interface select is handled in top block hw layer */ 245 DPU_REG_WRITE(c, INTF_TIMING_ENGINE_EN, enable != 0); 246 } 247 248 static void dpu_hw_intf_setup_prg_fetch( 249 struct dpu_hw_intf *intf, 250 const struct intf_prog_fetch *fetch) 251 { 252 struct dpu_hw_blk_reg_map *c = &intf->hw; 253 int fetch_enable; 254 255 /* 256 * Fetch should always be outside the active lines. If the fetching 257 * is programmed within active region, hardware behavior is unknown. 258 */ 259 260 fetch_enable = DPU_REG_READ(c, INTF_CONFIG); 261 if (fetch->enable) { 262 fetch_enable |= BIT(31); 263 DPU_REG_WRITE(c, INTF_PROG_FETCH_START, 264 fetch->fetch_start); 265 } else { 266 fetch_enable &= ~BIT(31); 267 } 268 269 DPU_REG_WRITE(c, INTF_CONFIG, fetch_enable); 270 } 271 272 static void dpu_hw_intf_bind_pingpong_blk( 273 struct dpu_hw_intf *intf, 274 bool enable, 275 const enum dpu_pingpong pp) 276 { 277 struct dpu_hw_blk_reg_map *c = &intf->hw; 278 u32 mux_cfg; 279 280 mux_cfg = DPU_REG_READ(c, INTF_MUX); 281 mux_cfg &= ~0xf; 282 283 if (enable) 284 mux_cfg |= (pp - PINGPONG_0) & 0x7; 285 else 286 mux_cfg |= 0xf; 287 288 DPU_REG_WRITE(c, INTF_MUX, mux_cfg); 289 } 290 291 static void dpu_hw_intf_get_status( 292 struct dpu_hw_intf *intf, 293 struct intf_status *s) 294 { 295 struct dpu_hw_blk_reg_map *c = &intf->hw; 296 unsigned long cap = intf->cap->features; 297 298 if (cap & BIT(DPU_INTF_STATUS_SUPPORTED)) 299 s->is_en = DPU_REG_READ(c, INTF_STATUS) & BIT(0); 300 else 301 s->is_en = DPU_REG_READ(c, INTF_TIMING_ENGINE_EN); 302 303 s->is_prog_fetch_en = !!(DPU_REG_READ(c, INTF_CONFIG) & BIT(31)); 304 if (s->is_en) { 305 s->frame_count = DPU_REG_READ(c, INTF_FRAME_COUNT); 306 s->line_count = DPU_REG_READ(c, INTF_LINE_COUNT); 307 } else { 308 s->line_count = 0; 309 s->frame_count = 0; 310 } 311 } 312 313 static u32 dpu_hw_intf_get_line_count(struct dpu_hw_intf *intf) 314 { 315 struct dpu_hw_blk_reg_map *c; 316 317 if (!intf) 318 return 0; 319 320 c = &intf->hw; 321 322 return DPU_REG_READ(c, INTF_LINE_COUNT); 323 } 324 325 static void dpu_hw_intf_setup_misr(struct dpu_hw_intf *intf, bool enable, u32 frame_count) 326 { 327 dpu_hw_setup_misr(&intf->hw, INTF_MISR_CTRL, enable, frame_count); 328 } 329 330 static int dpu_hw_intf_collect_misr(struct dpu_hw_intf *intf, u32 *misr_value) 331 { 332 return dpu_hw_collect_misr(&intf->hw, INTF_MISR_CTRL, INTF_MISR_SIGNATURE, misr_value); 333 } 334 335 static void _setup_intf_ops(struct dpu_hw_intf_ops *ops, 336 unsigned long cap) 337 { 338 ops->setup_timing_gen = dpu_hw_intf_setup_timing_engine; 339 ops->setup_prg_fetch = dpu_hw_intf_setup_prg_fetch; 340 ops->get_status = dpu_hw_intf_get_status; 341 ops->enable_timing = dpu_hw_intf_enable_timing_engine; 342 ops->get_line_count = dpu_hw_intf_get_line_count; 343 if (cap & BIT(DPU_INTF_INPUT_CTRL)) 344 ops->bind_pingpong_blk = dpu_hw_intf_bind_pingpong_blk; 345 ops->setup_misr = dpu_hw_intf_setup_misr; 346 ops->collect_misr = dpu_hw_intf_collect_misr; 347 } 348 349 struct dpu_hw_intf *dpu_hw_intf_init(enum dpu_intf idx, 350 void __iomem *addr, 351 const struct dpu_mdss_cfg *m) 352 { 353 struct dpu_hw_intf *c; 354 const struct dpu_intf_cfg *cfg; 355 356 c = kzalloc(sizeof(*c), GFP_KERNEL); 357 if (!c) 358 return ERR_PTR(-ENOMEM); 359 360 cfg = _intf_offset(idx, m, addr, &c->hw); 361 if (IS_ERR_OR_NULL(cfg)) { 362 kfree(c); 363 pr_err("failed to create dpu_hw_intf %d\n", idx); 364 return ERR_PTR(-EINVAL); 365 } 366 367 /* 368 * Assign ops 369 */ 370 c->idx = idx; 371 c->cap = cfg; 372 c->mdss = m; 373 _setup_intf_ops(&c->ops, c->cap->features); 374 375 return c; 376 } 377 378 void dpu_hw_intf_destroy(struct dpu_hw_intf *intf) 379 { 380 kfree(intf); 381 } 382 383