1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 5 */ 6 7 #include "dpu_hwio.h" 8 #include "dpu_hw_catalog.h" 9 #include "dpu_hw_intf.h" 10 #include "dpu_kms.h" 11 12 #define INTF_TIMING_ENGINE_EN 0x000 13 #define INTF_CONFIG 0x004 14 #define INTF_HSYNC_CTL 0x008 15 #define INTF_VSYNC_PERIOD_F0 0x00C 16 #define INTF_VSYNC_PERIOD_F1 0x010 17 #define INTF_VSYNC_PULSE_WIDTH_F0 0x014 18 #define INTF_VSYNC_PULSE_WIDTH_F1 0x018 19 #define INTF_DISPLAY_V_START_F0 0x01C 20 #define INTF_DISPLAY_V_START_F1 0x020 21 #define INTF_DISPLAY_V_END_F0 0x024 22 #define INTF_DISPLAY_V_END_F1 0x028 23 #define INTF_ACTIVE_V_START_F0 0x02C 24 #define INTF_ACTIVE_V_START_F1 0x030 25 #define INTF_ACTIVE_V_END_F0 0x034 26 #define INTF_ACTIVE_V_END_F1 0x038 27 #define INTF_DISPLAY_HCTL 0x03C 28 #define INTF_ACTIVE_HCTL 0x040 29 #define INTF_BORDER_COLOR 0x044 30 #define INTF_UNDERFLOW_COLOR 0x048 31 #define INTF_HSYNC_SKEW 0x04C 32 #define INTF_POLARITY_CTL 0x050 33 #define INTF_TEST_CTL 0x054 34 #define INTF_TP_COLOR0 0x058 35 #define INTF_TP_COLOR1 0x05C 36 #define INTF_CONFIG2 0x060 37 #define INTF_DISPLAY_DATA_HCTL 0x064 38 #define INTF_ACTIVE_DATA_HCTL 0x068 39 #define INTF_FRAME_LINE_COUNT_EN 0x0A8 40 #define INTF_FRAME_COUNT 0x0AC 41 #define INTF_LINE_COUNT 0x0B0 42 43 #define INTF_DEFLICKER_CONFIG 0x0F0 44 #define INTF_DEFLICKER_STRNG_COEFF 0x0F4 45 #define INTF_DEFLICKER_WEAK_COEFF 0x0F8 46 47 #define INTF_DSI_CMD_MODE_TRIGGER_EN 0x084 48 #define INTF_PANEL_FORMAT 0x090 49 #define INTF_TPG_ENABLE 0x100 50 #define INTF_TPG_MAIN_CONTROL 0x104 51 #define INTF_TPG_VIDEO_CONFIG 0x108 52 #define INTF_TPG_COMPONENT_LIMITS 0x10C 53 #define INTF_TPG_RECTANGLE 0x110 54 #define INTF_TPG_INITIAL_VALUE 0x114 55 #define INTF_TPG_BLK_WHITE_PATTERN_FRAMES 0x118 56 #define INTF_TPG_RGB_MAPPING 0x11C 57 #define INTF_PROG_FETCH_START 0x170 58 #define INTF_PROG_ROT_START 0x174 59 60 #define INTF_FRAME_LINE_COUNT_EN 0x0A8 61 #define INTF_FRAME_COUNT 0x0AC 62 #define INTF_LINE_COUNT 0x0B0 63 64 #define INTF_MUX 0x25C 65 #define INTF_STATUS 0x26C 66 67 #define INTF_CFG_ACTIVE_H_EN BIT(29) 68 #define INTF_CFG_ACTIVE_V_EN BIT(30) 69 70 #define INTF_CFG2_DATABUS_WIDEN BIT(0) 71 #define INTF_CFG2_DATA_HCTL_EN BIT(4) 72 73 #define INTF_MISR_CTRL 0x180 74 #define INTF_MISR_SIGNATURE 0x184 75 76 static const struct dpu_intf_cfg *_intf_offset(enum dpu_intf intf, 77 const struct dpu_mdss_cfg *m, 78 void __iomem *addr, 79 struct dpu_hw_blk_reg_map *b) 80 { 81 int i; 82 83 for (i = 0; i < m->intf_count; i++) { 84 if ((intf == m->intf[i].id) && 85 (m->intf[i].type != INTF_NONE)) { 86 b->blk_addr = addr + m->intf[i].base; 87 b->log_mask = DPU_DBG_MASK_INTF; 88 return &m->intf[i]; 89 } 90 } 91 92 return ERR_PTR(-EINVAL); 93 } 94 95 static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, 96 const struct intf_timing_params *p, 97 const struct dpu_format *fmt) 98 { 99 struct dpu_hw_blk_reg_map *c = &ctx->hw; 100 u32 hsync_period, vsync_period; 101 u32 display_v_start, display_v_end; 102 u32 hsync_start_x, hsync_end_x; 103 u32 hsync_data_start_x, hsync_data_end_x; 104 u32 active_h_start, active_h_end; 105 u32 active_v_start, active_v_end; 106 u32 active_hctl, display_hctl, hsync_ctl; 107 u32 polarity_ctl, den_polarity, hsync_polarity, vsync_polarity; 108 u32 panel_format; 109 u32 intf_cfg, intf_cfg2 = 0; 110 u32 display_data_hctl = 0, active_data_hctl = 0; 111 u32 data_width; 112 bool dp_intf = false; 113 114 /* read interface_cfg */ 115 intf_cfg = DPU_REG_READ(c, INTF_CONFIG); 116 117 if (ctx->cap->type == INTF_DP) 118 dp_intf = true; 119 120 hsync_period = p->hsync_pulse_width + p->h_back_porch + p->width + 121 p->h_front_porch; 122 vsync_period = p->vsync_pulse_width + p->v_back_porch + p->height + 123 p->v_front_porch; 124 125 display_v_start = ((p->vsync_pulse_width + p->v_back_porch) * 126 hsync_period) + p->hsync_skew; 127 display_v_end = ((vsync_period - p->v_front_porch) * hsync_period) + 128 p->hsync_skew - 1; 129 130 hsync_start_x = p->h_back_porch + p->hsync_pulse_width; 131 hsync_end_x = hsync_period - p->h_front_porch - 1; 132 133 if (p->width != p->xres) { /* border fill added */ 134 active_h_start = hsync_start_x; 135 active_h_end = active_h_start + p->xres - 1; 136 } else { 137 active_h_start = 0; 138 active_h_end = 0; 139 } 140 141 if (p->height != p->yres) { /* border fill added */ 142 active_v_start = display_v_start; 143 active_v_end = active_v_start + (p->yres * hsync_period) - 1; 144 } else { 145 active_v_start = 0; 146 active_v_end = 0; 147 } 148 149 if (active_h_end) { 150 active_hctl = (active_h_end << 16) | active_h_start; 151 intf_cfg |= INTF_CFG_ACTIVE_H_EN; 152 } else { 153 active_hctl = 0; 154 } 155 156 if (active_v_end) 157 intf_cfg |= INTF_CFG_ACTIVE_V_EN; 158 159 hsync_ctl = (hsync_period << 16) | p->hsync_pulse_width; 160 display_hctl = (hsync_end_x << 16) | hsync_start_x; 161 162 /* 163 * DATA_HCTL_EN controls data timing which can be different from 164 * video timing. It is recommended to enable it for all cases, except 165 * if compression is enabled in 1 pixel per clock mode 166 */ 167 if (p->wide_bus_en) 168 intf_cfg2 |= INTF_CFG2_DATABUS_WIDEN | INTF_CFG2_DATA_HCTL_EN; 169 170 data_width = p->width; 171 172 hsync_data_start_x = hsync_start_x; 173 hsync_data_end_x = hsync_start_x + data_width - 1; 174 175 display_data_hctl = (hsync_data_end_x << 16) | hsync_data_start_x; 176 177 if (dp_intf) { 178 /* DP timing adjustment */ 179 display_v_start += p->hsync_pulse_width + p->h_back_porch; 180 display_v_end -= p->h_front_porch; 181 182 active_h_start = hsync_start_x; 183 active_h_end = active_h_start + p->xres - 1; 184 active_v_start = display_v_start; 185 active_v_end = active_v_start + (p->yres * hsync_period) - 1; 186 187 active_hctl = (active_h_end << 16) | active_h_start; 188 display_hctl = active_hctl; 189 190 intf_cfg |= INTF_CFG_ACTIVE_H_EN | INTF_CFG_ACTIVE_V_EN; 191 } 192 193 den_polarity = 0; 194 if (ctx->cap->type == INTF_HDMI) { 195 hsync_polarity = p->yres >= 720 ? 0 : 1; 196 vsync_polarity = p->yres >= 720 ? 0 : 1; 197 } else if (ctx->cap->type == INTF_DP) { 198 hsync_polarity = p->hsync_polarity; 199 vsync_polarity = p->vsync_polarity; 200 } else { 201 hsync_polarity = 0; 202 vsync_polarity = 0; 203 } 204 polarity_ctl = (den_polarity << 2) | /* DEN Polarity */ 205 (vsync_polarity << 1) | /* VSYNC Polarity */ 206 (hsync_polarity << 0); /* HSYNC Polarity */ 207 208 if (!DPU_FORMAT_IS_YUV(fmt)) 209 panel_format = (fmt->bits[C0_G_Y] | 210 (fmt->bits[C1_B_Cb] << 2) | 211 (fmt->bits[C2_R_Cr] << 4) | 212 (0x21 << 8)); 213 else 214 /* Interface treats all the pixel data in RGB888 format */ 215 panel_format = (COLOR_8BIT | 216 (COLOR_8BIT << 2) | 217 (COLOR_8BIT << 4) | 218 (0x21 << 8)); 219 220 DPU_REG_WRITE(c, INTF_HSYNC_CTL, hsync_ctl); 221 DPU_REG_WRITE(c, INTF_VSYNC_PERIOD_F0, vsync_period * hsync_period); 222 DPU_REG_WRITE(c, INTF_VSYNC_PULSE_WIDTH_F0, 223 p->vsync_pulse_width * hsync_period); 224 DPU_REG_WRITE(c, INTF_DISPLAY_HCTL, display_hctl); 225 DPU_REG_WRITE(c, INTF_DISPLAY_V_START_F0, display_v_start); 226 DPU_REG_WRITE(c, INTF_DISPLAY_V_END_F0, display_v_end); 227 DPU_REG_WRITE(c, INTF_ACTIVE_HCTL, active_hctl); 228 DPU_REG_WRITE(c, INTF_ACTIVE_V_START_F0, active_v_start); 229 DPU_REG_WRITE(c, INTF_ACTIVE_V_END_F0, active_v_end); 230 DPU_REG_WRITE(c, INTF_BORDER_COLOR, p->border_clr); 231 DPU_REG_WRITE(c, INTF_UNDERFLOW_COLOR, p->underflow_clr); 232 DPU_REG_WRITE(c, INTF_HSYNC_SKEW, p->hsync_skew); 233 DPU_REG_WRITE(c, INTF_POLARITY_CTL, polarity_ctl); 234 DPU_REG_WRITE(c, INTF_FRAME_LINE_COUNT_EN, 0x3); 235 DPU_REG_WRITE(c, INTF_CONFIG, intf_cfg); 236 DPU_REG_WRITE(c, INTF_PANEL_FORMAT, panel_format); 237 if (ctx->cap->features & BIT(DPU_DATA_HCTL_EN)) { 238 DPU_REG_WRITE(c, INTF_CONFIG2, intf_cfg2); 239 DPU_REG_WRITE(c, INTF_DISPLAY_DATA_HCTL, display_data_hctl); 240 DPU_REG_WRITE(c, INTF_ACTIVE_DATA_HCTL, active_data_hctl); 241 } 242 } 243 244 static void dpu_hw_intf_enable_timing_engine( 245 struct dpu_hw_intf *intf, 246 u8 enable) 247 { 248 struct dpu_hw_blk_reg_map *c = &intf->hw; 249 /* Note: Display interface select is handled in top block hw layer */ 250 DPU_REG_WRITE(c, INTF_TIMING_ENGINE_EN, enable != 0); 251 } 252 253 static void dpu_hw_intf_setup_prg_fetch( 254 struct dpu_hw_intf *intf, 255 const struct intf_prog_fetch *fetch) 256 { 257 struct dpu_hw_blk_reg_map *c = &intf->hw; 258 int fetch_enable; 259 260 /* 261 * Fetch should always be outside the active lines. If the fetching 262 * is programmed within active region, hardware behavior is unknown. 263 */ 264 265 fetch_enable = DPU_REG_READ(c, INTF_CONFIG); 266 if (fetch->enable) { 267 fetch_enable |= BIT(31); 268 DPU_REG_WRITE(c, INTF_PROG_FETCH_START, 269 fetch->fetch_start); 270 } else { 271 fetch_enable &= ~BIT(31); 272 } 273 274 DPU_REG_WRITE(c, INTF_CONFIG, fetch_enable); 275 } 276 277 static void dpu_hw_intf_bind_pingpong_blk( 278 struct dpu_hw_intf *intf, 279 bool enable, 280 const enum dpu_pingpong pp) 281 { 282 struct dpu_hw_blk_reg_map *c = &intf->hw; 283 u32 mux_cfg; 284 285 mux_cfg = DPU_REG_READ(c, INTF_MUX); 286 mux_cfg &= ~0xf; 287 288 if (enable) 289 mux_cfg |= (pp - PINGPONG_0) & 0x7; 290 else 291 mux_cfg |= 0xf; 292 293 DPU_REG_WRITE(c, INTF_MUX, mux_cfg); 294 } 295 296 static void dpu_hw_intf_get_status( 297 struct dpu_hw_intf *intf, 298 struct intf_status *s) 299 { 300 struct dpu_hw_blk_reg_map *c = &intf->hw; 301 unsigned long cap = intf->cap->features; 302 303 if (cap & BIT(DPU_INTF_STATUS_SUPPORTED)) 304 s->is_en = DPU_REG_READ(c, INTF_STATUS) & BIT(0); 305 else 306 s->is_en = DPU_REG_READ(c, INTF_TIMING_ENGINE_EN); 307 308 s->is_prog_fetch_en = !!(DPU_REG_READ(c, INTF_CONFIG) & BIT(31)); 309 if (s->is_en) { 310 s->frame_count = DPU_REG_READ(c, INTF_FRAME_COUNT); 311 s->line_count = DPU_REG_READ(c, INTF_LINE_COUNT); 312 } else { 313 s->line_count = 0; 314 s->frame_count = 0; 315 } 316 } 317 318 static u32 dpu_hw_intf_get_line_count(struct dpu_hw_intf *intf) 319 { 320 struct dpu_hw_blk_reg_map *c; 321 322 if (!intf) 323 return 0; 324 325 c = &intf->hw; 326 327 return DPU_REG_READ(c, INTF_LINE_COUNT); 328 } 329 330 static void dpu_hw_intf_setup_misr(struct dpu_hw_intf *intf, bool enable, u32 frame_count) 331 { 332 dpu_hw_setup_misr(&intf->hw, INTF_MISR_CTRL, enable, frame_count); 333 } 334 335 static int dpu_hw_intf_collect_misr(struct dpu_hw_intf *intf, u32 *misr_value) 336 { 337 return dpu_hw_collect_misr(&intf->hw, INTF_MISR_CTRL, INTF_MISR_SIGNATURE, misr_value); 338 } 339 340 static void _setup_intf_ops(struct dpu_hw_intf_ops *ops, 341 unsigned long cap) 342 { 343 ops->setup_timing_gen = dpu_hw_intf_setup_timing_engine; 344 ops->setup_prg_fetch = dpu_hw_intf_setup_prg_fetch; 345 ops->get_status = dpu_hw_intf_get_status; 346 ops->enable_timing = dpu_hw_intf_enable_timing_engine; 347 ops->get_line_count = dpu_hw_intf_get_line_count; 348 if (cap & BIT(DPU_INTF_INPUT_CTRL)) 349 ops->bind_pingpong_blk = dpu_hw_intf_bind_pingpong_blk; 350 ops->setup_misr = dpu_hw_intf_setup_misr; 351 ops->collect_misr = dpu_hw_intf_collect_misr; 352 } 353 354 struct dpu_hw_intf *dpu_hw_intf_init(enum dpu_intf idx, 355 void __iomem *addr, 356 const struct dpu_mdss_cfg *m) 357 { 358 struct dpu_hw_intf *c; 359 const struct dpu_intf_cfg *cfg; 360 361 c = kzalloc(sizeof(*c), GFP_KERNEL); 362 if (!c) 363 return ERR_PTR(-ENOMEM); 364 365 cfg = _intf_offset(idx, m, addr, &c->hw); 366 if (IS_ERR_OR_NULL(cfg)) { 367 kfree(c); 368 pr_err("failed to create dpu_hw_intf %d\n", idx); 369 return ERR_PTR(-EINVAL); 370 } 371 372 /* 373 * Assign ops 374 */ 375 c->idx = idx; 376 c->cap = cfg; 377 c->mdss = m; 378 _setup_intf_ops(&c->ops, c->cap->features); 379 380 return c; 381 } 382 383 void dpu_hw_intf_destroy(struct dpu_hw_intf *intf) 384 { 385 kfree(intf); 386 } 387 388