1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 5 */ 6 7 #include "dpu_hwio.h" 8 #include "dpu_hw_catalog.h" 9 #include "dpu_hw_intf.h" 10 #include "dpu_kms.h" 11 12 #define INTF_TIMING_ENGINE_EN 0x000 13 #define INTF_CONFIG 0x004 14 #define INTF_HSYNC_CTL 0x008 15 #define INTF_VSYNC_PERIOD_F0 0x00C 16 #define INTF_VSYNC_PERIOD_F1 0x010 17 #define INTF_VSYNC_PULSE_WIDTH_F0 0x014 18 #define INTF_VSYNC_PULSE_WIDTH_F1 0x018 19 #define INTF_DISPLAY_V_START_F0 0x01C 20 #define INTF_DISPLAY_V_START_F1 0x020 21 #define INTF_DISPLAY_V_END_F0 0x024 22 #define INTF_DISPLAY_V_END_F1 0x028 23 #define INTF_ACTIVE_V_START_F0 0x02C 24 #define INTF_ACTIVE_V_START_F1 0x030 25 #define INTF_ACTIVE_V_END_F0 0x034 26 #define INTF_ACTIVE_V_END_F1 0x038 27 #define INTF_DISPLAY_HCTL 0x03C 28 #define INTF_ACTIVE_HCTL 0x040 29 #define INTF_BORDER_COLOR 0x044 30 #define INTF_UNDERFLOW_COLOR 0x048 31 #define INTF_HSYNC_SKEW 0x04C 32 #define INTF_POLARITY_CTL 0x050 33 #define INTF_TEST_CTL 0x054 34 #define INTF_TP_COLOR0 0x058 35 #define INTF_TP_COLOR1 0x05C 36 #define INTF_CONFIG2 0x060 37 #define INTF_DISPLAY_DATA_HCTL 0x064 38 #define INTF_ACTIVE_DATA_HCTL 0x068 39 #define INTF_FRAME_LINE_COUNT_EN 0x0A8 40 #define INTF_FRAME_COUNT 0x0AC 41 #define INTF_LINE_COUNT 0x0B0 42 43 #define INTF_DEFLICKER_CONFIG 0x0F0 44 #define INTF_DEFLICKER_STRNG_COEFF 0x0F4 45 #define INTF_DEFLICKER_WEAK_COEFF 0x0F8 46 47 #define INTF_DSI_CMD_MODE_TRIGGER_EN 0x084 48 #define INTF_PANEL_FORMAT 0x090 49 #define INTF_TPG_ENABLE 0x100 50 #define INTF_TPG_MAIN_CONTROL 0x104 51 #define INTF_TPG_VIDEO_CONFIG 0x108 52 #define INTF_TPG_COMPONENT_LIMITS 0x10C 53 #define INTF_TPG_RECTANGLE 0x110 54 #define INTF_TPG_INITIAL_VALUE 0x114 55 #define INTF_TPG_BLK_WHITE_PATTERN_FRAMES 0x118 56 #define INTF_TPG_RGB_MAPPING 0x11C 57 #define INTF_PROG_FETCH_START 0x170 58 #define INTF_PROG_ROT_START 0x174 59 60 #define INTF_FRAME_LINE_COUNT_EN 0x0A8 61 #define INTF_FRAME_COUNT 0x0AC 62 #define INTF_LINE_COUNT 0x0B0 63 64 #define INTF_MUX 0x25C 65 66 #define INTF_CFG_ACTIVE_H_EN BIT(29) 67 #define INTF_CFG_ACTIVE_V_EN BIT(30) 68 69 #define INTF_CFG2_DATABUS_WIDEN BIT(0) 70 #define INTF_CFG2_DATA_HCTL_EN BIT(4) 71 72 #define INTF_MISR_CTRL 0x180 73 #define INTF_MISR_SIGNATURE 0x184 74 75 static const struct dpu_intf_cfg *_intf_offset(enum dpu_intf intf, 76 const struct dpu_mdss_cfg *m, 77 void __iomem *addr, 78 struct dpu_hw_blk_reg_map *b) 79 { 80 int i; 81 82 for (i = 0; i < m->intf_count; i++) { 83 if ((intf == m->intf[i].id) && 84 (m->intf[i].type != INTF_NONE)) { 85 b->blk_addr = addr + m->intf[i].base; 86 b->log_mask = DPU_DBG_MASK_INTF; 87 return &m->intf[i]; 88 } 89 } 90 91 return ERR_PTR(-EINVAL); 92 } 93 94 static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, 95 const struct intf_timing_params *p, 96 const struct dpu_format *fmt) 97 { 98 struct dpu_hw_blk_reg_map *c = &ctx->hw; 99 u32 hsync_period, vsync_period; 100 u32 display_v_start, display_v_end; 101 u32 hsync_start_x, hsync_end_x; 102 u32 hsync_data_start_x, hsync_data_end_x; 103 u32 active_h_start, active_h_end; 104 u32 active_v_start, active_v_end; 105 u32 active_hctl, display_hctl, hsync_ctl; 106 u32 polarity_ctl, den_polarity, hsync_polarity, vsync_polarity; 107 u32 panel_format; 108 u32 intf_cfg, intf_cfg2 = 0; 109 u32 display_data_hctl = 0, active_data_hctl = 0; 110 u32 data_width; 111 bool dp_intf = false; 112 113 /* read interface_cfg */ 114 intf_cfg = DPU_REG_READ(c, INTF_CONFIG); 115 116 if (ctx->cap->type == INTF_DP) 117 dp_intf = true; 118 119 hsync_period = p->hsync_pulse_width + p->h_back_porch + p->width + 120 p->h_front_porch; 121 vsync_period = p->vsync_pulse_width + p->v_back_porch + p->height + 122 p->v_front_porch; 123 124 display_v_start = ((p->vsync_pulse_width + p->v_back_porch) * 125 hsync_period) + p->hsync_skew; 126 display_v_end = ((vsync_period - p->v_front_porch) * hsync_period) + 127 p->hsync_skew - 1; 128 129 hsync_start_x = p->h_back_porch + p->hsync_pulse_width; 130 hsync_end_x = hsync_period - p->h_front_porch - 1; 131 132 if (p->width != p->xres) { /* border fill added */ 133 active_h_start = hsync_start_x; 134 active_h_end = active_h_start + p->xres - 1; 135 } else { 136 active_h_start = 0; 137 active_h_end = 0; 138 } 139 140 if (p->height != p->yres) { /* border fill added */ 141 active_v_start = display_v_start; 142 active_v_end = active_v_start + (p->yres * hsync_period) - 1; 143 } else { 144 active_v_start = 0; 145 active_v_end = 0; 146 } 147 148 if (active_h_end) { 149 active_hctl = (active_h_end << 16) | active_h_start; 150 intf_cfg |= INTF_CFG_ACTIVE_H_EN; 151 } else { 152 active_hctl = 0; 153 } 154 155 if (active_v_end) 156 intf_cfg |= INTF_CFG_ACTIVE_V_EN; 157 158 hsync_ctl = (hsync_period << 16) | p->hsync_pulse_width; 159 display_hctl = (hsync_end_x << 16) | hsync_start_x; 160 161 /* 162 * DATA_HCTL_EN controls data timing which can be different from 163 * video timing. It is recommended to enable it for all cases, except 164 * if compression is enabled in 1 pixel per clock mode 165 */ 166 if (p->wide_bus_en) 167 intf_cfg2 |= INTF_CFG2_DATABUS_WIDEN | INTF_CFG2_DATA_HCTL_EN; 168 169 data_width = p->width; 170 171 hsync_data_start_x = hsync_start_x; 172 hsync_data_end_x = hsync_start_x + data_width - 1; 173 174 display_data_hctl = (hsync_data_end_x << 16) | hsync_data_start_x; 175 176 if (dp_intf) { 177 /* DP timing adjustment */ 178 display_v_start += p->hsync_pulse_width + p->h_back_porch; 179 display_v_end -= p->h_front_porch; 180 181 active_h_start = hsync_start_x; 182 active_h_end = active_h_start + p->xres - 1; 183 active_v_start = display_v_start; 184 active_v_end = active_v_start + (p->yres * hsync_period) - 1; 185 186 active_hctl = (active_h_end << 16) | active_h_start; 187 display_hctl = active_hctl; 188 189 intf_cfg |= INTF_CFG_ACTIVE_H_EN | INTF_CFG_ACTIVE_V_EN; 190 } 191 192 den_polarity = 0; 193 if (ctx->cap->type == INTF_HDMI) { 194 hsync_polarity = p->yres >= 720 ? 0 : 1; 195 vsync_polarity = p->yres >= 720 ? 0 : 1; 196 } else if (ctx->cap->type == INTF_DP) { 197 hsync_polarity = p->hsync_polarity; 198 vsync_polarity = p->vsync_polarity; 199 } else { 200 hsync_polarity = 0; 201 vsync_polarity = 0; 202 } 203 polarity_ctl = (den_polarity << 2) | /* DEN Polarity */ 204 (vsync_polarity << 1) | /* VSYNC Polarity */ 205 (hsync_polarity << 0); /* HSYNC Polarity */ 206 207 if (!DPU_FORMAT_IS_YUV(fmt)) 208 panel_format = (fmt->bits[C0_G_Y] | 209 (fmt->bits[C1_B_Cb] << 2) | 210 (fmt->bits[C2_R_Cr] << 4) | 211 (0x21 << 8)); 212 else 213 /* Interface treats all the pixel data in RGB888 format */ 214 panel_format = (COLOR_8BIT | 215 (COLOR_8BIT << 2) | 216 (COLOR_8BIT << 4) | 217 (0x21 << 8)); 218 219 DPU_REG_WRITE(c, INTF_HSYNC_CTL, hsync_ctl); 220 DPU_REG_WRITE(c, INTF_VSYNC_PERIOD_F0, vsync_period * hsync_period); 221 DPU_REG_WRITE(c, INTF_VSYNC_PULSE_WIDTH_F0, 222 p->vsync_pulse_width * hsync_period); 223 DPU_REG_WRITE(c, INTF_DISPLAY_HCTL, display_hctl); 224 DPU_REG_WRITE(c, INTF_DISPLAY_V_START_F0, display_v_start); 225 DPU_REG_WRITE(c, INTF_DISPLAY_V_END_F0, display_v_end); 226 DPU_REG_WRITE(c, INTF_ACTIVE_HCTL, active_hctl); 227 DPU_REG_WRITE(c, INTF_ACTIVE_V_START_F0, active_v_start); 228 DPU_REG_WRITE(c, INTF_ACTIVE_V_END_F0, active_v_end); 229 DPU_REG_WRITE(c, INTF_BORDER_COLOR, p->border_clr); 230 DPU_REG_WRITE(c, INTF_UNDERFLOW_COLOR, p->underflow_clr); 231 DPU_REG_WRITE(c, INTF_HSYNC_SKEW, p->hsync_skew); 232 DPU_REG_WRITE(c, INTF_POLARITY_CTL, polarity_ctl); 233 DPU_REG_WRITE(c, INTF_FRAME_LINE_COUNT_EN, 0x3); 234 DPU_REG_WRITE(c, INTF_CONFIG, intf_cfg); 235 DPU_REG_WRITE(c, INTF_PANEL_FORMAT, panel_format); 236 if (ctx->cap->features & BIT(DPU_DATA_HCTL_EN)) { 237 DPU_REG_WRITE(c, INTF_CONFIG2, intf_cfg2); 238 DPU_REG_WRITE(c, INTF_DISPLAY_DATA_HCTL, display_data_hctl); 239 DPU_REG_WRITE(c, INTF_ACTIVE_DATA_HCTL, active_data_hctl); 240 } 241 } 242 243 static void dpu_hw_intf_enable_timing_engine( 244 struct dpu_hw_intf *intf, 245 u8 enable) 246 { 247 struct dpu_hw_blk_reg_map *c = &intf->hw; 248 /* Note: Display interface select is handled in top block hw layer */ 249 DPU_REG_WRITE(c, INTF_TIMING_ENGINE_EN, enable != 0); 250 } 251 252 static void dpu_hw_intf_setup_prg_fetch( 253 struct dpu_hw_intf *intf, 254 const struct intf_prog_fetch *fetch) 255 { 256 struct dpu_hw_blk_reg_map *c = &intf->hw; 257 int fetch_enable; 258 259 /* 260 * Fetch should always be outside the active lines. If the fetching 261 * is programmed within active region, hardware behavior is unknown. 262 */ 263 264 fetch_enable = DPU_REG_READ(c, INTF_CONFIG); 265 if (fetch->enable) { 266 fetch_enable |= BIT(31); 267 DPU_REG_WRITE(c, INTF_PROG_FETCH_START, 268 fetch->fetch_start); 269 } else { 270 fetch_enable &= ~BIT(31); 271 } 272 273 DPU_REG_WRITE(c, INTF_CONFIG, fetch_enable); 274 } 275 276 static void dpu_hw_intf_bind_pingpong_blk( 277 struct dpu_hw_intf *intf, 278 bool enable, 279 const enum dpu_pingpong pp) 280 { 281 struct dpu_hw_blk_reg_map *c = &intf->hw; 282 u32 mux_cfg; 283 284 mux_cfg = DPU_REG_READ(c, INTF_MUX); 285 mux_cfg &= ~0xf; 286 287 if (enable) 288 mux_cfg |= (pp - PINGPONG_0) & 0x7; 289 else 290 mux_cfg |= 0xf; 291 292 DPU_REG_WRITE(c, INTF_MUX, mux_cfg); 293 } 294 295 static void dpu_hw_intf_get_status( 296 struct dpu_hw_intf *intf, 297 struct intf_status *s) 298 { 299 struct dpu_hw_blk_reg_map *c = &intf->hw; 300 301 s->is_en = DPU_REG_READ(c, INTF_TIMING_ENGINE_EN); 302 s->is_prog_fetch_en = !!(DPU_REG_READ(c, INTF_CONFIG) & BIT(31)); 303 if (s->is_en) { 304 s->frame_count = DPU_REG_READ(c, INTF_FRAME_COUNT); 305 s->line_count = DPU_REG_READ(c, INTF_LINE_COUNT); 306 } else { 307 s->line_count = 0; 308 s->frame_count = 0; 309 } 310 } 311 312 static u32 dpu_hw_intf_get_line_count(struct dpu_hw_intf *intf) 313 { 314 struct dpu_hw_blk_reg_map *c; 315 316 if (!intf) 317 return 0; 318 319 c = &intf->hw; 320 321 return DPU_REG_READ(c, INTF_LINE_COUNT); 322 } 323 324 static void dpu_hw_intf_setup_misr(struct dpu_hw_intf *intf, bool enable, u32 frame_count) 325 { 326 dpu_hw_setup_misr(&intf->hw, INTF_MISR_CTRL, enable, frame_count); 327 } 328 329 static int dpu_hw_intf_collect_misr(struct dpu_hw_intf *intf, u32 *misr_value) 330 { 331 return dpu_hw_collect_misr(&intf->hw, INTF_MISR_CTRL, INTF_MISR_SIGNATURE, misr_value); 332 } 333 334 static void _setup_intf_ops(struct dpu_hw_intf_ops *ops, 335 unsigned long cap) 336 { 337 ops->setup_timing_gen = dpu_hw_intf_setup_timing_engine; 338 ops->setup_prg_fetch = dpu_hw_intf_setup_prg_fetch; 339 ops->get_status = dpu_hw_intf_get_status; 340 ops->enable_timing = dpu_hw_intf_enable_timing_engine; 341 ops->get_line_count = dpu_hw_intf_get_line_count; 342 if (cap & BIT(DPU_INTF_INPUT_CTRL)) 343 ops->bind_pingpong_blk = dpu_hw_intf_bind_pingpong_blk; 344 ops->setup_misr = dpu_hw_intf_setup_misr; 345 ops->collect_misr = dpu_hw_intf_collect_misr; 346 } 347 348 struct dpu_hw_intf *dpu_hw_intf_init(enum dpu_intf idx, 349 void __iomem *addr, 350 const struct dpu_mdss_cfg *m) 351 { 352 struct dpu_hw_intf *c; 353 const struct dpu_intf_cfg *cfg; 354 355 c = kzalloc(sizeof(*c), GFP_KERNEL); 356 if (!c) 357 return ERR_PTR(-ENOMEM); 358 359 cfg = _intf_offset(idx, m, addr, &c->hw); 360 if (IS_ERR_OR_NULL(cfg)) { 361 kfree(c); 362 pr_err("failed to create dpu_hw_intf %d\n", idx); 363 return ERR_PTR(-EINVAL); 364 } 365 366 /* 367 * Assign ops 368 */ 369 c->idx = idx; 370 c->cap = cfg; 371 c->mdss = m; 372 _setup_intf_ops(&c->ops, c->cap->features); 373 374 return c; 375 } 376 377 void dpu_hw_intf_destroy(struct dpu_hw_intf *intf) 378 { 379 kfree(intf); 380 } 381 382