1 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 2 * 3 * This program is free software; you can redistribute it and/or modify 4 * it under the terms of the GNU General Public License version 2 and 5 * only version 2 as published by the Free Software Foundation. 6 * 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 */ 12 13 #include "dpu_hwio.h" 14 #include "dpu_hw_catalog.h" 15 #include "dpu_hw_intf.h" 16 #include "dpu_dbg.h" 17 #include "dpu_kms.h" 18 19 #define INTF_TIMING_ENGINE_EN 0x000 20 #define INTF_CONFIG 0x004 21 #define INTF_HSYNC_CTL 0x008 22 #define INTF_VSYNC_PERIOD_F0 0x00C 23 #define INTF_VSYNC_PERIOD_F1 0x010 24 #define INTF_VSYNC_PULSE_WIDTH_F0 0x014 25 #define INTF_VSYNC_PULSE_WIDTH_F1 0x018 26 #define INTF_DISPLAY_V_START_F0 0x01C 27 #define INTF_DISPLAY_V_START_F1 0x020 28 #define INTF_DISPLAY_V_END_F0 0x024 29 #define INTF_DISPLAY_V_END_F1 0x028 30 #define INTF_ACTIVE_V_START_F0 0x02C 31 #define INTF_ACTIVE_V_START_F1 0x030 32 #define INTF_ACTIVE_V_END_F0 0x034 33 #define INTF_ACTIVE_V_END_F1 0x038 34 #define INTF_DISPLAY_HCTL 0x03C 35 #define INTF_ACTIVE_HCTL 0x040 36 #define INTF_BORDER_COLOR 0x044 37 #define INTF_UNDERFLOW_COLOR 0x048 38 #define INTF_HSYNC_SKEW 0x04C 39 #define INTF_POLARITY_CTL 0x050 40 #define INTF_TEST_CTL 0x054 41 #define INTF_TP_COLOR0 0x058 42 #define INTF_TP_COLOR1 0x05C 43 #define INTF_FRAME_LINE_COUNT_EN 0x0A8 44 #define INTF_FRAME_COUNT 0x0AC 45 #define INTF_LINE_COUNT 0x0B0 46 47 #define INTF_DEFLICKER_CONFIG 0x0F0 48 #define INTF_DEFLICKER_STRNG_COEFF 0x0F4 49 #define INTF_DEFLICKER_WEAK_COEFF 0x0F8 50 51 #define INTF_DSI_CMD_MODE_TRIGGER_EN 0x084 52 #define INTF_PANEL_FORMAT 0x090 53 #define INTF_TPG_ENABLE 0x100 54 #define INTF_TPG_MAIN_CONTROL 0x104 55 #define INTF_TPG_VIDEO_CONFIG 0x108 56 #define INTF_TPG_COMPONENT_LIMITS 0x10C 57 #define INTF_TPG_RECTANGLE 0x110 58 #define INTF_TPG_INITIAL_VALUE 0x114 59 #define INTF_TPG_BLK_WHITE_PATTERN_FRAMES 0x118 60 #define INTF_TPG_RGB_MAPPING 0x11C 61 #define INTF_PROG_FETCH_START 0x170 62 #define INTF_PROG_ROT_START 0x174 63 64 #define INTF_FRAME_LINE_COUNT_EN 0x0A8 65 #define INTF_FRAME_COUNT 0x0AC 66 #define INTF_LINE_COUNT 0x0B0 67 68 static struct dpu_intf_cfg *_intf_offset(enum dpu_intf intf, 69 struct dpu_mdss_cfg *m, 70 void __iomem *addr, 71 struct dpu_hw_blk_reg_map *b) 72 { 73 int i; 74 75 for (i = 0; i < m->intf_count; i++) { 76 if ((intf == m->intf[i].id) && 77 (m->intf[i].type != INTF_NONE)) { 78 b->base_off = addr; 79 b->blk_off = m->intf[i].base; 80 b->length = m->intf[i].len; 81 b->hwversion = m->hwversion; 82 b->log_mask = DPU_DBG_MASK_INTF; 83 return &m->intf[i]; 84 } 85 } 86 87 return ERR_PTR(-EINVAL); 88 } 89 90 static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, 91 const struct intf_timing_params *p, 92 const struct dpu_format *fmt) 93 { 94 struct dpu_hw_blk_reg_map *c = &ctx->hw; 95 u32 hsync_period, vsync_period; 96 u32 display_v_start, display_v_end; 97 u32 hsync_start_x, hsync_end_x; 98 u32 active_h_start, active_h_end; 99 u32 active_v_start, active_v_end; 100 u32 active_hctl, display_hctl, hsync_ctl; 101 u32 polarity_ctl, den_polarity, hsync_polarity, vsync_polarity; 102 u32 panel_format; 103 u32 intf_cfg; 104 105 /* read interface_cfg */ 106 intf_cfg = DPU_REG_READ(c, INTF_CONFIG); 107 hsync_period = p->hsync_pulse_width + p->h_back_porch + p->width + 108 p->h_front_porch; 109 vsync_period = p->vsync_pulse_width + p->v_back_porch + p->height + 110 p->v_front_porch; 111 112 display_v_start = ((p->vsync_pulse_width + p->v_back_porch) * 113 hsync_period) + p->hsync_skew; 114 display_v_end = ((vsync_period - p->v_front_porch) * hsync_period) + 115 p->hsync_skew - 1; 116 117 if (ctx->cap->type == INTF_EDP || ctx->cap->type == INTF_DP) { 118 display_v_start += p->hsync_pulse_width + p->h_back_porch; 119 display_v_end -= p->h_front_porch; 120 } 121 122 hsync_start_x = p->h_back_porch + p->hsync_pulse_width; 123 hsync_end_x = hsync_period - p->h_front_porch - 1; 124 125 if (p->width != p->xres) { 126 active_h_start = hsync_start_x; 127 active_h_end = active_h_start + p->xres - 1; 128 } else { 129 active_h_start = 0; 130 active_h_end = 0; 131 } 132 133 if (p->height != p->yres) { 134 active_v_start = display_v_start; 135 active_v_end = active_v_start + (p->yres * hsync_period) - 1; 136 } else { 137 active_v_start = 0; 138 active_v_end = 0; 139 } 140 141 if (active_h_end) { 142 active_hctl = (active_h_end << 16) | active_h_start; 143 intf_cfg |= BIT(29); /* ACTIVE_H_ENABLE */ 144 } else { 145 active_hctl = 0; 146 } 147 148 if (active_v_end) 149 intf_cfg |= BIT(30); /* ACTIVE_V_ENABLE */ 150 151 hsync_ctl = (hsync_period << 16) | p->hsync_pulse_width; 152 display_hctl = (hsync_end_x << 16) | hsync_start_x; 153 154 den_polarity = 0; 155 if (ctx->cap->type == INTF_HDMI) { 156 hsync_polarity = p->yres >= 720 ? 0 : 1; 157 vsync_polarity = p->yres >= 720 ? 0 : 1; 158 } else { 159 hsync_polarity = 0; 160 vsync_polarity = 0; 161 } 162 polarity_ctl = (den_polarity << 2) | /* DEN Polarity */ 163 (vsync_polarity << 1) | /* VSYNC Polarity */ 164 (hsync_polarity << 0); /* HSYNC Polarity */ 165 166 if (!DPU_FORMAT_IS_YUV(fmt)) 167 panel_format = (fmt->bits[C0_G_Y] | 168 (fmt->bits[C1_B_Cb] << 2) | 169 (fmt->bits[C2_R_Cr] << 4) | 170 (0x21 << 8)); 171 else 172 /* Interface treats all the pixel data in RGB888 format */ 173 panel_format = (COLOR_8BIT | 174 (COLOR_8BIT << 2) | 175 (COLOR_8BIT << 4) | 176 (0x21 << 8)); 177 178 DPU_REG_WRITE(c, INTF_HSYNC_CTL, hsync_ctl); 179 DPU_REG_WRITE(c, INTF_VSYNC_PERIOD_F0, vsync_period * hsync_period); 180 DPU_REG_WRITE(c, INTF_VSYNC_PULSE_WIDTH_F0, 181 p->vsync_pulse_width * hsync_period); 182 DPU_REG_WRITE(c, INTF_DISPLAY_HCTL, display_hctl); 183 DPU_REG_WRITE(c, INTF_DISPLAY_V_START_F0, display_v_start); 184 DPU_REG_WRITE(c, INTF_DISPLAY_V_END_F0, display_v_end); 185 DPU_REG_WRITE(c, INTF_ACTIVE_HCTL, active_hctl); 186 DPU_REG_WRITE(c, INTF_ACTIVE_V_START_F0, active_v_start); 187 DPU_REG_WRITE(c, INTF_ACTIVE_V_END_F0, active_v_end); 188 DPU_REG_WRITE(c, INTF_BORDER_COLOR, p->border_clr); 189 DPU_REG_WRITE(c, INTF_UNDERFLOW_COLOR, p->underflow_clr); 190 DPU_REG_WRITE(c, INTF_HSYNC_SKEW, p->hsync_skew); 191 DPU_REG_WRITE(c, INTF_POLARITY_CTL, polarity_ctl); 192 DPU_REG_WRITE(c, INTF_FRAME_LINE_COUNT_EN, 0x3); 193 DPU_REG_WRITE(c, INTF_CONFIG, intf_cfg); 194 DPU_REG_WRITE(c, INTF_PANEL_FORMAT, panel_format); 195 } 196 197 static void dpu_hw_intf_enable_timing_engine( 198 struct dpu_hw_intf *intf, 199 u8 enable) 200 { 201 struct dpu_hw_blk_reg_map *c = &intf->hw; 202 /* Note: Display interface select is handled in top block hw layer */ 203 DPU_REG_WRITE(c, INTF_TIMING_ENGINE_EN, enable != 0); 204 } 205 206 static void dpu_hw_intf_setup_prg_fetch( 207 struct dpu_hw_intf *intf, 208 const struct intf_prog_fetch *fetch) 209 { 210 struct dpu_hw_blk_reg_map *c = &intf->hw; 211 int fetch_enable; 212 213 /* 214 * Fetch should always be outside the active lines. If the fetching 215 * is programmed within active region, hardware behavior is unknown. 216 */ 217 218 fetch_enable = DPU_REG_READ(c, INTF_CONFIG); 219 if (fetch->enable) { 220 fetch_enable |= BIT(31); 221 DPU_REG_WRITE(c, INTF_PROG_FETCH_START, 222 fetch->fetch_start); 223 } else { 224 fetch_enable &= ~BIT(31); 225 } 226 227 DPU_REG_WRITE(c, INTF_CONFIG, fetch_enable); 228 } 229 230 static void dpu_hw_intf_get_status( 231 struct dpu_hw_intf *intf, 232 struct intf_status *s) 233 { 234 struct dpu_hw_blk_reg_map *c = &intf->hw; 235 236 s->is_en = DPU_REG_READ(c, INTF_TIMING_ENGINE_EN); 237 if (s->is_en) { 238 s->frame_count = DPU_REG_READ(c, INTF_FRAME_COUNT); 239 s->line_count = DPU_REG_READ(c, INTF_LINE_COUNT); 240 } else { 241 s->line_count = 0; 242 s->frame_count = 0; 243 } 244 } 245 246 static u32 dpu_hw_intf_get_line_count(struct dpu_hw_intf *intf) 247 { 248 struct dpu_hw_blk_reg_map *c; 249 250 if (!intf) 251 return 0; 252 253 c = &intf->hw; 254 255 return DPU_REG_READ(c, INTF_LINE_COUNT); 256 } 257 258 static void _setup_intf_ops(struct dpu_hw_intf_ops *ops, 259 unsigned long cap) 260 { 261 ops->setup_timing_gen = dpu_hw_intf_setup_timing_engine; 262 ops->setup_prg_fetch = dpu_hw_intf_setup_prg_fetch; 263 ops->get_status = dpu_hw_intf_get_status; 264 ops->enable_timing = dpu_hw_intf_enable_timing_engine; 265 ops->get_line_count = dpu_hw_intf_get_line_count; 266 } 267 268 static struct dpu_hw_blk_ops dpu_hw_ops = { 269 .start = NULL, 270 .stop = NULL, 271 }; 272 273 struct dpu_hw_intf *dpu_hw_intf_init(enum dpu_intf idx, 274 void __iomem *addr, 275 struct dpu_mdss_cfg *m) 276 { 277 struct dpu_hw_intf *c; 278 struct dpu_intf_cfg *cfg; 279 int rc; 280 281 c = kzalloc(sizeof(*c), GFP_KERNEL); 282 if (!c) 283 return ERR_PTR(-ENOMEM); 284 285 cfg = _intf_offset(idx, m, addr, &c->hw); 286 if (IS_ERR_OR_NULL(cfg)) { 287 kfree(c); 288 pr_err("failed to create dpu_hw_intf %d\n", idx); 289 return ERR_PTR(-EINVAL); 290 } 291 292 /* 293 * Assign ops 294 */ 295 c->idx = idx; 296 c->cap = cfg; 297 c->mdss = m; 298 _setup_intf_ops(&c->ops, c->cap->features); 299 300 rc = dpu_hw_blk_init(&c->base, DPU_HW_BLK_INTF, idx, &dpu_hw_ops); 301 if (rc) { 302 DPU_ERROR("failed to init hw blk %d\n", rc); 303 goto blk_init_error; 304 } 305 306 return c; 307 308 blk_init_error: 309 kzfree(c); 310 311 return ERR_PTR(rc); 312 } 313 314 void dpu_hw_intf_destroy(struct dpu_hw_intf *intf) 315 { 316 if (intf) 317 dpu_hw_blk_destroy(&intf->base); 318 kfree(intf); 319 } 320 321