1 /* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. 2 * 3 * This program is free software; you can redistribute it and/or modify 4 * it under the terms of the GNU General Public License version 2 and 5 * only version 2 as published by the Free Software Foundation. 6 * 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 */ 12 13 #ifndef _DPU_HW_INTERRUPTS_H 14 #define _DPU_HW_INTERRUPTS_H 15 16 #include <linux/types.h> 17 18 #include "dpu_hwio.h" 19 #include "dpu_hw_catalog.h" 20 #include "dpu_hw_util.h" 21 #include "dpu_hw_mdss.h" 22 23 /** 24 * dpu_intr_type - HW Interrupt Type 25 * @DPU_IRQ_TYPE_WB_ROT_COMP: WB rotator done 26 * @DPU_IRQ_TYPE_WB_WFD_COMP: WB WFD done 27 * @DPU_IRQ_TYPE_PING_PONG_COMP: PingPong done 28 * @DPU_IRQ_TYPE_PING_PONG_RD_PTR: PingPong read pointer 29 * @DPU_IRQ_TYPE_PING_PONG_WR_PTR: PingPong write pointer 30 * @DPU_IRQ_TYPE_PING_PONG_AUTO_REF: PingPong auto refresh 31 * @DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK: PingPong Tear check 32 * @DPU_IRQ_TYPE_PING_PONG_TE_CHECK: PingPong TE detection 33 * @DPU_IRQ_TYPE_INTF_UNDER_RUN: INTF underrun 34 * @DPU_IRQ_TYPE_INTF_VSYNC: INTF VSYNC 35 * @DPU_IRQ_TYPE_CWB_OVERFLOW: Concurrent WB overflow 36 * @DPU_IRQ_TYPE_HIST_VIG_DONE: VIG Histogram done 37 * @DPU_IRQ_TYPE_HIST_VIG_RSTSEQ: VIG Histogram reset 38 * @DPU_IRQ_TYPE_HIST_DSPP_DONE: DSPP Histogram done 39 * @DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ: DSPP Histogram reset 40 * @DPU_IRQ_TYPE_WD_TIMER: Watchdog timer 41 * @DPU_IRQ_TYPE_SFI_VIDEO_IN: Video static frame INTR into static 42 * @DPU_IRQ_TYPE_SFI_VIDEO_OUT: Video static frame INTR out-of static 43 * @DPU_IRQ_TYPE_SFI_CMD_0_IN: DSI CMD0 static frame INTR into static 44 * @DPU_IRQ_TYPE_SFI_CMD_0_OUT: DSI CMD0 static frame INTR out-of static 45 * @DPU_IRQ_TYPE_SFI_CMD_1_IN: DSI CMD1 static frame INTR into static 46 * @DPU_IRQ_TYPE_SFI_CMD_1_OUT: DSI CMD1 static frame INTR out-of static 47 * @DPU_IRQ_TYPE_SFI_CMD_2_IN: DSI CMD2 static frame INTR into static 48 * @DPU_IRQ_TYPE_SFI_CMD_2_OUT: DSI CMD2 static frame INTR out-of static 49 * @DPU_IRQ_TYPE_PROG_LINE: Programmable Line interrupt 50 * @DPU_IRQ_TYPE_AD4_BL_DONE: AD4 backlight 51 * @DPU_IRQ_TYPE_CTL_START: Control start 52 * @DPU_IRQ_TYPE_RESERVED: Reserved for expansion 53 */ 54 enum dpu_intr_type { 55 DPU_IRQ_TYPE_WB_ROT_COMP, 56 DPU_IRQ_TYPE_WB_WFD_COMP, 57 DPU_IRQ_TYPE_PING_PONG_COMP, 58 DPU_IRQ_TYPE_PING_PONG_RD_PTR, 59 DPU_IRQ_TYPE_PING_PONG_WR_PTR, 60 DPU_IRQ_TYPE_PING_PONG_AUTO_REF, 61 DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK, 62 DPU_IRQ_TYPE_PING_PONG_TE_CHECK, 63 DPU_IRQ_TYPE_INTF_UNDER_RUN, 64 DPU_IRQ_TYPE_INTF_VSYNC, 65 DPU_IRQ_TYPE_CWB_OVERFLOW, 66 DPU_IRQ_TYPE_HIST_VIG_DONE, 67 DPU_IRQ_TYPE_HIST_VIG_RSTSEQ, 68 DPU_IRQ_TYPE_HIST_DSPP_DONE, 69 DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ, 70 DPU_IRQ_TYPE_WD_TIMER, 71 DPU_IRQ_TYPE_SFI_VIDEO_IN, 72 DPU_IRQ_TYPE_SFI_VIDEO_OUT, 73 DPU_IRQ_TYPE_SFI_CMD_0_IN, 74 DPU_IRQ_TYPE_SFI_CMD_0_OUT, 75 DPU_IRQ_TYPE_SFI_CMD_1_IN, 76 DPU_IRQ_TYPE_SFI_CMD_1_OUT, 77 DPU_IRQ_TYPE_SFI_CMD_2_IN, 78 DPU_IRQ_TYPE_SFI_CMD_2_OUT, 79 DPU_IRQ_TYPE_PROG_LINE, 80 DPU_IRQ_TYPE_AD4_BL_DONE, 81 DPU_IRQ_TYPE_CTL_START, 82 DPU_IRQ_TYPE_RESERVED, 83 }; 84 85 struct dpu_hw_intr; 86 87 /** 88 * Interrupt operations. 89 */ 90 struct dpu_hw_intr_ops { 91 /** 92 * irq_idx_lookup - Lookup IRQ index on the HW interrupt type 93 * Used for all irq related ops 94 * @intr_type: Interrupt type defined in dpu_intr_type 95 * @instance_idx: HW interrupt block instance 96 * @return: irq_idx or -EINVAL for lookup fail 97 */ 98 int (*irq_idx_lookup)( 99 enum dpu_intr_type intr_type, 100 u32 instance_idx); 101 102 /** 103 * enable_irq - Enable IRQ based on lookup IRQ index 104 * @intr: HW interrupt handle 105 * @irq_idx: Lookup irq index return from irq_idx_lookup 106 * @return: 0 for success, otherwise failure 107 */ 108 int (*enable_irq)( 109 struct dpu_hw_intr *intr, 110 int irq_idx); 111 112 /** 113 * disable_irq - Disable IRQ based on lookup IRQ index 114 * @intr: HW interrupt handle 115 * @irq_idx: Lookup irq index return from irq_idx_lookup 116 * @return: 0 for success, otherwise failure 117 */ 118 int (*disable_irq)( 119 struct dpu_hw_intr *intr, 120 int irq_idx); 121 122 /** 123 * clear_all_irqs - Clears all the interrupts (i.e. acknowledges 124 * any asserted IRQs). Useful during reset. 125 * @intr: HW interrupt handle 126 * @return: 0 for success, otherwise failure 127 */ 128 int (*clear_all_irqs)( 129 struct dpu_hw_intr *intr); 130 131 /** 132 * disable_all_irqs - Disables all the interrupts. Useful during reset. 133 * @intr: HW interrupt handle 134 * @return: 0 for success, otherwise failure 135 */ 136 int (*disable_all_irqs)( 137 struct dpu_hw_intr *intr); 138 139 /** 140 * dispatch_irqs - IRQ dispatcher will call the given callback 141 * function when a matching interrupt status bit is 142 * found in the irq mapping table. 143 * @intr: HW interrupt handle 144 * @cbfunc: Callback function pointer 145 * @arg: Argument to pass back during callback 146 */ 147 void (*dispatch_irqs)( 148 struct dpu_hw_intr *intr, 149 void (*cbfunc)(void *arg, int irq_idx), 150 void *arg); 151 152 /** 153 * get_interrupt_statuses - Gets and store value from all interrupt 154 * status registers that are currently fired. 155 * @intr: HW interrupt handle 156 */ 157 void (*get_interrupt_statuses)( 158 struct dpu_hw_intr *intr); 159 160 /** 161 * clear_intr_status_nolock() - clears the HW interrupts without lock 162 * @intr: HW interrupt handle 163 * @irq_idx: Lookup irq index return from irq_idx_lookup 164 */ 165 void (*clear_intr_status_nolock)( 166 struct dpu_hw_intr *intr, 167 int irq_idx); 168 169 /** 170 * get_interrupt_status - Gets HW interrupt status, and clear if set, 171 * based on given lookup IRQ index. 172 * @intr: HW interrupt handle 173 * @irq_idx: Lookup irq index return from irq_idx_lookup 174 * @clear: True to clear irq after read 175 */ 176 u32 (*get_interrupt_status)( 177 struct dpu_hw_intr *intr, 178 int irq_idx, 179 bool clear); 180 }; 181 182 /** 183 * struct dpu_hw_intr: hw interrupts handling data structure 184 * @hw: virtual address mapping 185 * @ops: function pointer mapping for IRQ handling 186 * @cache_irq_mask: array of IRQ enable masks reg storage created during init 187 * @save_irq_status: array of IRQ status reg storage created during init 188 * @irq_idx_tbl_size: total number of irq_idx mapped in the hw_interrupts 189 * @irq_lock: spinlock for accessing IRQ resources 190 */ 191 struct dpu_hw_intr { 192 struct dpu_hw_blk_reg_map hw; 193 struct dpu_hw_intr_ops ops; 194 u32 *cache_irq_mask; 195 u32 *save_irq_status; 196 u32 irq_idx_tbl_size; 197 spinlock_t irq_lock; 198 }; 199 200 /** 201 * dpu_hw_intr_init(): Initializes the interrupts hw object 202 * @addr: mapped register io address of MDP 203 * @m : pointer to mdss catalog data 204 */ 205 struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr, 206 struct dpu_mdss_cfg *m); 207 208 /** 209 * dpu_hw_intr_destroy(): Cleanup interrutps hw object 210 * @intr: pointer to interrupts hw object 211 */ 212 void dpu_hw_intr_destroy(struct dpu_hw_intr *intr); 213 #endif 214