197fb5e8dSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */
225fdd593SJeykumar Sankaran /* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
325fdd593SJeykumar Sankaran  */
425fdd593SJeykumar Sankaran 
525fdd593SJeykumar Sankaran #ifndef _DPU_HW_INTERRUPTS_H
625fdd593SJeykumar Sankaran #define _DPU_HW_INTERRUPTS_H
725fdd593SJeykumar Sankaran 
825fdd593SJeykumar Sankaran #include <linux/types.h>
925fdd593SJeykumar Sankaran 
1025fdd593SJeykumar Sankaran #include "dpu_hwio.h"
1125fdd593SJeykumar Sankaran #include "dpu_hw_catalog.h"
1225fdd593SJeykumar Sankaran #include "dpu_hw_util.h"
1325fdd593SJeykumar Sankaran #include "dpu_hw_mdss.h"
1425fdd593SJeykumar Sankaran 
15597762d5SDmitry Baryshkov /* When making changes be sure to sync with dpu_intr_set */
16597762d5SDmitry Baryshkov enum dpu_hw_intr_reg {
17597762d5SDmitry Baryshkov 	MDP_SSPP_TOP0_INTR,
18597762d5SDmitry Baryshkov 	MDP_SSPP_TOP0_INTR2,
19597762d5SDmitry Baryshkov 	MDP_SSPP_TOP0_HIST_INTR,
20597762d5SDmitry Baryshkov 	MDP_INTF0_INTR,
21597762d5SDmitry Baryshkov 	MDP_INTF1_INTR,
22597762d5SDmitry Baryshkov 	MDP_INTF2_INTR,
23597762d5SDmitry Baryshkov 	MDP_INTF3_INTR,
24597762d5SDmitry Baryshkov 	MDP_INTF4_INTR,
25597762d5SDmitry Baryshkov 	MDP_AD4_0_INTR,
26597762d5SDmitry Baryshkov 	MDP_AD4_1_INTR,
27597762d5SDmitry Baryshkov 	MDP_INTF0_7xxx_INTR,
28597762d5SDmitry Baryshkov 	MDP_INTF1_7xxx_INTR,
29*89688e21SBjorn Andersson 	MDP_INTF2_7xxx_INTR,
30*89688e21SBjorn Andersson 	MDP_INTF3_7xxx_INTR,
31*89688e21SBjorn Andersson 	MDP_INTF4_7xxx_INTR,
32597762d5SDmitry Baryshkov 	MDP_INTF5_7xxx_INTR,
33597762d5SDmitry Baryshkov 	MDP_INTR_MAX,
34597762d5SDmitry Baryshkov };
35597762d5SDmitry Baryshkov 
36667e9985SDmitry Baryshkov #define DPU_IRQ_IDX(reg_idx, offset)	(reg_idx * 32 + offset)
37667e9985SDmitry Baryshkov 
3825fdd593SJeykumar Sankaran /**
3925fdd593SJeykumar Sankaran  * struct dpu_hw_intr: hw interrupts handling data structure
4025fdd593SJeykumar Sankaran  * @hw:               virtual address mapping
4125fdd593SJeykumar Sankaran  * @ops:              function pointer mapping for IRQ handling
4225fdd593SJeykumar Sankaran  * @cache_irq_mask:   array of IRQ enable masks reg storage created during init
4325fdd593SJeykumar Sankaran  * @save_irq_status:  array of IRQ status reg storage created during init
44667e9985SDmitry Baryshkov  * @total_irqs: total number of irq_idx mapped in the hw_interrupts
4525fdd593SJeykumar Sankaran  * @irq_lock:         spinlock for accessing IRQ resources
46f25f6566SDmitry Baryshkov  * @irq_cb_tbl:       array of IRQ callbacks lists
47f25f6566SDmitry Baryshkov  * @irq_counts:       array of IRQ counts
4825fdd593SJeykumar Sankaran  */
4925fdd593SJeykumar Sankaran struct dpu_hw_intr {
5025fdd593SJeykumar Sankaran 	struct dpu_hw_blk_reg_map hw;
5125fdd593SJeykumar Sankaran 	u32 *cache_irq_mask;
5225fdd593SJeykumar Sankaran 	u32 *save_irq_status;
53667e9985SDmitry Baryshkov 	u32 total_irqs;
5425fdd593SJeykumar Sankaran 	spinlock_t irq_lock;
550846cca3SShubhashree Dhar 	unsigned long irq_mask;
56f25f6566SDmitry Baryshkov 
57f25f6566SDmitry Baryshkov 	struct list_head *irq_cb_tbl;
58f25f6566SDmitry Baryshkov 	atomic_t *irq_counts;
5925fdd593SJeykumar Sankaran };
6025fdd593SJeykumar Sankaran 
6125fdd593SJeykumar Sankaran /**
6225fdd593SJeykumar Sankaran  * dpu_hw_intr_init(): Initializes the interrupts hw object
6325fdd593SJeykumar Sankaran  * @addr: mapped register io address of MDP
6425fdd593SJeykumar Sankaran  * @m :   pointer to mdss catalog data
6525fdd593SJeykumar Sankaran  */
6625fdd593SJeykumar Sankaran struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr,
6725fdd593SJeykumar Sankaran 		struct dpu_mdss_cfg *m);
6825fdd593SJeykumar Sankaran 
6925fdd593SJeykumar Sankaran /**
7025fdd593SJeykumar Sankaran  * dpu_hw_intr_destroy(): Cleanup interrutps hw object
7125fdd593SJeykumar Sankaran  * @intr: pointer to interrupts hw object
7225fdd593SJeykumar Sankaran  */
7325fdd593SJeykumar Sankaran void dpu_hw_intr_destroy(struct dpu_hw_intr *intr);
7425fdd593SJeykumar Sankaran #endif
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