125fdd593SJeykumar Sankaran /* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. 225fdd593SJeykumar Sankaran * 325fdd593SJeykumar Sankaran * This program is free software; you can redistribute it and/or modify 425fdd593SJeykumar Sankaran * it under the terms of the GNU General Public License version 2 and 525fdd593SJeykumar Sankaran * only version 2 as published by the Free Software Foundation. 625fdd593SJeykumar Sankaran * 725fdd593SJeykumar Sankaran * This program is distributed in the hope that it will be useful, 825fdd593SJeykumar Sankaran * but WITHOUT ANY WARRANTY; without even the implied warranty of 925fdd593SJeykumar Sankaran * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1025fdd593SJeykumar Sankaran * GNU General Public License for more details. 1125fdd593SJeykumar Sankaran */ 1225fdd593SJeykumar Sankaran 1325fdd593SJeykumar Sankaran #ifndef _DPU_HW_INTERRUPTS_H 1425fdd593SJeykumar Sankaran #define _DPU_HW_INTERRUPTS_H 1525fdd593SJeykumar Sankaran 1625fdd593SJeykumar Sankaran #include <linux/types.h> 1725fdd593SJeykumar Sankaran 1825fdd593SJeykumar Sankaran #include "dpu_hwio.h" 1925fdd593SJeykumar Sankaran #include "dpu_hw_catalog.h" 2025fdd593SJeykumar Sankaran #include "dpu_hw_util.h" 2125fdd593SJeykumar Sankaran #include "dpu_hw_mdss.h" 2225fdd593SJeykumar Sankaran 2325fdd593SJeykumar Sankaran #define IRQ_SOURCE_MDP BIT(0) 2425fdd593SJeykumar Sankaran #define IRQ_SOURCE_DSI0 BIT(4) 2525fdd593SJeykumar Sankaran #define IRQ_SOURCE_DSI1 BIT(5) 2625fdd593SJeykumar Sankaran #define IRQ_SOURCE_HDMI BIT(8) 2725fdd593SJeykumar Sankaran #define IRQ_SOURCE_EDP BIT(12) 2825fdd593SJeykumar Sankaran #define IRQ_SOURCE_MHL BIT(16) 2925fdd593SJeykumar Sankaran 3025fdd593SJeykumar Sankaran /** 3125fdd593SJeykumar Sankaran * dpu_intr_type - HW Interrupt Type 3225fdd593SJeykumar Sankaran * @DPU_IRQ_TYPE_WB_ROT_COMP: WB rotator done 3325fdd593SJeykumar Sankaran * @DPU_IRQ_TYPE_WB_WFD_COMP: WB WFD done 3425fdd593SJeykumar Sankaran * @DPU_IRQ_TYPE_PING_PONG_COMP: PingPong done 3525fdd593SJeykumar Sankaran * @DPU_IRQ_TYPE_PING_PONG_RD_PTR: PingPong read pointer 3625fdd593SJeykumar Sankaran * @DPU_IRQ_TYPE_PING_PONG_WR_PTR: PingPong write pointer 3725fdd593SJeykumar Sankaran * @DPU_IRQ_TYPE_PING_PONG_AUTO_REF: PingPong auto refresh 3825fdd593SJeykumar Sankaran * @DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK: PingPong Tear check 3925fdd593SJeykumar Sankaran * @DPU_IRQ_TYPE_PING_PONG_TE_CHECK: PingPong TE detection 4025fdd593SJeykumar Sankaran * @DPU_IRQ_TYPE_INTF_UNDER_RUN: INTF underrun 4125fdd593SJeykumar Sankaran * @DPU_IRQ_TYPE_INTF_VSYNC: INTF VSYNC 4225fdd593SJeykumar Sankaran * @DPU_IRQ_TYPE_CWB_OVERFLOW: Concurrent WB overflow 4325fdd593SJeykumar Sankaran * @DPU_IRQ_TYPE_HIST_VIG_DONE: VIG Histogram done 4425fdd593SJeykumar Sankaran * @DPU_IRQ_TYPE_HIST_VIG_RSTSEQ: VIG Histogram reset 4525fdd593SJeykumar Sankaran * @DPU_IRQ_TYPE_HIST_DSPP_DONE: DSPP Histogram done 4625fdd593SJeykumar Sankaran * @DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ: DSPP Histogram reset 4725fdd593SJeykumar Sankaran * @DPU_IRQ_TYPE_WD_TIMER: Watchdog timer 4825fdd593SJeykumar Sankaran * @DPU_IRQ_TYPE_SFI_VIDEO_IN: Video static frame INTR into static 4925fdd593SJeykumar Sankaran * @DPU_IRQ_TYPE_SFI_VIDEO_OUT: Video static frame INTR out-of static 5025fdd593SJeykumar Sankaran * @DPU_IRQ_TYPE_SFI_CMD_0_IN: DSI CMD0 static frame INTR into static 5125fdd593SJeykumar Sankaran * @DPU_IRQ_TYPE_SFI_CMD_0_OUT: DSI CMD0 static frame INTR out-of static 5225fdd593SJeykumar Sankaran * @DPU_IRQ_TYPE_SFI_CMD_1_IN: DSI CMD1 static frame INTR into static 5325fdd593SJeykumar Sankaran * @DPU_IRQ_TYPE_SFI_CMD_1_OUT: DSI CMD1 static frame INTR out-of static 5425fdd593SJeykumar Sankaran * @DPU_IRQ_TYPE_SFI_CMD_2_IN: DSI CMD2 static frame INTR into static 5525fdd593SJeykumar Sankaran * @DPU_IRQ_TYPE_SFI_CMD_2_OUT: DSI CMD2 static frame INTR out-of static 5625fdd593SJeykumar Sankaran * @DPU_IRQ_TYPE_PROG_LINE: Programmable Line interrupt 5725fdd593SJeykumar Sankaran * @DPU_IRQ_TYPE_AD4_BL_DONE: AD4 backlight 5825fdd593SJeykumar Sankaran * @DPU_IRQ_TYPE_CTL_START: Control start 5925fdd593SJeykumar Sankaran * @DPU_IRQ_TYPE_RESERVED: Reserved for expansion 6025fdd593SJeykumar Sankaran */ 6125fdd593SJeykumar Sankaran enum dpu_intr_type { 6225fdd593SJeykumar Sankaran DPU_IRQ_TYPE_WB_ROT_COMP, 6325fdd593SJeykumar Sankaran DPU_IRQ_TYPE_WB_WFD_COMP, 6425fdd593SJeykumar Sankaran DPU_IRQ_TYPE_PING_PONG_COMP, 6525fdd593SJeykumar Sankaran DPU_IRQ_TYPE_PING_PONG_RD_PTR, 6625fdd593SJeykumar Sankaran DPU_IRQ_TYPE_PING_PONG_WR_PTR, 6725fdd593SJeykumar Sankaran DPU_IRQ_TYPE_PING_PONG_AUTO_REF, 6825fdd593SJeykumar Sankaran DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK, 6925fdd593SJeykumar Sankaran DPU_IRQ_TYPE_PING_PONG_TE_CHECK, 7025fdd593SJeykumar Sankaran DPU_IRQ_TYPE_INTF_UNDER_RUN, 7125fdd593SJeykumar Sankaran DPU_IRQ_TYPE_INTF_VSYNC, 7225fdd593SJeykumar Sankaran DPU_IRQ_TYPE_CWB_OVERFLOW, 7325fdd593SJeykumar Sankaran DPU_IRQ_TYPE_HIST_VIG_DONE, 7425fdd593SJeykumar Sankaran DPU_IRQ_TYPE_HIST_VIG_RSTSEQ, 7525fdd593SJeykumar Sankaran DPU_IRQ_TYPE_HIST_DSPP_DONE, 7625fdd593SJeykumar Sankaran DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ, 7725fdd593SJeykumar Sankaran DPU_IRQ_TYPE_WD_TIMER, 7825fdd593SJeykumar Sankaran DPU_IRQ_TYPE_SFI_VIDEO_IN, 7925fdd593SJeykumar Sankaran DPU_IRQ_TYPE_SFI_VIDEO_OUT, 8025fdd593SJeykumar Sankaran DPU_IRQ_TYPE_SFI_CMD_0_IN, 8125fdd593SJeykumar Sankaran DPU_IRQ_TYPE_SFI_CMD_0_OUT, 8225fdd593SJeykumar Sankaran DPU_IRQ_TYPE_SFI_CMD_1_IN, 8325fdd593SJeykumar Sankaran DPU_IRQ_TYPE_SFI_CMD_1_OUT, 8425fdd593SJeykumar Sankaran DPU_IRQ_TYPE_SFI_CMD_2_IN, 8525fdd593SJeykumar Sankaran DPU_IRQ_TYPE_SFI_CMD_2_OUT, 8625fdd593SJeykumar Sankaran DPU_IRQ_TYPE_PROG_LINE, 8725fdd593SJeykumar Sankaran DPU_IRQ_TYPE_AD4_BL_DONE, 8825fdd593SJeykumar Sankaran DPU_IRQ_TYPE_CTL_START, 8925fdd593SJeykumar Sankaran DPU_IRQ_TYPE_RESERVED, 9025fdd593SJeykumar Sankaran }; 9125fdd593SJeykumar Sankaran 9225fdd593SJeykumar Sankaran struct dpu_hw_intr; 9325fdd593SJeykumar Sankaran 9425fdd593SJeykumar Sankaran /** 9525fdd593SJeykumar Sankaran * Interrupt operations. 9625fdd593SJeykumar Sankaran */ 9725fdd593SJeykumar Sankaran struct dpu_hw_intr_ops { 9825fdd593SJeykumar Sankaran /** 9925fdd593SJeykumar Sankaran * set_mask - Programs the given interrupt register with the 10025fdd593SJeykumar Sankaran * given interrupt mask. Register value will get overwritten. 10125fdd593SJeykumar Sankaran * @intr: HW interrupt handle 10225fdd593SJeykumar Sankaran * @reg_off: MDSS HW register offset 10325fdd593SJeykumar Sankaran * @irqmask: IRQ mask value 10425fdd593SJeykumar Sankaran */ 10525fdd593SJeykumar Sankaran void (*set_mask)( 10625fdd593SJeykumar Sankaran struct dpu_hw_intr *intr, 10725fdd593SJeykumar Sankaran uint32_t reg, 10825fdd593SJeykumar Sankaran uint32_t irqmask); 10925fdd593SJeykumar Sankaran 11025fdd593SJeykumar Sankaran /** 11125fdd593SJeykumar Sankaran * irq_idx_lookup - Lookup IRQ index on the HW interrupt type 11225fdd593SJeykumar Sankaran * Used for all irq related ops 11325fdd593SJeykumar Sankaran * @intr_type: Interrupt type defined in dpu_intr_type 11425fdd593SJeykumar Sankaran * @instance_idx: HW interrupt block instance 11525fdd593SJeykumar Sankaran * @return: irq_idx or -EINVAL for lookup fail 11625fdd593SJeykumar Sankaran */ 11725fdd593SJeykumar Sankaran int (*irq_idx_lookup)( 11825fdd593SJeykumar Sankaran enum dpu_intr_type intr_type, 11925fdd593SJeykumar Sankaran u32 instance_idx); 12025fdd593SJeykumar Sankaran 12125fdd593SJeykumar Sankaran /** 12225fdd593SJeykumar Sankaran * enable_irq - Enable IRQ based on lookup IRQ index 12325fdd593SJeykumar Sankaran * @intr: HW interrupt handle 12425fdd593SJeykumar Sankaran * @irq_idx: Lookup irq index return from irq_idx_lookup 12525fdd593SJeykumar Sankaran * @return: 0 for success, otherwise failure 12625fdd593SJeykumar Sankaran */ 12725fdd593SJeykumar Sankaran int (*enable_irq)( 12825fdd593SJeykumar Sankaran struct dpu_hw_intr *intr, 12925fdd593SJeykumar Sankaran int irq_idx); 13025fdd593SJeykumar Sankaran 13125fdd593SJeykumar Sankaran /** 13225fdd593SJeykumar Sankaran * disable_irq - Disable IRQ based on lookup IRQ index 13325fdd593SJeykumar Sankaran * @intr: HW interrupt handle 13425fdd593SJeykumar Sankaran * @irq_idx: Lookup irq index return from irq_idx_lookup 13525fdd593SJeykumar Sankaran * @return: 0 for success, otherwise failure 13625fdd593SJeykumar Sankaran */ 13725fdd593SJeykumar Sankaran int (*disable_irq)( 13825fdd593SJeykumar Sankaran struct dpu_hw_intr *intr, 13925fdd593SJeykumar Sankaran int irq_idx); 14025fdd593SJeykumar Sankaran 14125fdd593SJeykumar Sankaran /** 14225fdd593SJeykumar Sankaran * clear_all_irqs - Clears all the interrupts (i.e. acknowledges 14325fdd593SJeykumar Sankaran * any asserted IRQs). Useful during reset. 14425fdd593SJeykumar Sankaran * @intr: HW interrupt handle 14525fdd593SJeykumar Sankaran * @return: 0 for success, otherwise failure 14625fdd593SJeykumar Sankaran */ 14725fdd593SJeykumar Sankaran int (*clear_all_irqs)( 14825fdd593SJeykumar Sankaran struct dpu_hw_intr *intr); 14925fdd593SJeykumar Sankaran 15025fdd593SJeykumar Sankaran /** 15125fdd593SJeykumar Sankaran * disable_all_irqs - Disables all the interrupts. Useful during reset. 15225fdd593SJeykumar Sankaran * @intr: HW interrupt handle 15325fdd593SJeykumar Sankaran * @return: 0 for success, otherwise failure 15425fdd593SJeykumar Sankaran */ 15525fdd593SJeykumar Sankaran int (*disable_all_irqs)( 15625fdd593SJeykumar Sankaran struct dpu_hw_intr *intr); 15725fdd593SJeykumar Sankaran 15825fdd593SJeykumar Sankaran /** 15925fdd593SJeykumar Sankaran * dispatch_irqs - IRQ dispatcher will call the given callback 16025fdd593SJeykumar Sankaran * function when a matching interrupt status bit is 16125fdd593SJeykumar Sankaran * found in the irq mapping table. 16225fdd593SJeykumar Sankaran * @intr: HW interrupt handle 16325fdd593SJeykumar Sankaran * @cbfunc: Callback function pointer 16425fdd593SJeykumar Sankaran * @arg: Argument to pass back during callback 16525fdd593SJeykumar Sankaran */ 16625fdd593SJeykumar Sankaran void (*dispatch_irqs)( 16725fdd593SJeykumar Sankaran struct dpu_hw_intr *intr, 16825fdd593SJeykumar Sankaran void (*cbfunc)(void *arg, int irq_idx), 16925fdd593SJeykumar Sankaran void *arg); 17025fdd593SJeykumar Sankaran 17125fdd593SJeykumar Sankaran /** 17225fdd593SJeykumar Sankaran * get_interrupt_statuses - Gets and store value from all interrupt 17325fdd593SJeykumar Sankaran * status registers that are currently fired. 17425fdd593SJeykumar Sankaran * @intr: HW interrupt handle 17525fdd593SJeykumar Sankaran */ 17625fdd593SJeykumar Sankaran void (*get_interrupt_statuses)( 17725fdd593SJeykumar Sankaran struct dpu_hw_intr *intr); 17825fdd593SJeykumar Sankaran 17925fdd593SJeykumar Sankaran /** 18025fdd593SJeykumar Sankaran * clear_interrupt_status - Clears HW interrupt status based on given 18125fdd593SJeykumar Sankaran * lookup IRQ index. 18225fdd593SJeykumar Sankaran * @intr: HW interrupt handle 18325fdd593SJeykumar Sankaran * @irq_idx: Lookup irq index return from irq_idx_lookup 18425fdd593SJeykumar Sankaran */ 18525fdd593SJeykumar Sankaran void (*clear_interrupt_status)( 18625fdd593SJeykumar Sankaran struct dpu_hw_intr *intr, 18725fdd593SJeykumar Sankaran int irq_idx); 18825fdd593SJeykumar Sankaran 18925fdd593SJeykumar Sankaran /** 19025fdd593SJeykumar Sankaran * clear_intr_status_nolock() - clears the HW interrupts without lock 19125fdd593SJeykumar Sankaran * @intr: HW interrupt handle 19225fdd593SJeykumar Sankaran * @irq_idx: Lookup irq index return from irq_idx_lookup 19325fdd593SJeykumar Sankaran */ 19425fdd593SJeykumar Sankaran void (*clear_intr_status_nolock)( 19525fdd593SJeykumar Sankaran struct dpu_hw_intr *intr, 19625fdd593SJeykumar Sankaran int irq_idx); 19725fdd593SJeykumar Sankaran 19825fdd593SJeykumar Sankaran /** 19925fdd593SJeykumar Sankaran * get_interrupt_status - Gets HW interrupt status, and clear if set, 20025fdd593SJeykumar Sankaran * based on given lookup IRQ index. 20125fdd593SJeykumar Sankaran * @intr: HW interrupt handle 20225fdd593SJeykumar Sankaran * @irq_idx: Lookup irq index return from irq_idx_lookup 20325fdd593SJeykumar Sankaran * @clear: True to clear irq after read 20425fdd593SJeykumar Sankaran */ 20525fdd593SJeykumar Sankaran u32 (*get_interrupt_status)( 20625fdd593SJeykumar Sankaran struct dpu_hw_intr *intr, 20725fdd593SJeykumar Sankaran int irq_idx, 20825fdd593SJeykumar Sankaran bool clear); 20925fdd593SJeykumar Sankaran 21025fdd593SJeykumar Sankaran /** 21125fdd593SJeykumar Sankaran * get_valid_interrupts - Gets a mask of all valid interrupt sources 21225fdd593SJeykumar Sankaran * within DPU. These are actually status bits 21325fdd593SJeykumar Sankaran * within interrupt registers that specify the 21425fdd593SJeykumar Sankaran * source of the interrupt in IRQs. For example, 21525fdd593SJeykumar Sankaran * valid interrupt sources can be MDP, DSI, 21625fdd593SJeykumar Sankaran * HDMI etc. 21725fdd593SJeykumar Sankaran * @intr: HW interrupt handle 21825fdd593SJeykumar Sankaran * @mask: Returning the interrupt source MASK 21925fdd593SJeykumar Sankaran * @return: 0 for success, otherwise failure 22025fdd593SJeykumar Sankaran */ 22125fdd593SJeykumar Sankaran int (*get_valid_interrupts)( 22225fdd593SJeykumar Sankaran struct dpu_hw_intr *intr, 22325fdd593SJeykumar Sankaran uint32_t *mask); 22425fdd593SJeykumar Sankaran }; 22525fdd593SJeykumar Sankaran 22625fdd593SJeykumar Sankaran /** 22725fdd593SJeykumar Sankaran * struct dpu_hw_intr: hw interrupts handling data structure 22825fdd593SJeykumar Sankaran * @hw: virtual address mapping 22925fdd593SJeykumar Sankaran * @ops: function pointer mapping for IRQ handling 23025fdd593SJeykumar Sankaran * @cache_irq_mask: array of IRQ enable masks reg storage created during init 23125fdd593SJeykumar Sankaran * @save_irq_status: array of IRQ status reg storage created during init 23225fdd593SJeykumar Sankaran * @irq_idx_tbl_size: total number of irq_idx mapped in the hw_interrupts 23325fdd593SJeykumar Sankaran * @irq_lock: spinlock for accessing IRQ resources 23425fdd593SJeykumar Sankaran */ 23525fdd593SJeykumar Sankaran struct dpu_hw_intr { 23625fdd593SJeykumar Sankaran struct dpu_hw_blk_reg_map hw; 23725fdd593SJeykumar Sankaran struct dpu_hw_intr_ops ops; 23825fdd593SJeykumar Sankaran u32 *cache_irq_mask; 23925fdd593SJeykumar Sankaran u32 *save_irq_status; 24025fdd593SJeykumar Sankaran u32 irq_idx_tbl_size; 24125fdd593SJeykumar Sankaran spinlock_t irq_lock; 24225fdd593SJeykumar Sankaran }; 24325fdd593SJeykumar Sankaran 24425fdd593SJeykumar Sankaran /** 24525fdd593SJeykumar Sankaran * dpu_hw_intr_init(): Initializes the interrupts hw object 24625fdd593SJeykumar Sankaran * @addr: mapped register io address of MDP 24725fdd593SJeykumar Sankaran * @m : pointer to mdss catalog data 24825fdd593SJeykumar Sankaran */ 24925fdd593SJeykumar Sankaran struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr, 25025fdd593SJeykumar Sankaran struct dpu_mdss_cfg *m); 25125fdd593SJeykumar Sankaran 25225fdd593SJeykumar Sankaran /** 25325fdd593SJeykumar Sankaran * dpu_hw_intr_destroy(): Cleanup interrutps hw object 25425fdd593SJeykumar Sankaran * @intr: pointer to interrupts hw object 25525fdd593SJeykumar Sankaran */ 25625fdd593SJeykumar Sankaran void dpu_hw_intr_destroy(struct dpu_hw_intr *intr); 25725fdd593SJeykumar Sankaran #endif 258