197fb5e8dSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 225fdd593SJeykumar Sankaran /* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. 325fdd593SJeykumar Sankaran */ 425fdd593SJeykumar Sankaran 525fdd593SJeykumar Sankaran #ifndef _DPU_HW_INTERRUPTS_H 625fdd593SJeykumar Sankaran #define _DPU_HW_INTERRUPTS_H 725fdd593SJeykumar Sankaran 825fdd593SJeykumar Sankaran #include <linux/types.h> 925fdd593SJeykumar Sankaran 1025fdd593SJeykumar Sankaran #include "dpu_hwio.h" 1125fdd593SJeykumar Sankaran #include "dpu_hw_catalog.h" 1225fdd593SJeykumar Sankaran #include "dpu_hw_util.h" 1325fdd593SJeykumar Sankaran #include "dpu_hw_mdss.h" 1425fdd593SJeykumar Sankaran 1525fdd593SJeykumar Sankaran /** 1625fdd593SJeykumar Sankaran * dpu_intr_type - HW Interrupt Type 1725fdd593SJeykumar Sankaran * @DPU_IRQ_TYPE_WB_ROT_COMP: WB rotator done 1825fdd593SJeykumar Sankaran * @DPU_IRQ_TYPE_WB_WFD_COMP: WB WFD done 1925fdd593SJeykumar Sankaran * @DPU_IRQ_TYPE_PING_PONG_COMP: PingPong done 2025fdd593SJeykumar Sankaran * @DPU_IRQ_TYPE_PING_PONG_RD_PTR: PingPong read pointer 2125fdd593SJeykumar Sankaran * @DPU_IRQ_TYPE_PING_PONG_WR_PTR: PingPong write pointer 2225fdd593SJeykumar Sankaran * @DPU_IRQ_TYPE_PING_PONG_AUTO_REF: PingPong auto refresh 2325fdd593SJeykumar Sankaran * @DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK: PingPong Tear check 2425fdd593SJeykumar Sankaran * @DPU_IRQ_TYPE_PING_PONG_TE_CHECK: PingPong TE detection 2525fdd593SJeykumar Sankaran * @DPU_IRQ_TYPE_INTF_UNDER_RUN: INTF underrun 2625fdd593SJeykumar Sankaran * @DPU_IRQ_TYPE_INTF_VSYNC: INTF VSYNC 2725fdd593SJeykumar Sankaran * @DPU_IRQ_TYPE_CWB_OVERFLOW: Concurrent WB overflow 2825fdd593SJeykumar Sankaran * @DPU_IRQ_TYPE_HIST_VIG_DONE: VIG Histogram done 2925fdd593SJeykumar Sankaran * @DPU_IRQ_TYPE_HIST_VIG_RSTSEQ: VIG Histogram reset 3025fdd593SJeykumar Sankaran * @DPU_IRQ_TYPE_HIST_DSPP_DONE: DSPP Histogram done 3125fdd593SJeykumar Sankaran * @DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ: DSPP Histogram reset 3225fdd593SJeykumar Sankaran * @DPU_IRQ_TYPE_WD_TIMER: Watchdog timer 3325fdd593SJeykumar Sankaran * @DPU_IRQ_TYPE_SFI_VIDEO_IN: Video static frame INTR into static 3425fdd593SJeykumar Sankaran * @DPU_IRQ_TYPE_SFI_VIDEO_OUT: Video static frame INTR out-of static 3525fdd593SJeykumar Sankaran * @DPU_IRQ_TYPE_SFI_CMD_0_IN: DSI CMD0 static frame INTR into static 3625fdd593SJeykumar Sankaran * @DPU_IRQ_TYPE_SFI_CMD_0_OUT: DSI CMD0 static frame INTR out-of static 3725fdd593SJeykumar Sankaran * @DPU_IRQ_TYPE_SFI_CMD_1_IN: DSI CMD1 static frame INTR into static 3825fdd593SJeykumar Sankaran * @DPU_IRQ_TYPE_SFI_CMD_1_OUT: DSI CMD1 static frame INTR out-of static 3925fdd593SJeykumar Sankaran * @DPU_IRQ_TYPE_SFI_CMD_2_IN: DSI CMD2 static frame INTR into static 4025fdd593SJeykumar Sankaran * @DPU_IRQ_TYPE_SFI_CMD_2_OUT: DSI CMD2 static frame INTR out-of static 4125fdd593SJeykumar Sankaran * @DPU_IRQ_TYPE_PROG_LINE: Programmable Line interrupt 4225fdd593SJeykumar Sankaran * @DPU_IRQ_TYPE_AD4_BL_DONE: AD4 backlight 4325fdd593SJeykumar Sankaran * @DPU_IRQ_TYPE_CTL_START: Control start 4425fdd593SJeykumar Sankaran * @DPU_IRQ_TYPE_RESERVED: Reserved for expansion 4525fdd593SJeykumar Sankaran */ 4625fdd593SJeykumar Sankaran enum dpu_intr_type { 4725fdd593SJeykumar Sankaran DPU_IRQ_TYPE_WB_ROT_COMP, 4825fdd593SJeykumar Sankaran DPU_IRQ_TYPE_WB_WFD_COMP, 4925fdd593SJeykumar Sankaran DPU_IRQ_TYPE_PING_PONG_COMP, 5025fdd593SJeykumar Sankaran DPU_IRQ_TYPE_PING_PONG_RD_PTR, 5125fdd593SJeykumar Sankaran DPU_IRQ_TYPE_PING_PONG_WR_PTR, 5225fdd593SJeykumar Sankaran DPU_IRQ_TYPE_PING_PONG_AUTO_REF, 5325fdd593SJeykumar Sankaran DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK, 5425fdd593SJeykumar Sankaran DPU_IRQ_TYPE_PING_PONG_TE_CHECK, 5525fdd593SJeykumar Sankaran DPU_IRQ_TYPE_INTF_UNDER_RUN, 5625fdd593SJeykumar Sankaran DPU_IRQ_TYPE_INTF_VSYNC, 5725fdd593SJeykumar Sankaran DPU_IRQ_TYPE_CWB_OVERFLOW, 5825fdd593SJeykumar Sankaran DPU_IRQ_TYPE_HIST_VIG_DONE, 5925fdd593SJeykumar Sankaran DPU_IRQ_TYPE_HIST_VIG_RSTSEQ, 6025fdd593SJeykumar Sankaran DPU_IRQ_TYPE_HIST_DSPP_DONE, 6125fdd593SJeykumar Sankaran DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ, 6225fdd593SJeykumar Sankaran DPU_IRQ_TYPE_WD_TIMER, 6325fdd593SJeykumar Sankaran DPU_IRQ_TYPE_SFI_VIDEO_IN, 6425fdd593SJeykumar Sankaran DPU_IRQ_TYPE_SFI_VIDEO_OUT, 6525fdd593SJeykumar Sankaran DPU_IRQ_TYPE_SFI_CMD_0_IN, 6625fdd593SJeykumar Sankaran DPU_IRQ_TYPE_SFI_CMD_0_OUT, 6725fdd593SJeykumar Sankaran DPU_IRQ_TYPE_SFI_CMD_1_IN, 6825fdd593SJeykumar Sankaran DPU_IRQ_TYPE_SFI_CMD_1_OUT, 6925fdd593SJeykumar Sankaran DPU_IRQ_TYPE_SFI_CMD_2_IN, 7025fdd593SJeykumar Sankaran DPU_IRQ_TYPE_SFI_CMD_2_OUT, 7125fdd593SJeykumar Sankaran DPU_IRQ_TYPE_PROG_LINE, 7225fdd593SJeykumar Sankaran DPU_IRQ_TYPE_AD4_BL_DONE, 7325fdd593SJeykumar Sankaran DPU_IRQ_TYPE_CTL_START, 7425fdd593SJeykumar Sankaran DPU_IRQ_TYPE_RESERVED, 7525fdd593SJeykumar Sankaran }; 7625fdd593SJeykumar Sankaran 7725fdd593SJeykumar Sankaran struct dpu_hw_intr; 7825fdd593SJeykumar Sankaran 7925fdd593SJeykumar Sankaran /** 8025fdd593SJeykumar Sankaran * Interrupt operations. 8125fdd593SJeykumar Sankaran */ 8225fdd593SJeykumar Sankaran struct dpu_hw_intr_ops { 8325fdd593SJeykumar Sankaran /** 8425fdd593SJeykumar Sankaran * irq_idx_lookup - Lookup IRQ index on the HW interrupt type 8525fdd593SJeykumar Sankaran * Used for all irq related ops 8625fdd593SJeykumar Sankaran * @intr_type: Interrupt type defined in dpu_intr_type 8725fdd593SJeykumar Sankaran * @instance_idx: HW interrupt block instance 8825fdd593SJeykumar Sankaran * @return: irq_idx or -EINVAL for lookup fail 8925fdd593SJeykumar Sankaran */ 9025fdd593SJeykumar Sankaran int (*irq_idx_lookup)( 9125fdd593SJeykumar Sankaran enum dpu_intr_type intr_type, 9225fdd593SJeykumar Sankaran u32 instance_idx); 9325fdd593SJeykumar Sankaran 9425fdd593SJeykumar Sankaran /** 9525fdd593SJeykumar Sankaran * enable_irq - Enable IRQ based on lookup IRQ index 9625fdd593SJeykumar Sankaran * @intr: HW interrupt handle 9725fdd593SJeykumar Sankaran * @irq_idx: Lookup irq index return from irq_idx_lookup 9825fdd593SJeykumar Sankaran * @return: 0 for success, otherwise failure 9925fdd593SJeykumar Sankaran */ 10025fdd593SJeykumar Sankaran int (*enable_irq)( 10125fdd593SJeykumar Sankaran struct dpu_hw_intr *intr, 10225fdd593SJeykumar Sankaran int irq_idx); 10325fdd593SJeykumar Sankaran 10425fdd593SJeykumar Sankaran /** 10525fdd593SJeykumar Sankaran * disable_irq - Disable IRQ based on lookup IRQ index 10625fdd593SJeykumar Sankaran * @intr: HW interrupt handle 10725fdd593SJeykumar Sankaran * @irq_idx: Lookup irq index return from irq_idx_lookup 10825fdd593SJeykumar Sankaran * @return: 0 for success, otherwise failure 10925fdd593SJeykumar Sankaran */ 11025fdd593SJeykumar Sankaran int (*disable_irq)( 11125fdd593SJeykumar Sankaran struct dpu_hw_intr *intr, 11225fdd593SJeykumar Sankaran int irq_idx); 11325fdd593SJeykumar Sankaran 11425fdd593SJeykumar Sankaran /** 11525fdd593SJeykumar Sankaran * clear_all_irqs - Clears all the interrupts (i.e. acknowledges 11625fdd593SJeykumar Sankaran * any asserted IRQs). Useful during reset. 11725fdd593SJeykumar Sankaran * @intr: HW interrupt handle 11825fdd593SJeykumar Sankaran * @return: 0 for success, otherwise failure 11925fdd593SJeykumar Sankaran */ 12025fdd593SJeykumar Sankaran int (*clear_all_irqs)( 12125fdd593SJeykumar Sankaran struct dpu_hw_intr *intr); 12225fdd593SJeykumar Sankaran 12325fdd593SJeykumar Sankaran /** 12425fdd593SJeykumar Sankaran * disable_all_irqs - Disables all the interrupts. Useful during reset. 12525fdd593SJeykumar Sankaran * @intr: HW interrupt handle 12625fdd593SJeykumar Sankaran * @return: 0 for success, otherwise failure 12725fdd593SJeykumar Sankaran */ 12825fdd593SJeykumar Sankaran int (*disable_all_irqs)( 12925fdd593SJeykumar Sankaran struct dpu_hw_intr *intr); 13025fdd593SJeykumar Sankaran 13125fdd593SJeykumar Sankaran /** 13225fdd593SJeykumar Sankaran * dispatch_irqs - IRQ dispatcher will call the given callback 13325fdd593SJeykumar Sankaran * function when a matching interrupt status bit is 13425fdd593SJeykumar Sankaran * found in the irq mapping table. 13525fdd593SJeykumar Sankaran * @intr: HW interrupt handle 13625fdd593SJeykumar Sankaran * @cbfunc: Callback function pointer 13725fdd593SJeykumar Sankaran * @arg: Argument to pass back during callback 13825fdd593SJeykumar Sankaran */ 13925fdd593SJeykumar Sankaran void (*dispatch_irqs)( 14025fdd593SJeykumar Sankaran struct dpu_hw_intr *intr, 14125fdd593SJeykumar Sankaran void (*cbfunc)(void *arg, int irq_idx), 14225fdd593SJeykumar Sankaran void *arg); 14325fdd593SJeykumar Sankaran 14425fdd593SJeykumar Sankaran /** 14525fdd593SJeykumar Sankaran * get_interrupt_statuses - Gets and store value from all interrupt 14625fdd593SJeykumar Sankaran * status registers that are currently fired. 14725fdd593SJeykumar Sankaran * @intr: HW interrupt handle 14825fdd593SJeykumar Sankaran */ 14925fdd593SJeykumar Sankaran void (*get_interrupt_statuses)( 15025fdd593SJeykumar Sankaran struct dpu_hw_intr *intr); 15125fdd593SJeykumar Sankaran 15225fdd593SJeykumar Sankaran /** 15325fdd593SJeykumar Sankaran * clear_intr_status_nolock() - clears the HW interrupts without lock 15425fdd593SJeykumar Sankaran * @intr: HW interrupt handle 15525fdd593SJeykumar Sankaran * @irq_idx: Lookup irq index return from irq_idx_lookup 15625fdd593SJeykumar Sankaran */ 15725fdd593SJeykumar Sankaran void (*clear_intr_status_nolock)( 15825fdd593SJeykumar Sankaran struct dpu_hw_intr *intr, 15925fdd593SJeykumar Sankaran int irq_idx); 16025fdd593SJeykumar Sankaran 16125fdd593SJeykumar Sankaran /** 16225fdd593SJeykumar Sankaran * get_interrupt_status - Gets HW interrupt status, and clear if set, 16325fdd593SJeykumar Sankaran * based on given lookup IRQ index. 16425fdd593SJeykumar Sankaran * @intr: HW interrupt handle 16525fdd593SJeykumar Sankaran * @irq_idx: Lookup irq index return from irq_idx_lookup 16625fdd593SJeykumar Sankaran * @clear: True to clear irq after read 16725fdd593SJeykumar Sankaran */ 16825fdd593SJeykumar Sankaran u32 (*get_interrupt_status)( 16925fdd593SJeykumar Sankaran struct dpu_hw_intr *intr, 17025fdd593SJeykumar Sankaran int irq_idx, 17125fdd593SJeykumar Sankaran bool clear); 17225fdd593SJeykumar Sankaran }; 17325fdd593SJeykumar Sankaran 17425fdd593SJeykumar Sankaran /** 17525fdd593SJeykumar Sankaran * struct dpu_hw_intr: hw interrupts handling data structure 17625fdd593SJeykumar Sankaran * @hw: virtual address mapping 17725fdd593SJeykumar Sankaran * @ops: function pointer mapping for IRQ handling 17825fdd593SJeykumar Sankaran * @cache_irq_mask: array of IRQ enable masks reg storage created during init 17925fdd593SJeykumar Sankaran * @save_irq_status: array of IRQ status reg storage created during init 18025fdd593SJeykumar Sankaran * @irq_idx_tbl_size: total number of irq_idx mapped in the hw_interrupts 18125fdd593SJeykumar Sankaran * @irq_lock: spinlock for accessing IRQ resources 18225fdd593SJeykumar Sankaran */ 18325fdd593SJeykumar Sankaran struct dpu_hw_intr { 18425fdd593SJeykumar Sankaran struct dpu_hw_blk_reg_map hw; 18525fdd593SJeykumar Sankaran struct dpu_hw_intr_ops ops; 18625fdd593SJeykumar Sankaran u32 *cache_irq_mask; 18725fdd593SJeykumar Sankaran u32 *save_irq_status; 18825fdd593SJeykumar Sankaran u32 irq_idx_tbl_size; 18925fdd593SJeykumar Sankaran spinlock_t irq_lock; 1900846cca3SShubhashree Dhar unsigned long irq_mask; 19125fdd593SJeykumar Sankaran }; 19225fdd593SJeykumar Sankaran 19325fdd593SJeykumar Sankaran /** 19425fdd593SJeykumar Sankaran * dpu_hw_intr_init(): Initializes the interrupts hw object 19525fdd593SJeykumar Sankaran * @addr: mapped register io address of MDP 19625fdd593SJeykumar Sankaran * @m : pointer to mdss catalog data 19725fdd593SJeykumar Sankaran */ 19825fdd593SJeykumar Sankaran struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr, 19925fdd593SJeykumar Sankaran struct dpu_mdss_cfg *m); 20025fdd593SJeykumar Sankaran 20125fdd593SJeykumar Sankaran /** 20225fdd593SJeykumar Sankaran * dpu_hw_intr_destroy(): Cleanup interrutps hw object 20325fdd593SJeykumar Sankaran * @intr: pointer to interrupts hw object 20425fdd593SJeykumar Sankaran */ 20525fdd593SJeykumar Sankaran void dpu_hw_intr_destroy(struct dpu_hw_intr *intr); 20625fdd593SJeykumar Sankaran #endif 207