1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. 3 */ 4 5 #include <linux/bitops.h> 6 #include <linux/slab.h> 7 8 #include "dpu_kms.h" 9 #include "dpu_hw_interrupts.h" 10 #include "dpu_hw_util.h" 11 #include "dpu_hw_mdss.h" 12 13 /** 14 * Register offsets in MDSS register file for the interrupt registers 15 * w.r.t. to the MDP base 16 */ 17 #define MDP_SSPP_TOP0_OFF 0x0 18 #define MDP_INTF_0_OFF 0x6A000 19 #define MDP_INTF_1_OFF 0x6A800 20 #define MDP_INTF_2_OFF 0x6B000 21 #define MDP_INTF_3_OFF 0x6B800 22 #define MDP_INTF_4_OFF 0x6C000 23 #define MDP_AD4_0_OFF 0x7C000 24 #define MDP_AD4_1_OFF 0x7D000 25 #define MDP_AD4_INTR_EN_OFF 0x41c 26 #define MDP_AD4_INTR_CLEAR_OFF 0x424 27 #define MDP_AD4_INTR_STATUS_OFF 0x420 28 29 /** 30 * WB interrupt status bit definitions 31 */ 32 #define DPU_INTR_WB_0_DONE BIT(0) 33 #define DPU_INTR_WB_1_DONE BIT(1) 34 #define DPU_INTR_WB_2_DONE BIT(4) 35 36 /** 37 * WDOG timer interrupt status bit definitions 38 */ 39 #define DPU_INTR_WD_TIMER_0_DONE BIT(2) 40 #define DPU_INTR_WD_TIMER_1_DONE BIT(3) 41 #define DPU_INTR_WD_TIMER_2_DONE BIT(5) 42 #define DPU_INTR_WD_TIMER_3_DONE BIT(6) 43 #define DPU_INTR_WD_TIMER_4_DONE BIT(7) 44 45 /** 46 * Pingpong interrupt status bit definitions 47 */ 48 #define DPU_INTR_PING_PONG_0_DONE BIT(8) 49 #define DPU_INTR_PING_PONG_1_DONE BIT(9) 50 #define DPU_INTR_PING_PONG_2_DONE BIT(10) 51 #define DPU_INTR_PING_PONG_3_DONE BIT(11) 52 #define DPU_INTR_PING_PONG_0_RD_PTR BIT(12) 53 #define DPU_INTR_PING_PONG_1_RD_PTR BIT(13) 54 #define DPU_INTR_PING_PONG_2_RD_PTR BIT(14) 55 #define DPU_INTR_PING_PONG_3_RD_PTR BIT(15) 56 #define DPU_INTR_PING_PONG_0_WR_PTR BIT(16) 57 #define DPU_INTR_PING_PONG_1_WR_PTR BIT(17) 58 #define DPU_INTR_PING_PONG_2_WR_PTR BIT(18) 59 #define DPU_INTR_PING_PONG_3_WR_PTR BIT(19) 60 #define DPU_INTR_PING_PONG_0_AUTOREFRESH_DONE BIT(20) 61 #define DPU_INTR_PING_PONG_1_AUTOREFRESH_DONE BIT(21) 62 #define DPU_INTR_PING_PONG_2_AUTOREFRESH_DONE BIT(22) 63 #define DPU_INTR_PING_PONG_3_AUTOREFRESH_DONE BIT(23) 64 65 /** 66 * Interface interrupt status bit definitions 67 */ 68 #define DPU_INTR_INTF_0_UNDERRUN BIT(24) 69 #define DPU_INTR_INTF_1_UNDERRUN BIT(26) 70 #define DPU_INTR_INTF_2_UNDERRUN BIT(28) 71 #define DPU_INTR_INTF_3_UNDERRUN BIT(30) 72 #define DPU_INTR_INTF_0_VSYNC BIT(25) 73 #define DPU_INTR_INTF_1_VSYNC BIT(27) 74 #define DPU_INTR_INTF_2_VSYNC BIT(29) 75 #define DPU_INTR_INTF_3_VSYNC BIT(31) 76 77 /** 78 * Pingpong Secondary interrupt status bit definitions 79 */ 80 #define DPU_INTR_PING_PONG_S0_AUTOREFRESH_DONE BIT(0) 81 #define DPU_INTR_PING_PONG_S0_WR_PTR BIT(4) 82 #define DPU_INTR_PING_PONG_S0_RD_PTR BIT(8) 83 #define DPU_INTR_PING_PONG_S0_TEAR_DETECTED BIT(22) 84 #define DPU_INTR_PING_PONG_S0_TE_DETECTED BIT(28) 85 86 /** 87 * Pingpong TEAR detection interrupt status bit definitions 88 */ 89 #define DPU_INTR_PING_PONG_0_TEAR_DETECTED BIT(16) 90 #define DPU_INTR_PING_PONG_1_TEAR_DETECTED BIT(17) 91 #define DPU_INTR_PING_PONG_2_TEAR_DETECTED BIT(18) 92 #define DPU_INTR_PING_PONG_3_TEAR_DETECTED BIT(19) 93 94 /** 95 * Pingpong TE detection interrupt status bit definitions 96 */ 97 #define DPU_INTR_PING_PONG_0_TE_DETECTED BIT(24) 98 #define DPU_INTR_PING_PONG_1_TE_DETECTED BIT(25) 99 #define DPU_INTR_PING_PONG_2_TE_DETECTED BIT(26) 100 #define DPU_INTR_PING_PONG_3_TE_DETECTED BIT(27) 101 102 /** 103 * Ctl start interrupt status bit definitions 104 */ 105 #define DPU_INTR_CTL_0_START BIT(9) 106 #define DPU_INTR_CTL_1_START BIT(10) 107 #define DPU_INTR_CTL_2_START BIT(11) 108 #define DPU_INTR_CTL_3_START BIT(12) 109 #define DPU_INTR_CTL_4_START BIT(13) 110 111 /** 112 * Concurrent WB overflow interrupt status bit definitions 113 */ 114 #define DPU_INTR_CWB_2_OVERFLOW BIT(14) 115 #define DPU_INTR_CWB_3_OVERFLOW BIT(15) 116 117 /** 118 * Histogram VIG done interrupt status bit definitions 119 */ 120 #define DPU_INTR_HIST_VIG_0_DONE BIT(0) 121 #define DPU_INTR_HIST_VIG_1_DONE BIT(4) 122 #define DPU_INTR_HIST_VIG_2_DONE BIT(8) 123 #define DPU_INTR_HIST_VIG_3_DONE BIT(10) 124 125 /** 126 * Histogram VIG reset Sequence done interrupt status bit definitions 127 */ 128 #define DPU_INTR_HIST_VIG_0_RSTSEQ_DONE BIT(1) 129 #define DPU_INTR_HIST_VIG_1_RSTSEQ_DONE BIT(5) 130 #define DPU_INTR_HIST_VIG_2_RSTSEQ_DONE BIT(9) 131 #define DPU_INTR_HIST_VIG_3_RSTSEQ_DONE BIT(11) 132 133 /** 134 * Histogram DSPP done interrupt status bit definitions 135 */ 136 #define DPU_INTR_HIST_DSPP_0_DONE BIT(12) 137 #define DPU_INTR_HIST_DSPP_1_DONE BIT(16) 138 #define DPU_INTR_HIST_DSPP_2_DONE BIT(20) 139 #define DPU_INTR_HIST_DSPP_3_DONE BIT(22) 140 141 /** 142 * Histogram DSPP reset Sequence done interrupt status bit definitions 143 */ 144 #define DPU_INTR_HIST_DSPP_0_RSTSEQ_DONE BIT(13) 145 #define DPU_INTR_HIST_DSPP_1_RSTSEQ_DONE BIT(17) 146 #define DPU_INTR_HIST_DSPP_2_RSTSEQ_DONE BIT(21) 147 #define DPU_INTR_HIST_DSPP_3_RSTSEQ_DONE BIT(23) 148 149 /** 150 * INTF interrupt status bit definitions 151 */ 152 #define DPU_INTR_VIDEO_INTO_STATIC BIT(0) 153 #define DPU_INTR_VIDEO_OUTOF_STATIC BIT(1) 154 #define DPU_INTR_DSICMD_0_INTO_STATIC BIT(2) 155 #define DPU_INTR_DSICMD_0_OUTOF_STATIC BIT(3) 156 #define DPU_INTR_DSICMD_1_INTO_STATIC BIT(4) 157 #define DPU_INTR_DSICMD_1_OUTOF_STATIC BIT(5) 158 #define DPU_INTR_DSICMD_2_INTO_STATIC BIT(6) 159 #define DPU_INTR_DSICMD_2_OUTOF_STATIC BIT(7) 160 #define DPU_INTR_PROG_LINE BIT(8) 161 162 /** 163 * AD4 interrupt status bit definitions 164 */ 165 #define DPU_INTR_BACKLIGHT_UPDATED BIT(0) 166 /** 167 * struct dpu_intr_reg - array of DPU register sets 168 * @clr_off: offset to CLEAR reg 169 * @en_off: offset to ENABLE reg 170 * @status_off: offset to STATUS reg 171 */ 172 struct dpu_intr_reg { 173 u32 clr_off; 174 u32 en_off; 175 u32 status_off; 176 }; 177 178 /** 179 * struct dpu_irq_type - maps each irq with i/f 180 * @intr_type: type of interrupt listed in dpu_intr_type 181 * @instance_idx: instance index of the associated HW block in DPU 182 * @irq_mask: corresponding bit in the interrupt status reg 183 * @reg_idx: which reg set to use 184 */ 185 struct dpu_irq_type { 186 u32 intr_type; 187 u32 instance_idx; 188 u32 irq_mask; 189 u32 reg_idx; 190 }; 191 192 /* 193 * struct dpu_intr_reg - List of DPU interrupt registers 194 */ 195 static const struct dpu_intr_reg dpu_intr_set[] = { 196 { 197 MDP_SSPP_TOP0_OFF+INTR_CLEAR, 198 MDP_SSPP_TOP0_OFF+INTR_EN, 199 MDP_SSPP_TOP0_OFF+INTR_STATUS 200 }, 201 { 202 MDP_SSPP_TOP0_OFF+INTR2_CLEAR, 203 MDP_SSPP_TOP0_OFF+INTR2_EN, 204 MDP_SSPP_TOP0_OFF+INTR2_STATUS 205 }, 206 { 207 MDP_SSPP_TOP0_OFF+HIST_INTR_CLEAR, 208 MDP_SSPP_TOP0_OFF+HIST_INTR_EN, 209 MDP_SSPP_TOP0_OFF+HIST_INTR_STATUS 210 }, 211 { 212 MDP_INTF_0_OFF+INTF_INTR_CLEAR, 213 MDP_INTF_0_OFF+INTF_INTR_EN, 214 MDP_INTF_0_OFF+INTF_INTR_STATUS 215 }, 216 { 217 MDP_INTF_1_OFF+INTF_INTR_CLEAR, 218 MDP_INTF_1_OFF+INTF_INTR_EN, 219 MDP_INTF_1_OFF+INTF_INTR_STATUS 220 }, 221 { 222 MDP_INTF_2_OFF+INTF_INTR_CLEAR, 223 MDP_INTF_2_OFF+INTF_INTR_EN, 224 MDP_INTF_2_OFF+INTF_INTR_STATUS 225 }, 226 { 227 MDP_INTF_3_OFF+INTF_INTR_CLEAR, 228 MDP_INTF_3_OFF+INTF_INTR_EN, 229 MDP_INTF_3_OFF+INTF_INTR_STATUS 230 }, 231 { 232 MDP_INTF_4_OFF+INTF_INTR_CLEAR, 233 MDP_INTF_4_OFF+INTF_INTR_EN, 234 MDP_INTF_4_OFF+INTF_INTR_STATUS 235 }, 236 { 237 MDP_AD4_0_OFF + MDP_AD4_INTR_CLEAR_OFF, 238 MDP_AD4_0_OFF + MDP_AD4_INTR_EN_OFF, 239 MDP_AD4_0_OFF + MDP_AD4_INTR_STATUS_OFF, 240 }, 241 { 242 MDP_AD4_1_OFF + MDP_AD4_INTR_CLEAR_OFF, 243 MDP_AD4_1_OFF + MDP_AD4_INTR_EN_OFF, 244 MDP_AD4_1_OFF + MDP_AD4_INTR_STATUS_OFF, 245 } 246 }; 247 248 /* 249 * struct dpu_irq_type - IRQ mapping table use for lookup an irq_idx in this 250 * table that have a matching interface type and 251 * instance index. 252 */ 253 static const struct dpu_irq_type dpu_irq_map[] = { 254 /* BEGIN MAP_RANGE: 0-31, INTR */ 255 /* irq_idx: 0-3 */ 256 { DPU_IRQ_TYPE_WB_ROT_COMP, WB_0, DPU_INTR_WB_0_DONE, 0}, 257 { DPU_IRQ_TYPE_WB_ROT_COMP, WB_1, DPU_INTR_WB_1_DONE, 0}, 258 { DPU_IRQ_TYPE_WD_TIMER, WD_TIMER_0, DPU_INTR_WD_TIMER_0_DONE, 0}, 259 { DPU_IRQ_TYPE_WD_TIMER, WD_TIMER_1, DPU_INTR_WD_TIMER_1_DONE, 0}, 260 /* irq_idx: 4-7 */ 261 { DPU_IRQ_TYPE_WB_WFD_COMP, WB_2, DPU_INTR_WB_2_DONE, 0}, 262 { DPU_IRQ_TYPE_WD_TIMER, WD_TIMER_2, DPU_INTR_WD_TIMER_2_DONE, 0}, 263 { DPU_IRQ_TYPE_WD_TIMER, WD_TIMER_3, DPU_INTR_WD_TIMER_3_DONE, 0}, 264 { DPU_IRQ_TYPE_WD_TIMER, WD_TIMER_4, DPU_INTR_WD_TIMER_4_DONE, 0}, 265 /* irq_idx: 8-11 */ 266 { DPU_IRQ_TYPE_PING_PONG_COMP, PINGPONG_0, 267 DPU_INTR_PING_PONG_0_DONE, 0}, 268 { DPU_IRQ_TYPE_PING_PONG_COMP, PINGPONG_1, 269 DPU_INTR_PING_PONG_1_DONE, 0}, 270 { DPU_IRQ_TYPE_PING_PONG_COMP, PINGPONG_2, 271 DPU_INTR_PING_PONG_2_DONE, 0}, 272 { DPU_IRQ_TYPE_PING_PONG_COMP, PINGPONG_3, 273 DPU_INTR_PING_PONG_3_DONE, 0}, 274 /* irq_idx: 12-15 */ 275 { DPU_IRQ_TYPE_PING_PONG_RD_PTR, PINGPONG_0, 276 DPU_INTR_PING_PONG_0_RD_PTR, 0}, 277 { DPU_IRQ_TYPE_PING_PONG_RD_PTR, PINGPONG_1, 278 DPU_INTR_PING_PONG_1_RD_PTR, 0}, 279 { DPU_IRQ_TYPE_PING_PONG_RD_PTR, PINGPONG_2, 280 DPU_INTR_PING_PONG_2_RD_PTR, 0}, 281 { DPU_IRQ_TYPE_PING_PONG_RD_PTR, PINGPONG_3, 282 DPU_INTR_PING_PONG_3_RD_PTR, 0}, 283 /* irq_idx: 16-19 */ 284 { DPU_IRQ_TYPE_PING_PONG_WR_PTR, PINGPONG_0, 285 DPU_INTR_PING_PONG_0_WR_PTR, 0}, 286 { DPU_IRQ_TYPE_PING_PONG_WR_PTR, PINGPONG_1, 287 DPU_INTR_PING_PONG_1_WR_PTR, 0}, 288 { DPU_IRQ_TYPE_PING_PONG_WR_PTR, PINGPONG_2, 289 DPU_INTR_PING_PONG_2_WR_PTR, 0}, 290 { DPU_IRQ_TYPE_PING_PONG_WR_PTR, PINGPONG_3, 291 DPU_INTR_PING_PONG_3_WR_PTR, 0}, 292 /* irq_idx: 20-23 */ 293 { DPU_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_0, 294 DPU_INTR_PING_PONG_0_AUTOREFRESH_DONE, 0}, 295 { DPU_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_1, 296 DPU_INTR_PING_PONG_1_AUTOREFRESH_DONE, 0}, 297 { DPU_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_2, 298 DPU_INTR_PING_PONG_2_AUTOREFRESH_DONE, 0}, 299 { DPU_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_3, 300 DPU_INTR_PING_PONG_3_AUTOREFRESH_DONE, 0}, 301 /* irq_idx: 24-27 */ 302 { DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_0, DPU_INTR_INTF_0_UNDERRUN, 0}, 303 { DPU_IRQ_TYPE_INTF_VSYNC, INTF_0, DPU_INTR_INTF_0_VSYNC, 0}, 304 { DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_1, DPU_INTR_INTF_1_UNDERRUN, 0}, 305 { DPU_IRQ_TYPE_INTF_VSYNC, INTF_1, DPU_INTR_INTF_1_VSYNC, 0}, 306 /* irq_idx: 28-31 */ 307 { DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_2, DPU_INTR_INTF_2_UNDERRUN, 0}, 308 { DPU_IRQ_TYPE_INTF_VSYNC, INTF_2, DPU_INTR_INTF_2_VSYNC, 0}, 309 { DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_3, DPU_INTR_INTF_3_UNDERRUN, 0}, 310 { DPU_IRQ_TYPE_INTF_VSYNC, INTF_3, DPU_INTR_INTF_3_VSYNC, 0}, 311 312 /* BEGIN MAP_RANGE: 32-64, INTR2 */ 313 /* irq_idx: 32-35 */ 314 { DPU_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_S0, 315 DPU_INTR_PING_PONG_S0_AUTOREFRESH_DONE, 1}, 316 { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, 317 { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, 318 { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, 319 /* irq_idx: 36-39 */ 320 { DPU_IRQ_TYPE_PING_PONG_WR_PTR, PINGPONG_S0, 321 DPU_INTR_PING_PONG_S0_WR_PTR, 1}, 322 { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, 323 { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, 324 { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, 325 /* irq_idx: 40 */ 326 { DPU_IRQ_TYPE_PING_PONG_RD_PTR, PINGPONG_S0, 327 DPU_INTR_PING_PONG_S0_RD_PTR, 1}, 328 /* irq_idx: 41-45 */ 329 { DPU_IRQ_TYPE_CTL_START, CTL_0, 330 DPU_INTR_CTL_0_START, 1}, 331 { DPU_IRQ_TYPE_CTL_START, CTL_1, 332 DPU_INTR_CTL_1_START, 1}, 333 { DPU_IRQ_TYPE_CTL_START, CTL_2, 334 DPU_INTR_CTL_2_START, 1}, 335 { DPU_IRQ_TYPE_CTL_START, CTL_3, 336 DPU_INTR_CTL_3_START, 1}, 337 { DPU_IRQ_TYPE_CTL_START, CTL_4, 338 DPU_INTR_CTL_4_START, 1}, 339 /* irq_idx: 46-47 */ 340 { DPU_IRQ_TYPE_CWB_OVERFLOW, CWB_2, DPU_INTR_CWB_2_OVERFLOW, 1}, 341 { DPU_IRQ_TYPE_CWB_OVERFLOW, CWB_3, DPU_INTR_CWB_3_OVERFLOW, 1}, 342 /* irq_idx: 48-51 */ 343 { DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_0, 344 DPU_INTR_PING_PONG_0_TEAR_DETECTED, 1}, 345 { DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_1, 346 DPU_INTR_PING_PONG_1_TEAR_DETECTED, 1}, 347 { DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_2, 348 DPU_INTR_PING_PONG_2_TEAR_DETECTED, 1}, 349 { DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_3, 350 DPU_INTR_PING_PONG_3_TEAR_DETECTED, 1}, 351 /* irq_idx: 52-55 */ 352 { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, 353 { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, 354 { DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_S0, 355 DPU_INTR_PING_PONG_S0_TEAR_DETECTED, 1}, 356 { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, 357 /* irq_idx: 56-59 */ 358 { DPU_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_0, 359 DPU_INTR_PING_PONG_0_TE_DETECTED, 1}, 360 { DPU_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_1, 361 DPU_INTR_PING_PONG_1_TE_DETECTED, 1}, 362 { DPU_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_2, 363 DPU_INTR_PING_PONG_2_TE_DETECTED, 1}, 364 { DPU_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_3, 365 DPU_INTR_PING_PONG_3_TE_DETECTED, 1}, 366 /* irq_idx: 60-63 */ 367 { DPU_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_S0, 368 DPU_INTR_PING_PONG_S0_TE_DETECTED, 1}, 369 { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, 370 { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, 371 { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, 372 373 /* BEGIN MAP_RANGE: 64-95 HIST */ 374 /* irq_idx: 64-67 */ 375 { DPU_IRQ_TYPE_HIST_VIG_DONE, SSPP_VIG0, DPU_INTR_HIST_VIG_0_DONE, 2}, 376 { DPU_IRQ_TYPE_HIST_VIG_RSTSEQ, SSPP_VIG0, 377 DPU_INTR_HIST_VIG_0_RSTSEQ_DONE, 2}, 378 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 379 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 380 /* irq_idx: 68-71 */ 381 { DPU_IRQ_TYPE_HIST_VIG_DONE, SSPP_VIG1, DPU_INTR_HIST_VIG_1_DONE, 2}, 382 { DPU_IRQ_TYPE_HIST_VIG_RSTSEQ, SSPP_VIG1, 383 DPU_INTR_HIST_VIG_1_RSTSEQ_DONE, 2}, 384 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 385 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 386 /* irq_idx: 72-75 */ 387 { DPU_IRQ_TYPE_HIST_VIG_DONE, SSPP_VIG2, DPU_INTR_HIST_VIG_2_DONE, 2}, 388 { DPU_IRQ_TYPE_HIST_VIG_RSTSEQ, SSPP_VIG2, 389 DPU_INTR_HIST_VIG_2_RSTSEQ_DONE, 2}, 390 { DPU_IRQ_TYPE_HIST_VIG_DONE, SSPP_VIG3, DPU_INTR_HIST_VIG_3_DONE, 2}, 391 { DPU_IRQ_TYPE_HIST_VIG_RSTSEQ, SSPP_VIG3, 392 DPU_INTR_HIST_VIG_3_RSTSEQ_DONE, 2}, 393 /* irq_idx: 76-79 */ 394 { DPU_IRQ_TYPE_HIST_DSPP_DONE, DSPP_0, DPU_INTR_HIST_DSPP_0_DONE, 2}, 395 { DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ, DSPP_0, 396 DPU_INTR_HIST_DSPP_0_RSTSEQ_DONE, 2}, 397 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 398 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 399 /* irq_idx: 80-83 */ 400 { DPU_IRQ_TYPE_HIST_DSPP_DONE, DSPP_1, DPU_INTR_HIST_DSPP_1_DONE, 2}, 401 { DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ, DSPP_1, 402 DPU_INTR_HIST_DSPP_1_RSTSEQ_DONE, 2}, 403 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 404 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 405 /* irq_idx: 84-87 */ 406 { DPU_IRQ_TYPE_HIST_DSPP_DONE, DSPP_2, DPU_INTR_HIST_DSPP_2_DONE, 2}, 407 { DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ, DSPP_2, 408 DPU_INTR_HIST_DSPP_2_RSTSEQ_DONE, 2}, 409 { DPU_IRQ_TYPE_HIST_DSPP_DONE, DSPP_3, DPU_INTR_HIST_DSPP_3_DONE, 2}, 410 { DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ, DSPP_3, 411 DPU_INTR_HIST_DSPP_3_RSTSEQ_DONE, 2}, 412 /* irq_idx: 88-91 */ 413 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 414 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 415 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 416 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 417 /* irq_idx: 92-95 */ 418 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 419 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 420 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 421 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 422 423 /* BEGIN MAP_RANGE: 96-127 INTF_0_INTR */ 424 /* irq_idx: 96-99 */ 425 { DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_0, 426 DPU_INTR_VIDEO_INTO_STATIC, 3}, 427 { DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_0, 428 DPU_INTR_VIDEO_OUTOF_STATIC, 3}, 429 { DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_0, 430 DPU_INTR_DSICMD_0_INTO_STATIC, 3}, 431 { DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_0, 432 DPU_INTR_DSICMD_0_OUTOF_STATIC, 3}, 433 /* irq_idx: 100-103 */ 434 { DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_0, 435 DPU_INTR_DSICMD_1_INTO_STATIC, 3}, 436 { DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_0, 437 DPU_INTR_DSICMD_1_OUTOF_STATIC, 3}, 438 { DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_0, 439 DPU_INTR_DSICMD_2_INTO_STATIC, 3}, 440 { DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_0, 441 DPU_INTR_DSICMD_2_OUTOF_STATIC, 3}, 442 /* irq_idx: 104-107 */ 443 { DPU_IRQ_TYPE_PROG_LINE, INTF_0, DPU_INTR_PROG_LINE, 3}, 444 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 445 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 446 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 447 /* irq_idx: 108-111 */ 448 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 449 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 450 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 451 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 452 /* irq_idx: 112-115 */ 453 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 454 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 455 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 456 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 457 /* irq_idx: 116-119 */ 458 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 459 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 460 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 461 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 462 /* irq_idx: 120-123 */ 463 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 464 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 465 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 466 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 467 /* irq_idx: 124-127 */ 468 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 469 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 470 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 471 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 472 473 /* BEGIN MAP_RANGE: 128-159 INTF_1_INTR */ 474 /* irq_idx: 128-131 */ 475 { DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_1, 476 DPU_INTR_VIDEO_INTO_STATIC, 4}, 477 { DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_1, 478 DPU_INTR_VIDEO_OUTOF_STATIC, 4}, 479 { DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_1, 480 DPU_INTR_DSICMD_0_INTO_STATIC, 4}, 481 { DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_1, 482 DPU_INTR_DSICMD_0_OUTOF_STATIC, 4}, 483 /* irq_idx: 132-135 */ 484 { DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_1, 485 DPU_INTR_DSICMD_1_INTO_STATIC, 4}, 486 { DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_1, 487 DPU_INTR_DSICMD_1_OUTOF_STATIC, 4}, 488 { DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_1, 489 DPU_INTR_DSICMD_2_INTO_STATIC, 4}, 490 { DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_1, 491 DPU_INTR_DSICMD_2_OUTOF_STATIC, 4}, 492 /* irq_idx: 136-139 */ 493 { DPU_IRQ_TYPE_PROG_LINE, INTF_1, DPU_INTR_PROG_LINE, 4}, 494 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 495 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 496 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 497 /* irq_idx: 140-143 */ 498 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 499 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 500 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 501 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 502 /* irq_idx: 144-147 */ 503 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 504 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 505 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 506 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 507 /* irq_idx: 148-151 */ 508 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 509 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 510 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 511 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 512 /* irq_idx: 152-155 */ 513 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 514 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 515 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 516 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 517 /* irq_idx: 156-159 */ 518 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 519 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 520 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 521 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 522 523 /* BEGIN MAP_RANGE: 160-191 INTF_2_INTR */ 524 /* irq_idx: 160-163 */ 525 { DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_2, 526 DPU_INTR_VIDEO_INTO_STATIC, 5}, 527 { DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_2, 528 DPU_INTR_VIDEO_OUTOF_STATIC, 5}, 529 { DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_2, 530 DPU_INTR_DSICMD_0_INTO_STATIC, 5}, 531 { DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_2, 532 DPU_INTR_DSICMD_0_OUTOF_STATIC, 5}, 533 /* irq_idx: 164-167 */ 534 { DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_2, 535 DPU_INTR_DSICMD_1_INTO_STATIC, 5}, 536 { DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_2, 537 DPU_INTR_DSICMD_1_OUTOF_STATIC, 5}, 538 { DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_2, 539 DPU_INTR_DSICMD_2_INTO_STATIC, 5}, 540 { DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_2, 541 DPU_INTR_DSICMD_2_OUTOF_STATIC, 5}, 542 /* irq_idx: 168-171 */ 543 { DPU_IRQ_TYPE_PROG_LINE, INTF_2, DPU_INTR_PROG_LINE, 5}, 544 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 545 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 546 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 547 /* irq_idx: 172-175 */ 548 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 549 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 550 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 551 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 552 /* irq_idx: 176-179 */ 553 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 554 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 555 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 556 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 557 /* irq_idx: 180-183 */ 558 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 559 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 560 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 561 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 562 /* irq_idx: 184-187 */ 563 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 564 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 565 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 566 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 567 /* irq_idx: 188-191 */ 568 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 569 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 570 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 571 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 572 573 /* BEGIN MAP_RANGE: 192-223 INTF_3_INTR */ 574 /* irq_idx: 192-195 */ 575 { DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_3, 576 DPU_INTR_VIDEO_INTO_STATIC, 6}, 577 { DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_3, 578 DPU_INTR_VIDEO_OUTOF_STATIC, 6}, 579 { DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_3, 580 DPU_INTR_DSICMD_0_INTO_STATIC, 6}, 581 { DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_3, 582 DPU_INTR_DSICMD_0_OUTOF_STATIC, 6}, 583 /* irq_idx: 196-199 */ 584 { DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_3, 585 DPU_INTR_DSICMD_1_INTO_STATIC, 6}, 586 { DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_3, 587 DPU_INTR_DSICMD_1_OUTOF_STATIC, 6}, 588 { DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_3, 589 DPU_INTR_DSICMD_2_INTO_STATIC, 6}, 590 { DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_3, 591 DPU_INTR_DSICMD_2_OUTOF_STATIC, 6}, 592 /* irq_idx: 200-203 */ 593 { DPU_IRQ_TYPE_PROG_LINE, INTF_3, DPU_INTR_PROG_LINE, 6}, 594 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 595 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 596 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 597 /* irq_idx: 204-207 */ 598 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 599 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 600 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 601 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 602 /* irq_idx: 208-211 */ 603 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 604 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 605 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 606 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 607 /* irq_idx: 212-215 */ 608 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 609 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 610 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 611 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 612 /* irq_idx: 216-219 */ 613 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 614 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 615 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 616 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 617 /* irq_idx: 220-223 */ 618 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 619 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 620 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 621 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 622 623 /* BEGIN MAP_RANGE: 224-255 INTF_4_INTR */ 624 /* irq_idx: 224-227 */ 625 { DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_4, 626 DPU_INTR_VIDEO_INTO_STATIC, 7}, 627 { DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_4, 628 DPU_INTR_VIDEO_OUTOF_STATIC, 7}, 629 { DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_4, 630 DPU_INTR_DSICMD_0_INTO_STATIC, 7}, 631 { DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_4, 632 DPU_INTR_DSICMD_0_OUTOF_STATIC, 7}, 633 /* irq_idx: 228-231 */ 634 { DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_4, 635 DPU_INTR_DSICMD_1_INTO_STATIC, 7}, 636 { DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_4, 637 DPU_INTR_DSICMD_1_OUTOF_STATIC, 7}, 638 { DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_4, 639 DPU_INTR_DSICMD_2_INTO_STATIC, 7}, 640 { DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_4, 641 DPU_INTR_DSICMD_2_OUTOF_STATIC, 7}, 642 /* irq_idx: 232-235 */ 643 { DPU_IRQ_TYPE_PROG_LINE, INTF_4, DPU_INTR_PROG_LINE, 7}, 644 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 645 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 646 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 647 /* irq_idx: 236-239 */ 648 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 649 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 650 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 651 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 652 /* irq_idx: 240-243 */ 653 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 654 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 655 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 656 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 657 /* irq_idx: 244-247 */ 658 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 659 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 660 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 661 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 662 /* irq_idx: 248-251 */ 663 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 664 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 665 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 666 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 667 /* irq_idx: 252-255 */ 668 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 669 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 670 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 671 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 672 673 /* BEGIN MAP_RANGE: 256-287 AD4_0_INTR */ 674 /* irq_idx: 256-259 */ 675 { DPU_IRQ_TYPE_AD4_BL_DONE, DSPP_0, DPU_INTR_BACKLIGHT_UPDATED, 8}, 676 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 677 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 678 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 679 /* irq_idx: 260-263 */ 680 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 681 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 682 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 683 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 684 /* irq_idx: 264-267 */ 685 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 686 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 687 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 688 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 689 /* irq_idx: 268-271 */ 690 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 691 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 692 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 693 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 694 /* irq_idx: 272-275 */ 695 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 696 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 697 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 698 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 699 /* irq_idx: 276-279 */ 700 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 701 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 702 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 703 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 704 /* irq_idx: 280-283 */ 705 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 706 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 707 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 708 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 709 /* irq_idx: 284-287 */ 710 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 711 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 712 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 713 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 714 715 /* BEGIN MAP_RANGE: 288-319 AD4_1_INTR */ 716 /* irq_idx: 288-291 */ 717 { DPU_IRQ_TYPE_AD4_BL_DONE, DSPP_1, DPU_INTR_BACKLIGHT_UPDATED, 9}, 718 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 719 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 720 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 721 /* irq_idx: 292-295 */ 722 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 723 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 724 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 725 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 726 /* irq_idx: 296-299 */ 727 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 728 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 729 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 730 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 731 /* irq_idx: 300-303 */ 732 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 733 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 734 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 735 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 736 /* irq_idx: 304-307 */ 737 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 738 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 739 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 740 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 741 /* irq_idx: 308-311 */ 742 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 743 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 744 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 745 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 746 /* irq_idx: 312-315 */ 747 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 748 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 749 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 750 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 751 /* irq_idx: 315-319 */ 752 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 753 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 754 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 755 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 756 }; 757 758 static int dpu_hw_intr_irqidx_lookup(enum dpu_intr_type intr_type, 759 u32 instance_idx) 760 { 761 int i; 762 763 for (i = 0; i < ARRAY_SIZE(dpu_irq_map); i++) { 764 if (intr_type == dpu_irq_map[i].intr_type && 765 instance_idx == dpu_irq_map[i].instance_idx) 766 return i; 767 } 768 769 pr_debug("IRQ lookup fail!! intr_type=%d, instance_idx=%d\n", 770 intr_type, instance_idx); 771 return -EINVAL; 772 } 773 774 static void dpu_hw_intr_dispatch_irq(struct dpu_hw_intr *intr, 775 void (*cbfunc)(void *, int), 776 void *arg) 777 { 778 int reg_idx; 779 int irq_idx; 780 int start_idx; 781 int end_idx; 782 u32 irq_status; 783 unsigned long irq_flags; 784 785 if (!intr) 786 return; 787 788 /* 789 * The dispatcher will save the IRQ status before calling here. 790 * Now need to go through each IRQ status and find matching 791 * irq lookup index. 792 */ 793 spin_lock_irqsave(&intr->irq_lock, irq_flags); 794 for (reg_idx = 0; reg_idx < ARRAY_SIZE(dpu_intr_set); reg_idx++) { 795 irq_status = intr->save_irq_status[reg_idx]; 796 797 /* 798 * Each Interrupt register has a range of 32 indexes, and 799 * that is static for dpu_irq_map. 800 */ 801 start_idx = reg_idx * 32; 802 end_idx = start_idx + 32; 803 804 if (!test_bit(reg_idx, &intr->irq_mask) || 805 start_idx >= ARRAY_SIZE(dpu_irq_map)) 806 continue; 807 808 /* 809 * Search through matching intr status from irq map. 810 * start_idx and end_idx defined the search range in 811 * the dpu_irq_map. 812 */ 813 for (irq_idx = start_idx; 814 (irq_idx < end_idx) && irq_status; 815 irq_idx++) 816 if ((irq_status & dpu_irq_map[irq_idx].irq_mask) && 817 (dpu_irq_map[irq_idx].reg_idx == reg_idx)) { 818 /* 819 * Once a match on irq mask, perform a callback 820 * to the given cbfunc. cbfunc will take care 821 * the interrupt status clearing. If cbfunc is 822 * not provided, then the interrupt clearing 823 * is here. 824 */ 825 if (cbfunc) 826 cbfunc(arg, irq_idx); 827 else 828 intr->ops.clear_intr_status_nolock( 829 intr, irq_idx); 830 831 /* 832 * When callback finish, clear the irq_status 833 * with the matching mask. Once irq_status 834 * is all cleared, the search can be stopped. 835 */ 836 irq_status &= ~dpu_irq_map[irq_idx].irq_mask; 837 } 838 } 839 spin_unlock_irqrestore(&intr->irq_lock, irq_flags); 840 } 841 842 static int dpu_hw_intr_enable_irq(struct dpu_hw_intr *intr, int irq_idx) 843 { 844 int reg_idx; 845 unsigned long irq_flags; 846 const struct dpu_intr_reg *reg; 847 const struct dpu_irq_type *irq; 848 const char *dbgstr = NULL; 849 uint32_t cache_irq_mask; 850 851 if (!intr) 852 return -EINVAL; 853 854 if (irq_idx < 0 || irq_idx >= ARRAY_SIZE(dpu_irq_map)) { 855 pr_err("invalid IRQ index: [%d]\n", irq_idx); 856 return -EINVAL; 857 } 858 859 irq = &dpu_irq_map[irq_idx]; 860 reg_idx = irq->reg_idx; 861 reg = &dpu_intr_set[reg_idx]; 862 863 spin_lock_irqsave(&intr->irq_lock, irq_flags); 864 cache_irq_mask = intr->cache_irq_mask[reg_idx]; 865 if (cache_irq_mask & irq->irq_mask) { 866 dbgstr = "DPU IRQ already set:"; 867 } else { 868 dbgstr = "DPU IRQ enabled:"; 869 870 cache_irq_mask |= irq->irq_mask; 871 /* Cleaning any pending interrupt */ 872 DPU_REG_WRITE(&intr->hw, reg->clr_off, irq->irq_mask); 873 /* Enabling interrupts with the new mask */ 874 DPU_REG_WRITE(&intr->hw, reg->en_off, cache_irq_mask); 875 876 /* ensure register write goes through */ 877 wmb(); 878 879 intr->cache_irq_mask[reg_idx] = cache_irq_mask; 880 } 881 spin_unlock_irqrestore(&intr->irq_lock, irq_flags); 882 883 pr_debug("%s MASK:0x%.8x, CACHE-MASK:0x%.8x\n", dbgstr, 884 irq->irq_mask, cache_irq_mask); 885 886 return 0; 887 } 888 889 static int dpu_hw_intr_disable_irq_nolock(struct dpu_hw_intr *intr, int irq_idx) 890 { 891 int reg_idx; 892 const struct dpu_intr_reg *reg; 893 const struct dpu_irq_type *irq; 894 const char *dbgstr = NULL; 895 uint32_t cache_irq_mask; 896 897 if (!intr) 898 return -EINVAL; 899 900 if (irq_idx < 0 || irq_idx >= ARRAY_SIZE(dpu_irq_map)) { 901 pr_err("invalid IRQ index: [%d]\n", irq_idx); 902 return -EINVAL; 903 } 904 905 irq = &dpu_irq_map[irq_idx]; 906 reg_idx = irq->reg_idx; 907 reg = &dpu_intr_set[reg_idx]; 908 909 cache_irq_mask = intr->cache_irq_mask[reg_idx]; 910 if ((cache_irq_mask & irq->irq_mask) == 0) { 911 dbgstr = "DPU IRQ is already cleared:"; 912 } else { 913 dbgstr = "DPU IRQ mask disable:"; 914 915 cache_irq_mask &= ~irq->irq_mask; 916 /* Disable interrupts based on the new mask */ 917 DPU_REG_WRITE(&intr->hw, reg->en_off, cache_irq_mask); 918 /* Cleaning any pending interrupt */ 919 DPU_REG_WRITE(&intr->hw, reg->clr_off, irq->irq_mask); 920 921 /* ensure register write goes through */ 922 wmb(); 923 924 intr->cache_irq_mask[reg_idx] = cache_irq_mask; 925 } 926 927 pr_debug("%s MASK:0x%.8x, CACHE-MASK:0x%.8x\n", dbgstr, 928 irq->irq_mask, cache_irq_mask); 929 930 return 0; 931 } 932 933 static int dpu_hw_intr_disable_irq(struct dpu_hw_intr *intr, int irq_idx) 934 { 935 unsigned long irq_flags; 936 937 if (!intr) 938 return -EINVAL; 939 940 if (irq_idx < 0 || irq_idx >= ARRAY_SIZE(dpu_irq_map)) { 941 pr_err("invalid IRQ index: [%d]\n", irq_idx); 942 return -EINVAL; 943 } 944 945 spin_lock_irqsave(&intr->irq_lock, irq_flags); 946 dpu_hw_intr_disable_irq_nolock(intr, irq_idx); 947 spin_unlock_irqrestore(&intr->irq_lock, irq_flags); 948 949 return 0; 950 } 951 952 static int dpu_hw_intr_clear_irqs(struct dpu_hw_intr *intr) 953 { 954 int i; 955 956 if (!intr) 957 return -EINVAL; 958 959 for (i = 0; i < ARRAY_SIZE(dpu_intr_set); i++) { 960 if (test_bit(i, &intr->irq_mask)) 961 DPU_REG_WRITE(&intr->hw, 962 dpu_intr_set[i].clr_off, 0xffffffff); 963 } 964 965 /* ensure register writes go through */ 966 wmb(); 967 968 return 0; 969 } 970 971 static int dpu_hw_intr_disable_irqs(struct dpu_hw_intr *intr) 972 { 973 int i; 974 975 if (!intr) 976 return -EINVAL; 977 978 for (i = 0; i < ARRAY_SIZE(dpu_intr_set); i++) { 979 if (test_bit(i, &intr->irq_mask)) 980 DPU_REG_WRITE(&intr->hw, 981 dpu_intr_set[i].en_off, 0x00000000); 982 } 983 984 /* ensure register writes go through */ 985 wmb(); 986 987 return 0; 988 } 989 990 static void dpu_hw_intr_get_interrupt_statuses(struct dpu_hw_intr *intr) 991 { 992 int i; 993 u32 enable_mask; 994 unsigned long irq_flags; 995 996 if (!intr) 997 return; 998 999 spin_lock_irqsave(&intr->irq_lock, irq_flags); 1000 for (i = 0; i < ARRAY_SIZE(dpu_intr_set); i++) { 1001 if (!test_bit(i, &intr->irq_mask)) 1002 continue; 1003 1004 /* Read interrupt status */ 1005 intr->save_irq_status[i] = DPU_REG_READ(&intr->hw, 1006 dpu_intr_set[i].status_off); 1007 1008 /* Read enable mask */ 1009 enable_mask = DPU_REG_READ(&intr->hw, dpu_intr_set[i].en_off); 1010 1011 /* and clear the interrupt */ 1012 if (intr->save_irq_status[i]) 1013 DPU_REG_WRITE(&intr->hw, dpu_intr_set[i].clr_off, 1014 intr->save_irq_status[i]); 1015 1016 /* Finally update IRQ status based on enable mask */ 1017 intr->save_irq_status[i] &= enable_mask; 1018 } 1019 1020 /* ensure register writes go through */ 1021 wmb(); 1022 1023 spin_unlock_irqrestore(&intr->irq_lock, irq_flags); 1024 } 1025 1026 static void dpu_hw_intr_clear_intr_status_nolock(struct dpu_hw_intr *intr, 1027 int irq_idx) 1028 { 1029 int reg_idx; 1030 1031 if (!intr) 1032 return; 1033 1034 reg_idx = dpu_irq_map[irq_idx].reg_idx; 1035 DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off, 1036 dpu_irq_map[irq_idx].irq_mask); 1037 1038 /* ensure register writes go through */ 1039 wmb(); 1040 } 1041 1042 static u32 dpu_hw_intr_get_interrupt_status(struct dpu_hw_intr *intr, 1043 int irq_idx, bool clear) 1044 { 1045 int reg_idx; 1046 unsigned long irq_flags; 1047 u32 intr_status; 1048 1049 if (!intr) 1050 return 0; 1051 1052 if (irq_idx >= ARRAY_SIZE(dpu_irq_map) || irq_idx < 0) { 1053 pr_err("invalid IRQ index: [%d]\n", irq_idx); 1054 return 0; 1055 } 1056 1057 spin_lock_irqsave(&intr->irq_lock, irq_flags); 1058 1059 reg_idx = dpu_irq_map[irq_idx].reg_idx; 1060 intr_status = DPU_REG_READ(&intr->hw, 1061 dpu_intr_set[reg_idx].status_off) & 1062 dpu_irq_map[irq_idx].irq_mask; 1063 if (intr_status && clear) 1064 DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off, 1065 intr_status); 1066 1067 /* ensure register writes go through */ 1068 wmb(); 1069 1070 spin_unlock_irqrestore(&intr->irq_lock, irq_flags); 1071 1072 return intr_status; 1073 } 1074 1075 static void __setup_intr_ops(struct dpu_hw_intr_ops *ops) 1076 { 1077 ops->irq_idx_lookup = dpu_hw_intr_irqidx_lookup; 1078 ops->enable_irq = dpu_hw_intr_enable_irq; 1079 ops->disable_irq = dpu_hw_intr_disable_irq; 1080 ops->dispatch_irqs = dpu_hw_intr_dispatch_irq; 1081 ops->clear_all_irqs = dpu_hw_intr_clear_irqs; 1082 ops->disable_all_irqs = dpu_hw_intr_disable_irqs; 1083 ops->get_interrupt_statuses = dpu_hw_intr_get_interrupt_statuses; 1084 ops->clear_intr_status_nolock = dpu_hw_intr_clear_intr_status_nolock; 1085 ops->get_interrupt_status = dpu_hw_intr_get_interrupt_status; 1086 } 1087 1088 static void __intr_offset(struct dpu_mdss_cfg *m, 1089 void __iomem *addr, struct dpu_hw_blk_reg_map *hw) 1090 { 1091 hw->base_off = addr; 1092 hw->blk_off = m->mdp[0].base; 1093 hw->hwversion = m->hwversion; 1094 } 1095 1096 struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr, 1097 struct dpu_mdss_cfg *m) 1098 { 1099 struct dpu_hw_intr *intr; 1100 1101 if (!addr || !m) 1102 return ERR_PTR(-EINVAL); 1103 1104 intr = kzalloc(sizeof(*intr), GFP_KERNEL); 1105 if (!intr) 1106 return ERR_PTR(-ENOMEM); 1107 1108 __intr_offset(m, addr, &intr->hw); 1109 __setup_intr_ops(&intr->ops); 1110 1111 intr->irq_idx_tbl_size = ARRAY_SIZE(dpu_irq_map); 1112 1113 intr->cache_irq_mask = kcalloc(ARRAY_SIZE(dpu_intr_set), sizeof(u32), 1114 GFP_KERNEL); 1115 if (intr->cache_irq_mask == NULL) { 1116 kfree(intr); 1117 return ERR_PTR(-ENOMEM); 1118 } 1119 1120 intr->save_irq_status = kcalloc(ARRAY_SIZE(dpu_intr_set), sizeof(u32), 1121 GFP_KERNEL); 1122 if (intr->save_irq_status == NULL) { 1123 kfree(intr->cache_irq_mask); 1124 kfree(intr); 1125 return ERR_PTR(-ENOMEM); 1126 } 1127 1128 intr->irq_mask = m->mdss_irqs; 1129 spin_lock_init(&intr->irq_lock); 1130 1131 return intr; 1132 } 1133 1134 void dpu_hw_intr_destroy(struct dpu_hw_intr *intr) 1135 { 1136 if (intr) { 1137 kfree(intr->cache_irq_mask); 1138 kfree(intr->save_irq_status); 1139 kfree(intr); 1140 } 1141 } 1142 1143