1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright (c) 2020-2022, Linaro Limited */ 3 4 #ifndef _DPU_HW_DSC_H 5 #define _DPU_HW_DSC_H 6 7 #include <drm/display/drm_dsc.h> 8 9 #define DSC_MODE_SPLIT_PANEL BIT(0) 10 #define DSC_MODE_MULTIPLEX BIT(1) 11 #define DSC_MODE_VIDEO BIT(2) 12 13 struct dpu_hw_dsc; 14 15 /** 16 * struct dpu_hw_dsc_ops - interface to the dsc hardware driver functions 17 * Assumption is these functions will be called after clocks are enabled 18 */ 19 struct dpu_hw_dsc_ops { 20 /** 21 * dsc_disable - disable dsc 22 * @hw_dsc: Pointer to dsc context 23 */ 24 void (*dsc_disable)(struct dpu_hw_dsc *hw_dsc); 25 26 /** 27 * dsc_config - configures dsc encoder 28 * @hw_dsc: Pointer to dsc context 29 * @dsc: panel dsc parameters 30 * @mode: dsc topology mode to be set 31 * @initial_lines: amount of initial lines to be used 32 */ 33 void (*dsc_config)(struct dpu_hw_dsc *hw_dsc, 34 struct drm_dsc_config *dsc, 35 u32 mode, 36 u32 initial_lines); 37 38 /** 39 * dsc_config_thresh - programs panel thresholds 40 * @hw_dsc: Pointer to dsc context 41 * @dsc: panel dsc parameters 42 */ 43 void (*dsc_config_thresh)(struct dpu_hw_dsc *hw_dsc, 44 struct drm_dsc_config *dsc); 45 }; 46 47 struct dpu_hw_dsc { 48 struct dpu_hw_blk base; 49 struct dpu_hw_blk_reg_map hw; 50 51 /* dsc */ 52 enum dpu_dsc idx; 53 const struct dpu_dsc_cfg *caps; 54 55 /* ops */ 56 struct dpu_hw_dsc_ops ops; 57 }; 58 59 /** 60 * dpu_hw_dsc_init - initializes the dsc block for the passed dsc idx. 61 * @idx: DSC index for which driver object is required 62 * @addr: Mapped register io address of MDP 63 * @m: Pointer to mdss catalog data 64 * Returns: Error code or allocated dpu_hw_dsc context 65 */ 66 struct dpu_hw_dsc *dpu_hw_dsc_init(enum dpu_dsc idx, void __iomem *addr, 67 const struct dpu_mdss_cfg *m); 68 69 /** 70 * dpu_hw_dsc_destroy - destroys dsc driver context 71 * @dsc: Pointer to dsc driver context returned by dpu_hw_dsc_init 72 */ 73 void dpu_hw_dsc_destroy(struct dpu_hw_dsc *dsc); 74 75 static inline struct dpu_hw_dsc *to_dpu_hw_dsc(struct dpu_hw_blk *hw) 76 { 77 return container_of(hw, struct dpu_hw_dsc, base); 78 } 79 80 #endif /* _DPU_HW_DSC_H */ 81