1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2020-2022, Linaro Limited 4 */ 5 6 #include "dpu_kms.h" 7 #include "dpu_hw_catalog.h" 8 #include "dpu_hwio.h" 9 #include "dpu_hw_mdss.h" 10 #include "dpu_hw_dsc.h" 11 12 #define DSC_COMMON_MODE 0x000 13 #define DSC_ENC 0x004 14 #define DSC_PICTURE 0x008 15 #define DSC_SLICE 0x00C 16 #define DSC_CHUNK_SIZE 0x010 17 #define DSC_DELAY 0x014 18 #define DSC_SCALE_INITIAL 0x018 19 #define DSC_SCALE_DEC_INTERVAL 0x01C 20 #define DSC_SCALE_INC_INTERVAL 0x020 21 #define DSC_FIRST_LINE_BPG_OFFSET 0x024 22 #define DSC_BPG_OFFSET 0x028 23 #define DSC_DSC_OFFSET 0x02C 24 #define DSC_FLATNESS 0x030 25 #define DSC_RC_MODEL_SIZE 0x034 26 #define DSC_RC 0x038 27 #define DSC_RC_BUF_THRESH 0x03C 28 #define DSC_RANGE_MIN_QP 0x074 29 #define DSC_RANGE_MAX_QP 0x0B0 30 #define DSC_RANGE_BPG_OFFSET 0x0EC 31 32 #define DSC_CTL(m) (0x1800 - 0x3FC * (m - DSC_0)) 33 34 static void dpu_hw_dsc_disable(struct dpu_hw_dsc *dsc) 35 { 36 struct dpu_hw_blk_reg_map *c = &dsc->hw; 37 38 DPU_REG_WRITE(c, DSC_COMMON_MODE, 0); 39 } 40 41 static void dpu_hw_dsc_config(struct dpu_hw_dsc *hw_dsc, 42 struct drm_dsc_config *dsc, 43 u32 mode, 44 u32 initial_lines) 45 { 46 struct dpu_hw_blk_reg_map *c = &hw_dsc->hw; 47 u32 data; 48 u32 slice_last_group_size; 49 u32 det_thresh_flatness; 50 bool is_cmd_mode = !(mode & DSC_MODE_VIDEO); 51 52 DPU_REG_WRITE(c, DSC_COMMON_MODE, mode); 53 54 if (is_cmd_mode) 55 initial_lines += 1; 56 57 slice_last_group_size = 3 - (dsc->slice_width % 3); 58 data = (initial_lines << 20); 59 data |= ((slice_last_group_size - 1) << 18); 60 /* bpp is 6.4 format, 4 LSBs bits are for fractional part */ 61 data |= (dsc->bits_per_pixel << 8); 62 data |= (dsc->block_pred_enable << 7); 63 data |= (dsc->line_buf_depth << 3); 64 data |= (dsc->simple_422 << 2); 65 data |= (dsc->convert_rgb << 1); 66 data |= dsc->bits_per_component; 67 68 DPU_REG_WRITE(c, DSC_ENC, data); 69 70 data = dsc->pic_width << 16; 71 data |= dsc->pic_height; 72 DPU_REG_WRITE(c, DSC_PICTURE, data); 73 74 data = dsc->slice_width << 16; 75 data |= dsc->slice_height; 76 DPU_REG_WRITE(c, DSC_SLICE, data); 77 78 data = dsc->slice_chunk_size << 16; 79 DPU_REG_WRITE(c, DSC_CHUNK_SIZE, data); 80 81 data = dsc->initial_dec_delay << 16; 82 data |= dsc->initial_xmit_delay; 83 DPU_REG_WRITE(c, DSC_DELAY, data); 84 85 data = dsc->initial_scale_value; 86 DPU_REG_WRITE(c, DSC_SCALE_INITIAL, data); 87 88 data = dsc->scale_decrement_interval; 89 DPU_REG_WRITE(c, DSC_SCALE_DEC_INTERVAL, data); 90 91 data = dsc->scale_increment_interval; 92 DPU_REG_WRITE(c, DSC_SCALE_INC_INTERVAL, data); 93 94 data = dsc->first_line_bpg_offset; 95 DPU_REG_WRITE(c, DSC_FIRST_LINE_BPG_OFFSET, data); 96 97 data = dsc->nfl_bpg_offset << 16; 98 data |= dsc->slice_bpg_offset; 99 DPU_REG_WRITE(c, DSC_BPG_OFFSET, data); 100 101 data = dsc->initial_offset << 16; 102 data |= dsc->final_offset; 103 DPU_REG_WRITE(c, DSC_DSC_OFFSET, data); 104 105 det_thresh_flatness = 7 + 2 * (dsc->bits_per_component - 8); 106 data = det_thresh_flatness << 10; 107 data |= dsc->flatness_max_qp << 5; 108 data |= dsc->flatness_min_qp; 109 DPU_REG_WRITE(c, DSC_FLATNESS, data); 110 111 data = dsc->rc_model_size; 112 DPU_REG_WRITE(c, DSC_RC_MODEL_SIZE, data); 113 114 data = dsc->rc_tgt_offset_low << 18; 115 data |= dsc->rc_tgt_offset_high << 14; 116 data |= dsc->rc_quant_incr_limit1 << 9; 117 data |= dsc->rc_quant_incr_limit0 << 4; 118 data |= dsc->rc_edge_factor; 119 DPU_REG_WRITE(c, DSC_RC, data); 120 } 121 122 static void dpu_hw_dsc_config_thresh(struct dpu_hw_dsc *hw_dsc, 123 struct drm_dsc_config *dsc) 124 { 125 struct drm_dsc_rc_range_parameters *rc = dsc->rc_range_params; 126 struct dpu_hw_blk_reg_map *c = &hw_dsc->hw; 127 u32 off; 128 int i; 129 130 off = DSC_RC_BUF_THRESH; 131 for (i = 0; i < DSC_NUM_BUF_RANGES - 1 ; i++) { 132 DPU_REG_WRITE(c, off, dsc->rc_buf_thresh[i]); 133 off += 4; 134 } 135 136 off = DSC_RANGE_MIN_QP; 137 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { 138 DPU_REG_WRITE(c, off, rc[i].range_min_qp); 139 off += 4; 140 } 141 142 off = DSC_RANGE_MAX_QP; 143 for (i = 0; i < 15; i++) { 144 DPU_REG_WRITE(c, off, rc[i].range_max_qp); 145 off += 4; 146 } 147 148 off = DSC_RANGE_BPG_OFFSET; 149 for (i = 0; i < 15; i++) { 150 DPU_REG_WRITE(c, off, rc[i].range_bpg_offset); 151 off += 4; 152 } 153 } 154 155 static void dpu_hw_dsc_bind_pingpong_blk( 156 struct dpu_hw_dsc *hw_dsc, 157 bool enable, 158 const enum dpu_pingpong pp) 159 { 160 struct dpu_hw_blk_reg_map *c = &hw_dsc->hw; 161 int mux_cfg = 0xF; 162 u32 dsc_ctl_offset; 163 164 dsc_ctl_offset = DSC_CTL(hw_dsc->idx); 165 166 if (enable) 167 mux_cfg = (pp - PINGPONG_0) & 0x7; 168 169 DRM_DEBUG_KMS("%s dsc:%d %s pp:%d\n", 170 enable ? "Binding" : "Unbinding", 171 hw_dsc->idx - DSC_0, 172 enable ? "to" : "from", 173 pp - PINGPONG_0); 174 175 DPU_REG_WRITE(c, dsc_ctl_offset, mux_cfg); 176 } 177 178 static struct dpu_dsc_cfg *_dsc_offset(enum dpu_dsc dsc, 179 const struct dpu_mdss_cfg *m, 180 void __iomem *addr, 181 struct dpu_hw_blk_reg_map *b) 182 { 183 int i; 184 185 for (i = 0; i < m->dsc_count; i++) { 186 if (dsc == m->dsc[i].id) { 187 b->blk_addr = addr + m->dsc[i].base; 188 b->log_mask = DPU_DBG_MASK_DSC; 189 return &m->dsc[i]; 190 } 191 } 192 193 return NULL; 194 } 195 196 static void _setup_dsc_ops(struct dpu_hw_dsc_ops *ops, 197 unsigned long cap) 198 { 199 ops->dsc_disable = dpu_hw_dsc_disable; 200 ops->dsc_config = dpu_hw_dsc_config; 201 ops->dsc_config_thresh = dpu_hw_dsc_config_thresh; 202 if (cap & BIT(DPU_DSC_OUTPUT_CTRL)) 203 ops->dsc_bind_pingpong_blk = dpu_hw_dsc_bind_pingpong_blk; 204 }; 205 206 struct dpu_hw_dsc *dpu_hw_dsc_init(enum dpu_dsc idx, void __iomem *addr, 207 const struct dpu_mdss_cfg *m) 208 { 209 struct dpu_hw_dsc *c; 210 struct dpu_dsc_cfg *cfg; 211 212 c = kzalloc(sizeof(*c), GFP_KERNEL); 213 if (!c) 214 return ERR_PTR(-ENOMEM); 215 216 cfg = _dsc_offset(idx, m, addr, &c->hw); 217 if (IS_ERR_OR_NULL(cfg)) { 218 kfree(c); 219 return ERR_PTR(-EINVAL); 220 } 221 222 c->idx = idx; 223 c->caps = cfg; 224 _setup_dsc_ops(&c->ops, c->caps->features); 225 226 return c; 227 } 228 229 void dpu_hw_dsc_destroy(struct dpu_hw_dsc *dsc) 230 { 231 kfree(dsc); 232 } 233