1 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 2 * 3 * This program is free software; you can redistribute it and/or modify 4 * it under the terms of the GNU General Public License version 2 and 5 * only version 2 as published by the Free Software Foundation. 6 * 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 */ 12 13 #ifndef _DPU_HW_CTL_H 14 #define _DPU_HW_CTL_H 15 16 #include "dpu_hw_mdss.h" 17 #include "dpu_hw_util.h" 18 #include "dpu_hw_catalog.h" 19 #include "dpu_hw_sspp.h" 20 #include "dpu_hw_blk.h" 21 22 /** 23 * dpu_ctl_mode_sel: Interface mode selection 24 * DPU_CTL_MODE_SEL_VID: Video mode interface 25 * DPU_CTL_MODE_SEL_CMD: Command mode interface 26 */ 27 enum dpu_ctl_mode_sel { 28 DPU_CTL_MODE_SEL_VID = 0, 29 DPU_CTL_MODE_SEL_CMD 30 }; 31 32 struct dpu_hw_ctl; 33 /** 34 * struct dpu_hw_stage_cfg - blending stage cfg 35 * @stage : SSPP_ID at each stage 36 * @multirect_index: index of the rectangle of SSPP. 37 */ 38 struct dpu_hw_stage_cfg { 39 enum dpu_sspp stage[DPU_STAGE_MAX][PIPES_PER_STAGE]; 40 enum dpu_sspp_multirect_index multirect_index 41 [DPU_STAGE_MAX][PIPES_PER_STAGE]; 42 }; 43 44 /** 45 * struct dpu_hw_intf_cfg :Describes how the DPU writes data to output interface 46 * @intf : Interface id 47 * @mode_3d: 3d mux configuration 48 * @intf_mode_sel: Interface mode, cmd / vid 49 * @stream_sel: Stream selection for multi-stream interfaces 50 */ 51 struct dpu_hw_intf_cfg { 52 enum dpu_intf intf; 53 enum dpu_3d_blend_mode mode_3d; 54 enum dpu_ctl_mode_sel intf_mode_sel; 55 int stream_sel; 56 }; 57 58 /** 59 * struct dpu_hw_ctl_ops - Interface to the wb Hw driver functions 60 * Assumption is these functions will be called after clocks are enabled 61 */ 62 struct dpu_hw_ctl_ops { 63 /** 64 * kickoff hw operation for Sw controlled interfaces 65 * DSI cmd mode and WB interface are SW controlled 66 * @ctx : ctl path ctx pointer 67 */ 68 void (*trigger_start)(struct dpu_hw_ctl *ctx); 69 70 /** 71 * kickoff prepare is in progress hw operation for sw 72 * controlled interfaces: DSI cmd mode and WB interface 73 * are SW controlled 74 * @ctx : ctl path ctx pointer 75 */ 76 void (*trigger_pending)(struct dpu_hw_ctl *ctx); 77 78 /** 79 * Clear the value of the cached pending_flush_mask 80 * No effect on hardware 81 * @ctx : ctl path ctx pointer 82 */ 83 void (*clear_pending_flush)(struct dpu_hw_ctl *ctx); 84 85 /** 86 * Query the value of the cached pending_flush_mask 87 * No effect on hardware 88 * @ctx : ctl path ctx pointer 89 */ 90 u32 (*get_pending_flush)(struct dpu_hw_ctl *ctx); 91 92 /** 93 * OR in the given flushbits to the cached pending_flush_mask 94 * No effect on hardware 95 * @ctx : ctl path ctx pointer 96 * @flushbits : module flushmask 97 */ 98 void (*update_pending_flush)(struct dpu_hw_ctl *ctx, 99 u32 flushbits); 100 101 /** 102 * Write the value of the pending_flush_mask to hardware 103 * @ctx : ctl path ctx pointer 104 */ 105 void (*trigger_flush)(struct dpu_hw_ctl *ctx); 106 107 /** 108 * Read the value of the flush register 109 * @ctx : ctl path ctx pointer 110 * @Return: value of the ctl flush register. 111 */ 112 u32 (*get_flush_register)(struct dpu_hw_ctl *ctx); 113 114 /** 115 * Setup ctl_path interface config 116 * @ctx 117 * @cfg : interface config structure pointer 118 */ 119 void (*setup_intf_cfg)(struct dpu_hw_ctl *ctx, 120 struct dpu_hw_intf_cfg *cfg); 121 122 int (*reset)(struct dpu_hw_ctl *c); 123 124 /* 125 * wait_reset_status - checks ctl reset status 126 * @ctx : ctl path ctx pointer 127 * 128 * This function checks the ctl reset status bit. 129 * If the reset bit is set, it keeps polling the status till the hw 130 * reset is complete. 131 * Returns: 0 on success or -error if reset incomplete within interval 132 */ 133 int (*wait_reset_status)(struct dpu_hw_ctl *ctx); 134 135 uint32_t (*get_bitmask_sspp)(struct dpu_hw_ctl *ctx, 136 enum dpu_sspp blk); 137 138 uint32_t (*get_bitmask_mixer)(struct dpu_hw_ctl *ctx, 139 enum dpu_lm blk); 140 141 int (*get_bitmask_intf)(struct dpu_hw_ctl *ctx, 142 u32 *flushbits, 143 enum dpu_intf blk); 144 145 /** 146 * Set all blend stages to disabled 147 * @ctx : ctl path ctx pointer 148 */ 149 void (*clear_all_blendstages)(struct dpu_hw_ctl *ctx); 150 151 /** 152 * Configure layer mixer to pipe configuration 153 * @ctx : ctl path ctx pointer 154 * @lm : layer mixer enumeration 155 * @cfg : blend stage configuration 156 */ 157 void (*setup_blendstage)(struct dpu_hw_ctl *ctx, 158 enum dpu_lm lm, struct dpu_hw_stage_cfg *cfg); 159 }; 160 161 /** 162 * struct dpu_hw_ctl : CTL PATH driver object 163 * @base: hardware block base structure 164 * @hw: block register map object 165 * @idx: control path index 166 * @caps: control path capabilities 167 * @mixer_count: number of mixers 168 * @mixer_hw_caps: mixer hardware capabilities 169 * @pending_flush_mask: storage for pending ctl_flush managed via ops 170 * @ops: operation list 171 */ 172 struct dpu_hw_ctl { 173 struct dpu_hw_blk base; 174 struct dpu_hw_blk_reg_map hw; 175 176 /* ctl path */ 177 int idx; 178 const struct dpu_ctl_cfg *caps; 179 int mixer_count; 180 const struct dpu_lm_cfg *mixer_hw_caps; 181 u32 pending_flush_mask; 182 183 /* ops */ 184 struct dpu_hw_ctl_ops ops; 185 }; 186 187 /** 188 * dpu_hw_ctl - convert base object dpu_hw_base to container 189 * @hw: Pointer to base hardware block 190 * return: Pointer to hardware block container 191 */ 192 static inline struct dpu_hw_ctl *to_dpu_hw_ctl(struct dpu_hw_blk *hw) 193 { 194 return container_of(hw, struct dpu_hw_ctl, base); 195 } 196 197 /** 198 * dpu_hw_ctl_init(): Initializes the ctl_path hw driver object. 199 * should be called before accessing every ctl path registers. 200 * @idx: ctl_path index for which driver object is required 201 * @addr: mapped register io address of MDP 202 * @m : pointer to mdss catalog data 203 */ 204 struct dpu_hw_ctl *dpu_hw_ctl_init(enum dpu_ctl idx, 205 void __iomem *addr, 206 struct dpu_mdss_cfg *m); 207 208 /** 209 * dpu_hw_ctl_destroy(): Destroys ctl driver context 210 * should be called to free the context 211 */ 212 void dpu_hw_ctl_destroy(struct dpu_hw_ctl *ctx); 213 214 #endif /*_DPU_HW_CTL_H */ 215