1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
3  */
4 
5 #ifndef _DPU_HW_CTL_H
6 #define _DPU_HW_CTL_H
7 
8 #include "dpu_hw_mdss.h"
9 #include "dpu_hw_util.h"
10 #include "dpu_hw_catalog.h"
11 #include "dpu_hw_sspp.h"
12 #include "dpu_hw_blk.h"
13 
14 /**
15  * dpu_ctl_mode_sel: Interface mode selection
16  * DPU_CTL_MODE_SEL_VID:    Video mode interface
17  * DPU_CTL_MODE_SEL_CMD:    Command mode interface
18  */
19 enum dpu_ctl_mode_sel {
20 	DPU_CTL_MODE_SEL_VID = 0,
21 	DPU_CTL_MODE_SEL_CMD
22 };
23 
24 struct dpu_hw_ctl;
25 /**
26  * struct dpu_hw_stage_cfg - blending stage cfg
27  * @stage : SSPP_ID at each stage
28  * @multirect_index: index of the rectangle of SSPP.
29  */
30 struct dpu_hw_stage_cfg {
31 	enum dpu_sspp stage[DPU_STAGE_MAX][PIPES_PER_STAGE];
32 	enum dpu_sspp_multirect_index multirect_index
33 					[DPU_STAGE_MAX][PIPES_PER_STAGE];
34 };
35 
36 /**
37  * struct dpu_hw_intf_cfg :Describes how the DPU writes data to output interface
38  * @intf :                 Interface id
39  * @mode_3d:               3d mux configuration
40  * @merge_3d:              3d merge block used
41  * @intf_mode_sel:         Interface mode, cmd / vid
42  * @stream_sel:            Stream selection for multi-stream interfaces
43  */
44 struct dpu_hw_intf_cfg {
45 	enum dpu_intf intf;
46 	enum dpu_3d_blend_mode mode_3d;
47 	enum dpu_merge_3d merge_3d;
48 	enum dpu_ctl_mode_sel intf_mode_sel;
49 	int stream_sel;
50 };
51 
52 /**
53  * struct dpu_hw_ctl_ops - Interface to the wb Hw driver functions
54  * Assumption is these functions will be called after clocks are enabled
55  */
56 struct dpu_hw_ctl_ops {
57 	/**
58 	 * kickoff hw operation for Sw controlled interfaces
59 	 * DSI cmd mode and WB interface are SW controlled
60 	 * @ctx       : ctl path ctx pointer
61 	 */
62 	void (*trigger_start)(struct dpu_hw_ctl *ctx);
63 
64 	/**
65 	 * kickoff prepare is in progress hw operation for sw
66 	 * controlled interfaces: DSI cmd mode and WB interface
67 	 * are SW controlled
68 	 * @ctx       : ctl path ctx pointer
69 	 */
70 	void (*trigger_pending)(struct dpu_hw_ctl *ctx);
71 
72 	/**
73 	 * Clear the value of the cached pending_flush_mask
74 	 * No effect on hardware
75 	 * @ctx       : ctl path ctx pointer
76 	 */
77 	void (*clear_pending_flush)(struct dpu_hw_ctl *ctx);
78 
79 	/**
80 	 * Query the value of the cached pending_flush_mask
81 	 * No effect on hardware
82 	 * @ctx       : ctl path ctx pointer
83 	 */
84 	u32 (*get_pending_flush)(struct dpu_hw_ctl *ctx);
85 
86 	/**
87 	 * OR in the given flushbits to the cached pending_flush_mask
88 	 * No effect on hardware
89 	 * @ctx       : ctl path ctx pointer
90 	 * @flushbits : module flushmask
91 	 */
92 	void (*update_pending_flush)(struct dpu_hw_ctl *ctx,
93 		u32 flushbits);
94 
95 	/**
96 	 * OR in the given flushbits to the cached pending_(intf_)flush_mask
97 	 * No effect on hardware
98 	 * @ctx       : ctl path ctx pointer
99 	 * @blk       : interface block index
100 	 */
101 	void (*update_pending_flush_intf)(struct dpu_hw_ctl *ctx,
102 		enum dpu_intf blk);
103 
104 	/**
105 	 * OR in the given flushbits to the cached pending_(merge_3d_)flush_mask
106 	 * No effect on hardware
107 	 * @ctx       : ctl path ctx pointer
108 	 * @blk       : interface block index
109 	 */
110 	void (*update_pending_flush_merge_3d)(struct dpu_hw_ctl *ctx,
111 		enum dpu_merge_3d blk);
112 
113 	/**
114 	 * Write the value of the pending_flush_mask to hardware
115 	 * @ctx       : ctl path ctx pointer
116 	 */
117 	void (*trigger_flush)(struct dpu_hw_ctl *ctx);
118 
119 	/**
120 	 * Read the value of the flush register
121 	 * @ctx       : ctl path ctx pointer
122 	 * @Return: value of the ctl flush register.
123 	 */
124 	u32 (*get_flush_register)(struct dpu_hw_ctl *ctx);
125 
126 	/**
127 	 * Setup ctl_path interface config
128 	 * @ctx
129 	 * @cfg    : interface config structure pointer
130 	 */
131 	void (*setup_intf_cfg)(struct dpu_hw_ctl *ctx,
132 		struct dpu_hw_intf_cfg *cfg);
133 
134 	int (*reset)(struct dpu_hw_ctl *c);
135 
136 	/*
137 	 * wait_reset_status - checks ctl reset status
138 	 * @ctx       : ctl path ctx pointer
139 	 *
140 	 * This function checks the ctl reset status bit.
141 	 * If the reset bit is set, it keeps polling the status till the hw
142 	 * reset is complete.
143 	 * Returns: 0 on success or -error if reset incomplete within interval
144 	 */
145 	int (*wait_reset_status)(struct dpu_hw_ctl *ctx);
146 
147 	uint32_t (*get_bitmask_sspp)(struct dpu_hw_ctl *ctx,
148 		enum dpu_sspp blk);
149 
150 	uint32_t (*get_bitmask_mixer)(struct dpu_hw_ctl *ctx,
151 		enum dpu_lm blk);
152 
153 	uint32_t (*get_bitmask_dspp)(struct dpu_hw_ctl *ctx,
154 		enum dpu_dspp blk);
155 
156 	/**
157 	 * Set all blend stages to disabled
158 	 * @ctx       : ctl path ctx pointer
159 	 */
160 	void (*clear_all_blendstages)(struct dpu_hw_ctl *ctx);
161 
162 	/**
163 	 * Configure layer mixer to pipe configuration
164 	 * @ctx       : ctl path ctx pointer
165 	 * @lm        : layer mixer enumeration
166 	 * @cfg       : blend stage configuration
167 	 */
168 	void (*setup_blendstage)(struct dpu_hw_ctl *ctx,
169 		enum dpu_lm lm, struct dpu_hw_stage_cfg *cfg);
170 
171 	void (*set_active_pipes)(struct dpu_hw_ctl *ctx,
172 		unsigned long *fetch_active);
173 };
174 
175 /**
176  * struct dpu_hw_ctl : CTL PATH driver object
177  * @base: hardware block base structure
178  * @hw: block register map object
179  * @idx: control path index
180  * @caps: control path capabilities
181  * @mixer_count: number of mixers
182  * @mixer_hw_caps: mixer hardware capabilities
183  * @pending_flush_mask: storage for pending ctl_flush managed via ops
184  * @pending_intf_flush_mask: pending INTF flush
185  * @ops: operation list
186  */
187 struct dpu_hw_ctl {
188 	struct dpu_hw_blk base;
189 	struct dpu_hw_blk_reg_map hw;
190 
191 	/* ctl path */
192 	int idx;
193 	const struct dpu_ctl_cfg *caps;
194 	int mixer_count;
195 	const struct dpu_lm_cfg *mixer_hw_caps;
196 	u32 pending_flush_mask;
197 	u32 pending_intf_flush_mask;
198 	u32 pending_merge_3d_flush_mask;
199 
200 	/* ops */
201 	struct dpu_hw_ctl_ops ops;
202 };
203 
204 /**
205  * dpu_hw_ctl - convert base object dpu_hw_base to container
206  * @hw: Pointer to base hardware block
207  * return: Pointer to hardware block container
208  */
209 static inline struct dpu_hw_ctl *to_dpu_hw_ctl(struct dpu_hw_blk *hw)
210 {
211 	return container_of(hw, struct dpu_hw_ctl, base);
212 }
213 
214 /**
215  * dpu_hw_ctl_init(): Initializes the ctl_path hw driver object.
216  * should be called before accessing every ctl path registers.
217  * @idx:  ctl_path index for which driver object is required
218  * @addr: mapped register io address of MDP
219  * @m :   pointer to mdss catalog data
220  */
221 struct dpu_hw_ctl *dpu_hw_ctl_init(enum dpu_ctl idx,
222 		void __iomem *addr,
223 		const struct dpu_mdss_cfg *m);
224 
225 /**
226  * dpu_hw_ctl_destroy(): Destroys ctl driver context
227  * should be called to free the context
228  */
229 void dpu_hw_ctl_destroy(struct dpu_hw_ctl *ctx);
230 
231 #endif /*_DPU_HW_CTL_H */
232