1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
3  * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
4  */
5 
6 #ifndef _DPU_HW_CTL_H
7 #define _DPU_HW_CTL_H
8 
9 #include "dpu_hw_mdss.h"
10 #include "dpu_hw_util.h"
11 #include "dpu_hw_catalog.h"
12 #include "dpu_hw_sspp.h"
13 
14 /**
15  * dpu_ctl_mode_sel: Interface mode selection
16  * DPU_CTL_MODE_SEL_VID:    Video mode interface
17  * DPU_CTL_MODE_SEL_CMD:    Command mode interface
18  */
19 enum dpu_ctl_mode_sel {
20 	DPU_CTL_MODE_SEL_VID = 0,
21 	DPU_CTL_MODE_SEL_CMD
22 };
23 
24 struct dpu_hw_ctl;
25 /**
26  * struct dpu_hw_stage_cfg - blending stage cfg
27  * @stage : SSPP_ID at each stage
28  * @multirect_index: index of the rectangle of SSPP.
29  */
30 struct dpu_hw_stage_cfg {
31 	enum dpu_sspp stage[DPU_STAGE_MAX][PIPES_PER_STAGE];
32 	enum dpu_sspp_multirect_index multirect_index
33 					[DPU_STAGE_MAX][PIPES_PER_STAGE];
34 };
35 
36 /**
37  * struct dpu_hw_intf_cfg :Describes how the DPU writes data to output interface
38  * @intf :                 Interface id
39  * @mode_3d:               3d mux configuration
40  * @merge_3d:              3d merge block used
41  * @intf_mode_sel:         Interface mode, cmd / vid
42  * @stream_sel:            Stream selection for multi-stream interfaces
43  * @dsc:                   DSC BIT masks used
44  */
45 struct dpu_hw_intf_cfg {
46 	enum dpu_intf intf;
47 	enum dpu_wb wb;
48 	enum dpu_3d_blend_mode mode_3d;
49 	enum dpu_merge_3d merge_3d;
50 	enum dpu_ctl_mode_sel intf_mode_sel;
51 	int stream_sel;
52 	unsigned int dsc;
53 };
54 
55 /**
56  * struct dpu_hw_ctl_ops - Interface to the wb Hw driver functions
57  * Assumption is these functions will be called after clocks are enabled
58  */
59 struct dpu_hw_ctl_ops {
60 	/**
61 	 * kickoff hw operation for Sw controlled interfaces
62 	 * DSI cmd mode and WB interface are SW controlled
63 	 * @ctx       : ctl path ctx pointer
64 	 */
65 	void (*trigger_start)(struct dpu_hw_ctl *ctx);
66 
67 	/**
68 	 * check if the ctl is started
69 	 * @ctx       : ctl path ctx pointer
70 	 * @Return: true if started, false if stopped
71 	 */
72 	bool (*is_started)(struct dpu_hw_ctl *ctx);
73 
74 	/**
75 	 * kickoff prepare is in progress hw operation for sw
76 	 * controlled interfaces: DSI cmd mode and WB interface
77 	 * are SW controlled
78 	 * @ctx       : ctl path ctx pointer
79 	 */
80 	void (*trigger_pending)(struct dpu_hw_ctl *ctx);
81 
82 	/**
83 	 * Clear the value of the cached pending_flush_mask
84 	 * No effect on hardware
85 	 * @ctx       : ctl path ctx pointer
86 	 */
87 	void (*clear_pending_flush)(struct dpu_hw_ctl *ctx);
88 
89 	/**
90 	 * Query the value of the cached pending_flush_mask
91 	 * No effect on hardware
92 	 * @ctx       : ctl path ctx pointer
93 	 */
94 	u32 (*get_pending_flush)(struct dpu_hw_ctl *ctx);
95 
96 	/**
97 	 * OR in the given flushbits to the cached pending_flush_mask
98 	 * No effect on hardware
99 	 * @ctx       : ctl path ctx pointer
100 	 * @flushbits : module flushmask
101 	 */
102 	void (*update_pending_flush)(struct dpu_hw_ctl *ctx,
103 		u32 flushbits);
104 
105 	/**
106 	 * OR in the given flushbits to the cached pending_(wb_)flush_mask
107 	 * No effect on hardware
108 	 * @ctx       : ctl path ctx pointer
109 	 * @blk       : writeback block index
110 	 */
111 	void (*update_pending_flush_wb)(struct dpu_hw_ctl *ctx,
112 		enum dpu_wb blk);
113 
114 	/**
115 	 * OR in the given flushbits to the cached pending_(intf_)flush_mask
116 	 * No effect on hardware
117 	 * @ctx       : ctl path ctx pointer
118 	 * @blk       : interface block index
119 	 */
120 	void (*update_pending_flush_intf)(struct dpu_hw_ctl *ctx,
121 		enum dpu_intf blk);
122 
123 	/**
124 	 * OR in the given flushbits to the cached pending_(merge_3d_)flush_mask
125 	 * No effect on hardware
126 	 * @ctx       : ctl path ctx pointer
127 	 * @blk       : interface block index
128 	 */
129 	void (*update_pending_flush_merge_3d)(struct dpu_hw_ctl *ctx,
130 		enum dpu_merge_3d blk);
131 
132 	/**
133 	 * Write the value of the pending_flush_mask to hardware
134 	 * @ctx       : ctl path ctx pointer
135 	 */
136 	void (*trigger_flush)(struct dpu_hw_ctl *ctx);
137 
138 	/**
139 	 * Read the value of the flush register
140 	 * @ctx       : ctl path ctx pointer
141 	 * @Return: value of the ctl flush register.
142 	 */
143 	u32 (*get_flush_register)(struct dpu_hw_ctl *ctx);
144 
145 	/**
146 	 * Setup ctl_path interface config
147 	 * @ctx
148 	 * @cfg    : interface config structure pointer
149 	 */
150 	void (*setup_intf_cfg)(struct dpu_hw_ctl *ctx,
151 		struct dpu_hw_intf_cfg *cfg);
152 
153 	/**
154 	 * reset ctl_path interface config
155 	 * @ctx    : ctl path ctx pointer
156 	 * @cfg    : interface config structure pointer
157 	 */
158 	void (*reset_intf_cfg)(struct dpu_hw_ctl *ctx,
159 			struct dpu_hw_intf_cfg *cfg);
160 
161 	int (*reset)(struct dpu_hw_ctl *c);
162 
163 	/*
164 	 * wait_reset_status - checks ctl reset status
165 	 * @ctx       : ctl path ctx pointer
166 	 *
167 	 * This function checks the ctl reset status bit.
168 	 * If the reset bit is set, it keeps polling the status till the hw
169 	 * reset is complete.
170 	 * Returns: 0 on success or -error if reset incomplete within interval
171 	 */
172 	int (*wait_reset_status)(struct dpu_hw_ctl *ctx);
173 
174 	uint32_t (*get_bitmask_sspp)(struct dpu_hw_ctl *ctx,
175 		enum dpu_sspp blk);
176 
177 	uint32_t (*get_bitmask_mixer)(struct dpu_hw_ctl *ctx,
178 		enum dpu_lm blk);
179 
180 	uint32_t (*get_bitmask_dspp)(struct dpu_hw_ctl *ctx,
181 		enum dpu_dspp blk);
182 
183 	/**
184 	 * Set all blend stages to disabled
185 	 * @ctx       : ctl path ctx pointer
186 	 */
187 	void (*clear_all_blendstages)(struct dpu_hw_ctl *ctx);
188 
189 	/**
190 	 * Configure layer mixer to pipe configuration
191 	 * @ctx       : ctl path ctx pointer
192 	 * @lm        : layer mixer enumeration
193 	 * @cfg       : blend stage configuration
194 	 */
195 	void (*setup_blendstage)(struct dpu_hw_ctl *ctx,
196 		enum dpu_lm lm, struct dpu_hw_stage_cfg *cfg);
197 
198 	void (*set_active_pipes)(struct dpu_hw_ctl *ctx,
199 		unsigned long *fetch_active);
200 };
201 
202 /**
203  * struct dpu_hw_ctl : CTL PATH driver object
204  * @base: hardware block base structure
205  * @hw: block register map object
206  * @idx: control path index
207  * @caps: control path capabilities
208  * @mixer_count: number of mixers
209  * @mixer_hw_caps: mixer hardware capabilities
210  * @pending_flush_mask: storage for pending ctl_flush managed via ops
211  * @pending_intf_flush_mask: pending INTF flush
212  * @pending_wb_flush_mask: pending WB flush
213  * @ops: operation list
214  */
215 struct dpu_hw_ctl {
216 	struct dpu_hw_blk base;
217 	struct dpu_hw_blk_reg_map hw;
218 
219 	/* ctl path */
220 	int idx;
221 	const struct dpu_ctl_cfg *caps;
222 	int mixer_count;
223 	const struct dpu_lm_cfg *mixer_hw_caps;
224 	u32 pending_flush_mask;
225 	u32 pending_intf_flush_mask;
226 	u32 pending_wb_flush_mask;
227 	u32 pending_merge_3d_flush_mask;
228 
229 	/* ops */
230 	struct dpu_hw_ctl_ops ops;
231 };
232 
233 /**
234  * dpu_hw_ctl - convert base object dpu_hw_base to container
235  * @hw: Pointer to base hardware block
236  * return: Pointer to hardware block container
237  */
238 static inline struct dpu_hw_ctl *to_dpu_hw_ctl(struct dpu_hw_blk *hw)
239 {
240 	return container_of(hw, struct dpu_hw_ctl, base);
241 }
242 
243 /**
244  * dpu_hw_ctl_init(): Initializes the ctl_path hw driver object.
245  * should be called before accessing every ctl path registers.
246  * @idx:  ctl_path index for which driver object is required
247  * @addr: mapped register io address of MDP
248  * @m :   pointer to mdss catalog data
249  */
250 struct dpu_hw_ctl *dpu_hw_ctl_init(enum dpu_ctl idx,
251 		void __iomem *addr,
252 		const struct dpu_mdss_cfg *m);
253 
254 /**
255  * dpu_hw_ctl_destroy(): Destroys ctl driver context
256  * should be called to free the context
257  */
258 void dpu_hw_ctl_destroy(struct dpu_hw_ctl *ctx);
259 
260 #endif /*_DPU_HW_CTL_H */
261