1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 3 */ 4 5 #ifndef _DPU_HW_CTL_H 6 #define _DPU_HW_CTL_H 7 8 #include "dpu_hw_mdss.h" 9 #include "dpu_hw_util.h" 10 #include "dpu_hw_catalog.h" 11 #include "dpu_hw_sspp.h" 12 #include "dpu_hw_blk.h" 13 14 /** 15 * dpu_ctl_mode_sel: Interface mode selection 16 * DPU_CTL_MODE_SEL_VID: Video mode interface 17 * DPU_CTL_MODE_SEL_CMD: Command mode interface 18 */ 19 enum dpu_ctl_mode_sel { 20 DPU_CTL_MODE_SEL_VID = 0, 21 DPU_CTL_MODE_SEL_CMD 22 }; 23 24 struct dpu_hw_ctl; 25 /** 26 * struct dpu_hw_stage_cfg - blending stage cfg 27 * @stage : SSPP_ID at each stage 28 * @multirect_index: index of the rectangle of SSPP. 29 */ 30 struct dpu_hw_stage_cfg { 31 enum dpu_sspp stage[DPU_STAGE_MAX][PIPES_PER_STAGE]; 32 enum dpu_sspp_multirect_index multirect_index 33 [DPU_STAGE_MAX][PIPES_PER_STAGE]; 34 }; 35 36 /** 37 * struct dpu_hw_intf_cfg :Describes how the DPU writes data to output interface 38 * @intf : Interface id 39 * @mode_3d: 3d mux configuration 40 * @intf_mode_sel: Interface mode, cmd / vid 41 * @stream_sel: Stream selection for multi-stream interfaces 42 */ 43 struct dpu_hw_intf_cfg { 44 enum dpu_intf intf; 45 enum dpu_3d_blend_mode mode_3d; 46 enum dpu_ctl_mode_sel intf_mode_sel; 47 int stream_sel; 48 }; 49 50 /** 51 * struct dpu_hw_ctl_ops - Interface to the wb Hw driver functions 52 * Assumption is these functions will be called after clocks are enabled 53 */ 54 struct dpu_hw_ctl_ops { 55 /** 56 * kickoff hw operation for Sw controlled interfaces 57 * DSI cmd mode and WB interface are SW controlled 58 * @ctx : ctl path ctx pointer 59 */ 60 void (*trigger_start)(struct dpu_hw_ctl *ctx); 61 62 /** 63 * kickoff prepare is in progress hw operation for sw 64 * controlled interfaces: DSI cmd mode and WB interface 65 * are SW controlled 66 * @ctx : ctl path ctx pointer 67 */ 68 void (*trigger_pending)(struct dpu_hw_ctl *ctx); 69 70 /** 71 * Clear the value of the cached pending_flush_mask 72 * No effect on hardware 73 * @ctx : ctl path ctx pointer 74 */ 75 void (*clear_pending_flush)(struct dpu_hw_ctl *ctx); 76 77 /** 78 * Query the value of the cached pending_flush_mask 79 * No effect on hardware 80 * @ctx : ctl path ctx pointer 81 */ 82 u32 (*get_pending_flush)(struct dpu_hw_ctl *ctx); 83 84 /** 85 * OR in the given flushbits to the cached pending_flush_mask 86 * No effect on hardware 87 * @ctx : ctl path ctx pointer 88 * @flushbits : module flushmask 89 */ 90 void (*update_pending_flush)(struct dpu_hw_ctl *ctx, 91 u32 flushbits); 92 93 /** 94 * OR in the given flushbits to the cached pending_intf_flush_mask 95 * No effect on hardware 96 * @ctx : ctl path ctx pointer 97 * @flushbits : module flushmask 98 */ 99 void (*update_pending_intf_flush)(struct dpu_hw_ctl *ctx, 100 u32 flushbits); 101 102 /** 103 * Write the value of the pending_flush_mask to hardware 104 * @ctx : ctl path ctx pointer 105 */ 106 void (*trigger_flush)(struct dpu_hw_ctl *ctx); 107 108 /** 109 * Read the value of the flush register 110 * @ctx : ctl path ctx pointer 111 * @Return: value of the ctl flush register. 112 */ 113 u32 (*get_flush_register)(struct dpu_hw_ctl *ctx); 114 115 /** 116 * Setup ctl_path interface config 117 * @ctx 118 * @cfg : interface config structure pointer 119 */ 120 void (*setup_intf_cfg)(struct dpu_hw_ctl *ctx, 121 struct dpu_hw_intf_cfg *cfg); 122 123 int (*reset)(struct dpu_hw_ctl *c); 124 125 /* 126 * wait_reset_status - checks ctl reset status 127 * @ctx : ctl path ctx pointer 128 * 129 * This function checks the ctl reset status bit. 130 * If the reset bit is set, it keeps polling the status till the hw 131 * reset is complete. 132 * Returns: 0 on success or -error if reset incomplete within interval 133 */ 134 int (*wait_reset_status)(struct dpu_hw_ctl *ctx); 135 136 uint32_t (*get_bitmask_sspp)(struct dpu_hw_ctl *ctx, 137 enum dpu_sspp blk); 138 139 uint32_t (*get_bitmask_mixer)(struct dpu_hw_ctl *ctx, 140 enum dpu_lm blk); 141 142 uint32_t (*get_bitmask_dspp)(struct dpu_hw_ctl *ctx, 143 enum dpu_dspp blk); 144 145 /** 146 * Query the value of the intf flush mask 147 * No effect on hardware 148 * @ctx : ctl path ctx pointer 149 */ 150 int (*get_bitmask_intf)(struct dpu_hw_ctl *ctx, 151 u32 *flushbits, 152 enum dpu_intf blk); 153 154 /** 155 * Query the value of the intf active flush mask 156 * No effect on hardware 157 * @ctx : ctl path ctx pointer 158 */ 159 int (*get_bitmask_active_intf)(struct dpu_hw_ctl *ctx, 160 u32 *flushbits, enum dpu_intf blk); 161 162 /** 163 * Set all blend stages to disabled 164 * @ctx : ctl path ctx pointer 165 */ 166 void (*clear_all_blendstages)(struct dpu_hw_ctl *ctx); 167 168 /** 169 * Configure layer mixer to pipe configuration 170 * @ctx : ctl path ctx pointer 171 * @lm : layer mixer enumeration 172 * @cfg : blend stage configuration 173 */ 174 void (*setup_blendstage)(struct dpu_hw_ctl *ctx, 175 enum dpu_lm lm, struct dpu_hw_stage_cfg *cfg); 176 }; 177 178 /** 179 * struct dpu_hw_ctl : CTL PATH driver object 180 * @base: hardware block base structure 181 * @hw: block register map object 182 * @idx: control path index 183 * @caps: control path capabilities 184 * @mixer_count: number of mixers 185 * @mixer_hw_caps: mixer hardware capabilities 186 * @pending_flush_mask: storage for pending ctl_flush managed via ops 187 * @pending_intf_flush_mask: pending INTF flush 188 * @ops: operation list 189 */ 190 struct dpu_hw_ctl { 191 struct dpu_hw_blk base; 192 struct dpu_hw_blk_reg_map hw; 193 194 /* ctl path */ 195 int idx; 196 const struct dpu_ctl_cfg *caps; 197 int mixer_count; 198 const struct dpu_lm_cfg *mixer_hw_caps; 199 u32 pending_flush_mask; 200 u32 pending_intf_flush_mask; 201 202 /* ops */ 203 struct dpu_hw_ctl_ops ops; 204 }; 205 206 /** 207 * dpu_hw_ctl - convert base object dpu_hw_base to container 208 * @hw: Pointer to base hardware block 209 * return: Pointer to hardware block container 210 */ 211 static inline struct dpu_hw_ctl *to_dpu_hw_ctl(struct dpu_hw_blk *hw) 212 { 213 return container_of(hw, struct dpu_hw_ctl, base); 214 } 215 216 /** 217 * dpu_hw_ctl_init(): Initializes the ctl_path hw driver object. 218 * should be called before accessing every ctl path registers. 219 * @idx: ctl_path index for which driver object is required 220 * @addr: mapped register io address of MDP 221 * @m : pointer to mdss catalog data 222 */ 223 struct dpu_hw_ctl *dpu_hw_ctl_init(enum dpu_ctl idx, 224 void __iomem *addr, 225 const struct dpu_mdss_cfg *m); 226 227 /** 228 * dpu_hw_ctl_destroy(): Destroys ctl driver context 229 * should be called to free the context 230 */ 231 void dpu_hw_ctl_destroy(struct dpu_hw_ctl *ctx); 232 233 #endif /*_DPU_HW_CTL_H */ 234