1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
3  * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
4  */
5 
6 #ifndef _DPU_HW_CTL_H
7 #define _DPU_HW_CTL_H
8 
9 #include "dpu_hw_mdss.h"
10 #include "dpu_hw_util.h"
11 #include "dpu_hw_catalog.h"
12 #include "dpu_hw_sspp.h"
13 
14 /**
15  * dpu_ctl_mode_sel: Interface mode selection
16  * DPU_CTL_MODE_SEL_VID:    Video mode interface
17  * DPU_CTL_MODE_SEL_CMD:    Command mode interface
18  */
19 enum dpu_ctl_mode_sel {
20 	DPU_CTL_MODE_SEL_VID = 0,
21 	DPU_CTL_MODE_SEL_CMD
22 };
23 
24 struct dpu_hw_ctl;
25 /**
26  * struct dpu_hw_stage_cfg - blending stage cfg
27  * @stage : SSPP_ID at each stage
28  * @multirect_index: index of the rectangle of SSPP.
29  */
30 struct dpu_hw_stage_cfg {
31 	enum dpu_sspp stage[DPU_STAGE_MAX][PIPES_PER_STAGE];
32 	enum dpu_sspp_multirect_index multirect_index
33 					[DPU_STAGE_MAX][PIPES_PER_STAGE];
34 };
35 
36 /**
37  * struct dpu_hw_intf_cfg :Describes how the DPU writes data to output interface
38  * @intf :                 Interface id
39  * @mode_3d:               3d mux configuration
40  * @merge_3d:              3d merge block used
41  * @intf_mode_sel:         Interface mode, cmd / vid
42  * @stream_sel:            Stream selection for multi-stream interfaces
43  * @dsc:                   DSC BIT masks used
44  */
45 struct dpu_hw_intf_cfg {
46 	enum dpu_intf intf;
47 	enum dpu_wb wb;
48 	enum dpu_3d_blend_mode mode_3d;
49 	enum dpu_merge_3d merge_3d;
50 	enum dpu_ctl_mode_sel intf_mode_sel;
51 	int stream_sel;
52 	unsigned int dsc;
53 };
54 
55 /**
56  * struct dpu_hw_ctl_ops - Interface to the wb Hw driver functions
57  * Assumption is these functions will be called after clocks are enabled
58  */
59 struct dpu_hw_ctl_ops {
60 	/**
61 	 * kickoff hw operation for Sw controlled interfaces
62 	 * DSI cmd mode and WB interface are SW controlled
63 	 * @ctx       : ctl path ctx pointer
64 	 */
65 	void (*trigger_start)(struct dpu_hw_ctl *ctx);
66 
67 	/**
68 	 * check if the ctl is started
69 	 * @ctx       : ctl path ctx pointer
70 	 * @Return: true if started, false if stopped
71 	 */
72 	bool (*is_started)(struct dpu_hw_ctl *ctx);
73 
74 	/**
75 	 * kickoff prepare is in progress hw operation for sw
76 	 * controlled interfaces: DSI cmd mode and WB interface
77 	 * are SW controlled
78 	 * @ctx       : ctl path ctx pointer
79 	 */
80 	void (*trigger_pending)(struct dpu_hw_ctl *ctx);
81 
82 	/**
83 	 * Clear the value of the cached pending_flush_mask
84 	 * No effect on hardware.
85 	 * Required to be implemented.
86 	 * @ctx       : ctl path ctx pointer
87 	 */
88 	void (*clear_pending_flush)(struct dpu_hw_ctl *ctx);
89 
90 	/**
91 	 * Query the value of the cached pending_flush_mask
92 	 * No effect on hardware
93 	 * @ctx       : ctl path ctx pointer
94 	 */
95 	u32 (*get_pending_flush)(struct dpu_hw_ctl *ctx);
96 
97 	/**
98 	 * OR in the given flushbits to the cached pending_flush_mask
99 	 * No effect on hardware
100 	 * @ctx       : ctl path ctx pointer
101 	 * @flushbits : module flushmask
102 	 */
103 	void (*update_pending_flush)(struct dpu_hw_ctl *ctx,
104 		u32 flushbits);
105 
106 	/**
107 	 * OR in the given flushbits to the cached pending_(wb_)flush_mask
108 	 * No effect on hardware
109 	 * @ctx       : ctl path ctx pointer
110 	 * @blk       : writeback block index
111 	 */
112 	void (*update_pending_flush_wb)(struct dpu_hw_ctl *ctx,
113 		enum dpu_wb blk);
114 
115 	/**
116 	 * OR in the given flushbits to the cached pending_(intf_)flush_mask
117 	 * No effect on hardware
118 	 * @ctx       : ctl path ctx pointer
119 	 * @blk       : interface block index
120 	 */
121 	void (*update_pending_flush_intf)(struct dpu_hw_ctl *ctx,
122 		enum dpu_intf blk);
123 
124 	/**
125 	 * OR in the given flushbits to the cached pending_(merge_3d_)flush_mask
126 	 * No effect on hardware
127 	 * @ctx       : ctl path ctx pointer
128 	 * @blk       : interface block index
129 	 */
130 	void (*update_pending_flush_merge_3d)(struct dpu_hw_ctl *ctx,
131 		enum dpu_merge_3d blk);
132 
133 	/**
134 	 * OR in the given flushbits to the cached pending_flush_mask
135 	 * No effect on hardware
136 	 * @ctx       : ctl path ctx pointer
137 	 * @blk       : SSPP block index
138 	 */
139 	void (*update_pending_flush_sspp)(struct dpu_hw_ctl *ctx,
140 		enum dpu_sspp blk);
141 
142 	/**
143 	 * OR in the given flushbits to the cached pending_flush_mask
144 	 * No effect on hardware
145 	 * @ctx       : ctl path ctx pointer
146 	 * @blk       : LM block index
147 	 */
148 	void (*update_pending_flush_mixer)(struct dpu_hw_ctl *ctx,
149 		enum dpu_lm blk);
150 
151 	/**
152 	 * OR in the given flushbits to the cached pending_flush_mask
153 	 * No effect on hardware
154 	 * @ctx       : ctl path ctx pointer
155 	 * @blk       : DSPP block index
156 	 * @dspp_sub_blk : DSPP sub-block index
157 	 */
158 	void (*update_pending_flush_dspp)(struct dpu_hw_ctl *ctx,
159 		enum dpu_dspp blk, u32 dspp_sub_blk);
160 
161 	/**
162 	 * OR in the given flushbits to the cached pending_(dsc_)flush_mask
163 	 * No effect on hardware
164 	 * @ctx: ctl path ctx pointer
165 	 * @blk: interface block index
166 	 */
167 	void (*update_pending_flush_dsc)(struct dpu_hw_ctl *ctx,
168 					 enum dpu_dsc blk);
169 
170 	/**
171 	 * Write the value of the pending_flush_mask to hardware
172 	 * @ctx       : ctl path ctx pointer
173 	 */
174 	void (*trigger_flush)(struct dpu_hw_ctl *ctx);
175 
176 	/**
177 	 * Read the value of the flush register
178 	 * @ctx       : ctl path ctx pointer
179 	 * @Return: value of the ctl flush register.
180 	 */
181 	u32 (*get_flush_register)(struct dpu_hw_ctl *ctx);
182 
183 	/**
184 	 * Setup ctl_path interface config
185 	 * @ctx
186 	 * @cfg    : interface config structure pointer
187 	 */
188 	void (*setup_intf_cfg)(struct dpu_hw_ctl *ctx,
189 		struct dpu_hw_intf_cfg *cfg);
190 
191 	/**
192 	 * reset ctl_path interface config
193 	 * @ctx    : ctl path ctx pointer
194 	 * @cfg    : interface config structure pointer
195 	 */
196 	void (*reset_intf_cfg)(struct dpu_hw_ctl *ctx,
197 			struct dpu_hw_intf_cfg *cfg);
198 
199 	int (*reset)(struct dpu_hw_ctl *c);
200 
201 	/*
202 	 * wait_reset_status - checks ctl reset status
203 	 * @ctx       : ctl path ctx pointer
204 	 *
205 	 * This function checks the ctl reset status bit.
206 	 * If the reset bit is set, it keeps polling the status till the hw
207 	 * reset is complete.
208 	 * Returns: 0 on success or -error if reset incomplete within interval
209 	 */
210 	int (*wait_reset_status)(struct dpu_hw_ctl *ctx);
211 
212 	/**
213 	 * Set all blend stages to disabled
214 	 * @ctx       : ctl path ctx pointer
215 	 */
216 	void (*clear_all_blendstages)(struct dpu_hw_ctl *ctx);
217 
218 	/**
219 	 * Configure layer mixer to pipe configuration
220 	 * @ctx       : ctl path ctx pointer
221 	 * @lm        : layer mixer enumeration
222 	 * @cfg       : blend stage configuration
223 	 */
224 	void (*setup_blendstage)(struct dpu_hw_ctl *ctx,
225 		enum dpu_lm lm, struct dpu_hw_stage_cfg *cfg);
226 
227 	void (*set_active_pipes)(struct dpu_hw_ctl *ctx,
228 		unsigned long *fetch_active);
229 };
230 
231 /**
232  * struct dpu_hw_ctl : CTL PATH driver object
233  * @base: hardware block base structure
234  * @hw: block register map object
235  * @idx: control path index
236  * @caps: control path capabilities
237  * @mixer_count: number of mixers
238  * @mixer_hw_caps: mixer hardware capabilities
239  * @pending_flush_mask: storage for pending ctl_flush managed via ops
240  * @pending_intf_flush_mask: pending INTF flush
241  * @pending_wb_flush_mask: pending WB flush
242  * @pending_dsc_flush_mask: pending DSC flush
243  * @ops: operation list
244  */
245 struct dpu_hw_ctl {
246 	struct dpu_hw_blk base;
247 	struct dpu_hw_blk_reg_map hw;
248 
249 	/* ctl path */
250 	int idx;
251 	const struct dpu_ctl_cfg *caps;
252 	int mixer_count;
253 	const struct dpu_lm_cfg *mixer_hw_caps;
254 	u32 pending_flush_mask;
255 	u32 pending_intf_flush_mask;
256 	u32 pending_wb_flush_mask;
257 	u32 pending_merge_3d_flush_mask;
258 	u32 pending_dspp_flush_mask[DSPP_MAX - DSPP_0];
259 	u32 pending_dsc_flush_mask;
260 
261 	/* ops */
262 	struct dpu_hw_ctl_ops ops;
263 };
264 
265 /**
266  * dpu_hw_ctl - convert base object dpu_hw_base to container
267  * @hw: Pointer to base hardware block
268  * return: Pointer to hardware block container
269  */
270 static inline struct dpu_hw_ctl *to_dpu_hw_ctl(struct dpu_hw_blk *hw)
271 {
272 	return container_of(hw, struct dpu_hw_ctl, base);
273 }
274 
275 /**
276  * dpu_hw_ctl_init() - Initializes the ctl_path hw driver object.
277  * Should be called before accessing any ctl_path register.
278  * @cfg:  ctl_path catalog entry for which driver object is required
279  * @addr: mapped register io address of MDP
280  * @mixer_count: Number of mixers in @mixer
281  * @mixer: Pointer to an array of Layer Mixers defined in the catalog
282  */
283 struct dpu_hw_ctl *dpu_hw_ctl_init(const struct dpu_ctl_cfg *cfg,
284 		void __iomem *addr,
285 		u32 mixer_count,
286 		const struct dpu_lm_cfg *mixer);
287 
288 /**
289  * dpu_hw_ctl_destroy(): Destroys ctl driver context
290  * should be called to free the context
291  */
292 void dpu_hw_ctl_destroy(struct dpu_hw_ctl *ctx);
293 
294 #endif /*_DPU_HW_CTL_H */
295