1 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 2 * 3 * This program is free software; you can redistribute it and/or modify 4 * it under the terms of the GNU General Public License version 2 and 5 * only version 2 as published by the Free Software Foundation. 6 * 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 */ 12 13 #ifndef _DPU_HW_CATALOG_H 14 #define _DPU_HW_CATALOG_H 15 16 #include <linux/kernel.h> 17 #include <linux/bug.h> 18 #include <linux/bitmap.h> 19 #include <linux/err.h> 20 #include <drm/drmP.h> 21 22 /** 23 * Max hardware block count: For ex: max 12 SSPP pipes or 24 * 5 ctl paths. In all cases, it can have max 12 hardware blocks 25 * based on current design 26 */ 27 #define MAX_BLOCKS 12 28 29 #define DPU_HW_VER(MAJOR, MINOR, STEP) (((MAJOR & 0xF) << 28) |\ 30 ((MINOR & 0xFFF) << 16) |\ 31 (STEP & 0xFFFF)) 32 33 #define DPU_HW_MAJOR(rev) ((rev) >> 28) 34 #define DPU_HW_MINOR(rev) (((rev) >> 16) & 0xFFF) 35 #define DPU_HW_STEP(rev) ((rev) & 0xFFFF) 36 #define DPU_HW_MAJOR_MINOR(rev) ((rev) >> 16) 37 38 #define IS_DPU_MAJOR_MINOR_SAME(rev1, rev2) \ 39 (DPU_HW_MAJOR_MINOR((rev1)) == DPU_HW_MAJOR_MINOR((rev2))) 40 41 #define DPU_HW_VER_170 DPU_HW_VER(1, 7, 0) /* 8996 v1.0 */ 42 #define DPU_HW_VER_171 DPU_HW_VER(1, 7, 1) /* 8996 v2.0 */ 43 #define DPU_HW_VER_172 DPU_HW_VER(1, 7, 2) /* 8996 v3.0 */ 44 #define DPU_HW_VER_300 DPU_HW_VER(3, 0, 0) /* 8998 v1.0 */ 45 #define DPU_HW_VER_301 DPU_HW_VER(3, 0, 1) /* 8998 v1.1 */ 46 #define DPU_HW_VER_400 DPU_HW_VER(4, 0, 0) /* sdm845 v1.0 */ 47 #define DPU_HW_VER_401 DPU_HW_VER(4, 0, 1) /* sdm845 v2.0 */ 48 #define DPU_HW_VER_410 DPU_HW_VER(4, 1, 0) /* sdm670 v1.0 */ 49 #define DPU_HW_VER_500 DPU_HW_VER(5, 0, 0) /* sdm855 v1.0 */ 50 51 52 #define IS_MSM8996_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_170) 53 #define IS_MSM8998_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_300) 54 #define IS_SDM845_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_400) 55 #define IS_SDM670_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_410) 56 #define IS_SDM855_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_500) 57 58 59 #define DPU_HW_BLK_NAME_LEN 16 60 61 #define MAX_IMG_WIDTH 0x3fff 62 #define MAX_IMG_HEIGHT 0x3fff 63 64 #define CRTC_DUAL_MIXERS 2 65 66 #define MAX_XIN_COUNT 16 67 68 /** 69 * Supported UBWC feature versions 70 */ 71 enum { 72 DPU_HW_UBWC_VER_10 = 0x100, 73 DPU_HW_UBWC_VER_20 = 0x200, 74 DPU_HW_UBWC_VER_30 = 0x300, 75 }; 76 77 #define IS_UBWC_20_SUPPORTED(rev) ((rev) >= DPU_HW_UBWC_VER_20) 78 79 /** 80 * MDP TOP BLOCK features 81 * @DPU_MDP_PANIC_PER_PIPE Panic configuration needs to be be done per pipe 82 * @DPU_MDP_10BIT_SUPPORT, Chipset supports 10 bit pixel formats 83 * @DPU_MDP_BWC, MDSS HW supports Bandwidth compression. 84 * @DPU_MDP_UBWC_1_0, This chipsets supports Universal Bandwidth 85 * compression initial revision 86 * @DPU_MDP_UBWC_1_5, Universal Bandwidth compression version 1.5 87 * @DPU_MDP_MAX Maximum value 88 89 */ 90 enum { 91 DPU_MDP_PANIC_PER_PIPE = 0x1, 92 DPU_MDP_10BIT_SUPPORT, 93 DPU_MDP_BWC, 94 DPU_MDP_UBWC_1_0, 95 DPU_MDP_UBWC_1_5, 96 DPU_MDP_MAX 97 }; 98 99 /** 100 * SSPP sub-blocks/features 101 * @DPU_SSPP_SRC Src and fetch part of the pipes, 102 * @DPU_SSPP_SCALER_QSEED2, QSEED2 algorithm support 103 * @DPU_SSPP_SCALER_QSEED3, QSEED3 alogorithm support 104 * @DPU_SSPP_SCALER_RGB, RGB Scaler, supported by RGB pipes 105 * @DPU_SSPP_CSC, Support of Color space converion 106 * @DPU_SSPP_CSC_10BIT, Support of 10-bit Color space conversion 107 * @DPU_SSPP_CURSOR, SSPP can be used as a cursor layer 108 * @DPU_SSPP_QOS, SSPP support QoS control, danger/safe/creq 109 * @DPU_SSPP_QOS_8LVL, SSPP support 8-level QoS control 110 * @DPU_SSPP_EXCL_RECT, SSPP supports exclusion rect 111 * @DPU_SSPP_SMART_DMA_V1, SmartDMA 1.0 support 112 * @DPU_SSPP_SMART_DMA_V2, SmartDMA 2.0 support 113 * @DPU_SSPP_TS_PREFILL Supports prefill with traffic shaper 114 * @DPU_SSPP_TS_PREFILL_REC1 Supports prefill with traffic shaper multirec 115 * @DPU_SSPP_CDP Supports client driven prefetch 116 * @DPU_SSPP_MAX maximum value 117 */ 118 enum { 119 DPU_SSPP_SRC = 0x1, 120 DPU_SSPP_SCALER_QSEED2, 121 DPU_SSPP_SCALER_QSEED3, 122 DPU_SSPP_SCALER_RGB, 123 DPU_SSPP_CSC, 124 DPU_SSPP_CSC_10BIT, 125 DPU_SSPP_CURSOR, 126 DPU_SSPP_QOS, 127 DPU_SSPP_QOS_8LVL, 128 DPU_SSPP_EXCL_RECT, 129 DPU_SSPP_SMART_DMA_V1, 130 DPU_SSPP_SMART_DMA_V2, 131 DPU_SSPP_TS_PREFILL, 132 DPU_SSPP_TS_PREFILL_REC1, 133 DPU_SSPP_CDP, 134 DPU_SSPP_MAX 135 }; 136 137 /* 138 * MIXER sub-blocks/features 139 * @DPU_MIXER_LAYER Layer mixer layer blend configuration, 140 * @DPU_MIXER_SOURCESPLIT Layer mixer supports source-split configuration 141 * @DPU_MIXER_GC Gamma correction block 142 * @DPU_DIM_LAYER Layer mixer supports dim layer 143 * @DPU_MIXER_MAX maximum value 144 */ 145 enum { 146 DPU_MIXER_LAYER = 0x1, 147 DPU_MIXER_SOURCESPLIT, 148 DPU_MIXER_GC, 149 DPU_DIM_LAYER, 150 DPU_MIXER_MAX 151 }; 152 153 /** 154 * PINGPONG sub-blocks 155 * @DPU_PINGPONG_TE Tear check block 156 * @DPU_PINGPONG_TE2 Additional tear check block for split pipes 157 * @DPU_PINGPONG_SPLIT PP block supports split fifo 158 * @DPU_PINGPONG_SLAVE PP block is a suitable slave for split fifo 159 * @DPU_PINGPONG_DITHER, Dither blocks 160 * @DPU_PINGPONG_MAX 161 */ 162 enum { 163 DPU_PINGPONG_TE = 0x1, 164 DPU_PINGPONG_TE2, 165 DPU_PINGPONG_SPLIT, 166 DPU_PINGPONG_SLAVE, 167 DPU_PINGPONG_DITHER, 168 DPU_PINGPONG_MAX 169 }; 170 171 /** 172 * CTL sub-blocks 173 * @DPU_CTL_SPLIT_DISPLAY CTL supports video mode split display 174 * @DPU_CTL_MAX 175 */ 176 enum { 177 DPU_CTL_SPLIT_DISPLAY = 0x1, 178 DPU_CTL_MAX 179 }; 180 181 /** 182 * VBIF sub-blocks and features 183 * @DPU_VBIF_QOS_OTLIM VBIF supports OT Limit 184 * @DPU_VBIF_QOS_REMAP VBIF supports QoS priority remap 185 * @DPU_VBIF_MAX maximum value 186 */ 187 enum { 188 DPU_VBIF_QOS_OTLIM = 0x1, 189 DPU_VBIF_QOS_REMAP, 190 DPU_VBIF_MAX 191 }; 192 193 /** 194 * MACRO DPU_HW_BLK_INFO - information of HW blocks inside DPU 195 * @name: string name for debug purposes 196 * @id: enum identifying this block 197 * @base: register base offset to mdss 198 * @len: length of hardware block 199 * @features bit mask identifying sub-blocks/features 200 */ 201 #define DPU_HW_BLK_INFO \ 202 char name[DPU_HW_BLK_NAME_LEN]; \ 203 u32 id; \ 204 u32 base; \ 205 u32 len; \ 206 unsigned long features 207 208 /** 209 * MACRO DPU_HW_SUBBLK_INFO - information of HW sub-block inside DPU 210 * @name: string name for debug purposes 211 * @id: enum identifying this sub-block 212 * @base: offset of this sub-block relative to the block 213 * offset 214 * @len register block length of this sub-block 215 */ 216 #define DPU_HW_SUBBLK_INFO \ 217 char name[DPU_HW_BLK_NAME_LEN]; \ 218 u32 id; \ 219 u32 base; \ 220 u32 len 221 222 /** 223 * struct dpu_src_blk: SSPP part of the source pipes 224 * @info: HW register and features supported by this sub-blk 225 */ 226 struct dpu_src_blk { 227 DPU_HW_SUBBLK_INFO; 228 }; 229 230 /** 231 * struct dpu_scaler_blk: Scaler information 232 * @info: HW register and features supported by this sub-blk 233 * @version: qseed block revision 234 */ 235 struct dpu_scaler_blk { 236 DPU_HW_SUBBLK_INFO; 237 u32 version; 238 }; 239 240 struct dpu_csc_blk { 241 DPU_HW_SUBBLK_INFO; 242 }; 243 244 /** 245 * struct dpu_pp_blk : Pixel processing sub-blk information 246 * @info: HW register and features supported by this sub-blk 247 * @version: HW Algorithm version 248 */ 249 struct dpu_pp_blk { 250 DPU_HW_SUBBLK_INFO; 251 u32 version; 252 }; 253 254 /** 255 * enum dpu_qos_lut_usage - define QoS LUT use cases 256 */ 257 enum dpu_qos_lut_usage { 258 DPU_QOS_LUT_USAGE_LINEAR, 259 DPU_QOS_LUT_USAGE_MACROTILE, 260 DPU_QOS_LUT_USAGE_NRT, 261 DPU_QOS_LUT_USAGE_MAX, 262 }; 263 264 /** 265 * struct dpu_qos_lut_entry - define QoS LUT table entry 266 * @fl: fill level, or zero on last entry to indicate default lut 267 * @lut: lut to use if equal to or less than fill level 268 */ 269 struct dpu_qos_lut_entry { 270 u32 fl; 271 u64 lut; 272 }; 273 274 /** 275 * struct dpu_qos_lut_tbl - define QoS LUT table 276 * @nentry: number of entry in this table 277 * @entries: Pointer to table entries 278 */ 279 struct dpu_qos_lut_tbl { 280 u32 nentry; 281 struct dpu_qos_lut_entry *entries; 282 }; 283 284 /** 285 * struct dpu_caps - define DPU capabilities 286 * @max_mixer_width max layer mixer line width support. 287 * @max_mixer_blendstages max layer mixer blend stages or 288 * supported z order 289 * @qseed_type qseed2 or qseed3 support. 290 * @smart_dma_rev Supported version of SmartDMA feature. 291 * @ubwc_version UBWC feature version (0x0 for not supported) 292 * @has_src_split source split feature status 293 * @has_dim_layer dim layer feature status 294 * @has_idle_pc indicate if idle power collapse feature is supported 295 */ 296 struct dpu_caps { 297 u32 max_mixer_width; 298 u32 max_mixer_blendstages; 299 u32 qseed_type; 300 u32 smart_dma_rev; 301 u32 ubwc_version; 302 bool has_src_split; 303 bool has_dim_layer; 304 bool has_idle_pc; 305 }; 306 307 /** 308 * struct dpu_sspp_blks_common : SSPP sub-blocks common configuration 309 * @maxwidth: max pixelwidth supported by this pipe 310 * @pixel_ram_size: size of latency hiding and de-tiling buffer in bytes 311 * @maxhdeciexp: max horizontal decimation supported by this pipe 312 * (max is 2^value) 313 * @maxvdeciexp: max vertical decimation supported by this pipe 314 * (max is 2^value) 315 */ 316 struct dpu_sspp_blks_common { 317 u32 maxlinewidth; 318 u32 pixel_ram_size; 319 u32 maxhdeciexp; 320 u32 maxvdeciexp; 321 }; 322 323 /** 324 * struct dpu_sspp_sub_blks : SSPP sub-blocks 325 * common: Pointer to common configurations shared by sub blocks 326 * @creq_vblank: creq priority during vertical blanking 327 * @danger_vblank: danger priority during vertical blanking 328 * @maxdwnscale: max downscale ratio supported(without DECIMATION) 329 * @maxupscale: maxupscale ratio supported 330 * @smart_dma_priority: hw priority of rect1 of multirect pipe 331 * @max_per_pipe_bw: maximum allowable bandwidth of this pipe in kBps 332 * @src_blk: 333 * @scaler_blk: 334 * @csc_blk: 335 * @hsic: 336 * @memcolor: 337 * @pcc_blk: 338 * @igc_blk: 339 * @format_list: Pointer to list of supported formats 340 * @num_formats: Number of supported formats 341 * @virt_format_list: Pointer to list of supported formats for virtual planes 342 * @virt_num_formats: Number of supported formats for virtual planes 343 */ 344 struct dpu_sspp_sub_blks { 345 const struct dpu_sspp_blks_common *common; 346 u32 creq_vblank; 347 u32 danger_vblank; 348 u32 maxdwnscale; 349 u32 maxupscale; 350 u32 smart_dma_priority; 351 u32 max_per_pipe_bw; 352 struct dpu_src_blk src_blk; 353 struct dpu_scaler_blk scaler_blk; 354 struct dpu_pp_blk csc_blk; 355 struct dpu_pp_blk hsic_blk; 356 struct dpu_pp_blk memcolor_blk; 357 struct dpu_pp_blk pcc_blk; 358 struct dpu_pp_blk igc_blk; 359 360 const u32 *format_list; 361 u32 num_formats; 362 const u32 *virt_format_list; 363 u32 virt_num_formats; 364 }; 365 366 /** 367 * struct dpu_lm_sub_blks: information of mixer block 368 * @maxwidth: Max pixel width supported by this mixer 369 * @maxblendstages: Max number of blend-stages supported 370 * @blendstage_base: Blend-stage register base offset 371 * @gc: gamma correction block 372 */ 373 struct dpu_lm_sub_blks { 374 u32 maxwidth; 375 u32 maxblendstages; 376 u32 blendstage_base[MAX_BLOCKS]; 377 struct dpu_pp_blk gc; 378 }; 379 380 struct dpu_pingpong_sub_blks { 381 struct dpu_pp_blk te; 382 struct dpu_pp_blk te2; 383 struct dpu_pp_blk dither; 384 }; 385 386 /** 387 * dpu_clk_ctrl_type - Defines top level clock control signals 388 */ 389 enum dpu_clk_ctrl_type { 390 DPU_CLK_CTRL_NONE, 391 DPU_CLK_CTRL_VIG0, 392 DPU_CLK_CTRL_VIG1, 393 DPU_CLK_CTRL_VIG2, 394 DPU_CLK_CTRL_VIG3, 395 DPU_CLK_CTRL_VIG4, 396 DPU_CLK_CTRL_RGB0, 397 DPU_CLK_CTRL_RGB1, 398 DPU_CLK_CTRL_RGB2, 399 DPU_CLK_CTRL_RGB3, 400 DPU_CLK_CTRL_DMA0, 401 DPU_CLK_CTRL_DMA1, 402 DPU_CLK_CTRL_CURSOR0, 403 DPU_CLK_CTRL_CURSOR1, 404 DPU_CLK_CTRL_INLINE_ROT0_SSPP, 405 DPU_CLK_CTRL_MAX, 406 }; 407 408 /* struct dpu_clk_ctrl_reg : Clock control register 409 * @reg_off: register offset 410 * @bit_off: bit offset 411 */ 412 struct dpu_clk_ctrl_reg { 413 u32 reg_off; 414 u32 bit_off; 415 }; 416 417 /* struct dpu_mdp_cfg : MDP TOP-BLK instance info 418 * @id: index identifying this block 419 * @base: register base offset to mdss 420 * @features bit mask identifying sub-blocks/features 421 * @highest_bank_bit: UBWC parameter 422 * @ubwc_static: ubwc static configuration 423 * @ubwc_swizzle: ubwc default swizzle setting 424 * @clk_ctrls clock control register definition 425 */ 426 struct dpu_mdp_cfg { 427 DPU_HW_BLK_INFO; 428 u32 highest_bank_bit; 429 u32 ubwc_static; 430 u32 ubwc_swizzle; 431 struct dpu_clk_ctrl_reg clk_ctrls[DPU_CLK_CTRL_MAX]; 432 }; 433 434 /* struct dpu_mdp_cfg : MDP TOP-BLK instance info 435 * @id: index identifying this block 436 * @base: register base offset to mdss 437 * @features bit mask identifying sub-blocks/features 438 */ 439 struct dpu_ctl_cfg { 440 DPU_HW_BLK_INFO; 441 }; 442 443 /** 444 * struct dpu_sspp_cfg - information of source pipes 445 * @id: index identifying this block 446 * @base register offset of this block 447 * @features bit mask identifying sub-blocks/features 448 * @sblk: SSPP sub-blocks information 449 * @xin_id: bus client identifier 450 * @clk_ctrl clock control identifier 451 * @type sspp type identifier 452 */ 453 struct dpu_sspp_cfg { 454 DPU_HW_BLK_INFO; 455 const struct dpu_sspp_sub_blks *sblk; 456 u32 xin_id; 457 enum dpu_clk_ctrl_type clk_ctrl; 458 u32 type; 459 }; 460 461 /** 462 * struct dpu_lm_cfg - information of layer mixer blocks 463 * @id: index identifying this block 464 * @base register offset of this block 465 * @features bit mask identifying sub-blocks/features 466 * @sblk: LM Sub-blocks information 467 * @pingpong: ID of connected PingPong, PINGPONG_MAX if unsupported 468 * @lm_pair_mask: Bitmask of LMs that can be controlled by same CTL 469 */ 470 struct dpu_lm_cfg { 471 DPU_HW_BLK_INFO; 472 const struct dpu_lm_sub_blks *sblk; 473 u32 pingpong; 474 unsigned long lm_pair_mask; 475 }; 476 477 /** 478 * struct dpu_pingpong_cfg - information of PING-PONG blocks 479 * @id enum identifying this block 480 * @base register offset of this block 481 * @features bit mask identifying sub-blocks/features 482 * @sblk sub-blocks information 483 */ 484 struct dpu_pingpong_cfg { 485 DPU_HW_BLK_INFO; 486 const struct dpu_pingpong_sub_blks *sblk; 487 }; 488 489 /** 490 * struct dpu_intf_cfg - information of timing engine blocks 491 * @id enum identifying this block 492 * @base register offset of this block 493 * @features bit mask identifying sub-blocks/features 494 * @type: Interface type(DSI, DP, HDMI) 495 * @controller_id: Controller Instance ID in case of multiple of intf type 496 * @prog_fetch_lines_worst_case Worst case latency num lines needed to prefetch 497 */ 498 struct dpu_intf_cfg { 499 DPU_HW_BLK_INFO; 500 u32 type; /* interface type*/ 501 u32 controller_id; 502 u32 prog_fetch_lines_worst_case; 503 }; 504 505 /** 506 * struct dpu_vbif_dynamic_ot_cfg - dynamic OT setting 507 * @pps pixel per seconds 508 * @ot_limit OT limit to use up to specified pixel per second 509 */ 510 struct dpu_vbif_dynamic_ot_cfg { 511 u64 pps; 512 u32 ot_limit; 513 }; 514 515 /** 516 * struct dpu_vbif_dynamic_ot_tbl - dynamic OT setting table 517 * @count length of cfg 518 * @cfg pointer to array of configuration settings with 519 * ascending requirements 520 */ 521 struct dpu_vbif_dynamic_ot_tbl { 522 u32 count; 523 struct dpu_vbif_dynamic_ot_cfg *cfg; 524 }; 525 526 /** 527 * struct dpu_vbif_qos_tbl - QoS priority table 528 * @npriority_lvl num of priority level 529 * @priority_lvl pointer to array of priority level in ascending order 530 */ 531 struct dpu_vbif_qos_tbl { 532 u32 npriority_lvl; 533 u32 *priority_lvl; 534 }; 535 536 /** 537 * struct dpu_vbif_cfg - information of VBIF blocks 538 * @id enum identifying this block 539 * @base register offset of this block 540 * @features bit mask identifying sub-blocks/features 541 * @ot_rd_limit default OT read limit 542 * @ot_wr_limit default OT write limit 543 * @xin_halt_timeout maximum time (in usec) for xin to halt 544 * @dynamic_ot_rd_tbl dynamic OT read configuration table 545 * @dynamic_ot_wr_tbl dynamic OT write configuration table 546 * @qos_rt_tbl real-time QoS priority table 547 * @qos_nrt_tbl non-real-time QoS priority table 548 * @memtype_count number of defined memtypes 549 * @memtype array of xin memtype definitions 550 */ 551 struct dpu_vbif_cfg { 552 DPU_HW_BLK_INFO; 553 u32 default_ot_rd_limit; 554 u32 default_ot_wr_limit; 555 u32 xin_halt_timeout; 556 struct dpu_vbif_dynamic_ot_tbl dynamic_ot_rd_tbl; 557 struct dpu_vbif_dynamic_ot_tbl dynamic_ot_wr_tbl; 558 struct dpu_vbif_qos_tbl qos_rt_tbl; 559 struct dpu_vbif_qos_tbl qos_nrt_tbl; 560 u32 memtype_count; 561 u32 memtype[MAX_XIN_COUNT]; 562 }; 563 /** 564 * struct dpu_reg_dma_cfg - information of lut dma blocks 565 * @id enum identifying this block 566 * @base register offset of this block 567 * @features bit mask identifying sub-blocks/features 568 * @version version of lutdma hw block 569 * @trigger_sel_off offset to trigger select registers of lutdma 570 */ 571 struct dpu_reg_dma_cfg { 572 DPU_HW_BLK_INFO; 573 u32 version; 574 u32 trigger_sel_off; 575 }; 576 577 /** 578 * Define CDP use cases 579 * @DPU_PERF_CDP_UDAGE_RT: real-time use cases 580 * @DPU_PERF_CDP_USAGE_NRT: non real-time use cases such as WFD 581 */ 582 enum { 583 DPU_PERF_CDP_USAGE_RT, 584 DPU_PERF_CDP_USAGE_NRT, 585 DPU_PERF_CDP_USAGE_MAX 586 }; 587 588 /** 589 * struct dpu_perf_cdp_cfg - define CDP use case configuration 590 * @rd_enable: true if read pipe CDP is enabled 591 * @wr_enable: true if write pipe CDP is enabled 592 */ 593 struct dpu_perf_cdp_cfg { 594 bool rd_enable; 595 bool wr_enable; 596 }; 597 598 /** 599 * struct dpu_perf_cfg - performance control settings 600 * @max_bw_low low threshold of maximum bandwidth (kbps) 601 * @max_bw_high high threshold of maximum bandwidth (kbps) 602 * @min_core_ib minimum bandwidth for core (kbps) 603 * @min_core_ib minimum mnoc ib vote in kbps 604 * @min_llcc_ib minimum llcc ib vote in kbps 605 * @min_dram_ib minimum dram ib vote in kbps 606 * @core_ib_ff core instantaneous bandwidth fudge factor 607 * @core_clk_ff core clock fudge factor 608 * @comp_ratio_rt string of 0 or more of <fourcc>/<ven>/<mod>/<comp ratio> 609 * @comp_ratio_nrt string of 0 or more of <fourcc>/<ven>/<mod>/<comp ratio> 610 * @undersized_prefill_lines undersized prefill in lines 611 * @xtra_prefill_lines extra prefill latency in lines 612 * @dest_scale_prefill_lines destination scaler latency in lines 613 * @macrotile_perfill_lines macrotile latency in lines 614 * @yuv_nv12_prefill_lines yuv_nv12 latency in lines 615 * @linear_prefill_lines linear latency in lines 616 * @downscaling_prefill_lines downscaling latency in lines 617 * @amortizable_theshold minimum y position for traffic shaping prefill 618 * @min_prefill_lines minimum pipeline latency in lines 619 * @safe_lut_tbl: LUT tables for safe signals 620 * @danger_lut_tbl: LUT tables for danger signals 621 * @qos_lut_tbl: LUT tables for QoS signals 622 * @cdp_cfg cdp use case configurations 623 */ 624 struct dpu_perf_cfg { 625 u32 max_bw_low; 626 u32 max_bw_high; 627 u32 min_core_ib; 628 u32 min_llcc_ib; 629 u32 min_dram_ib; 630 const char *core_ib_ff; 631 const char *core_clk_ff; 632 const char *comp_ratio_rt; 633 const char *comp_ratio_nrt; 634 u32 undersized_prefill_lines; 635 u32 xtra_prefill_lines; 636 u32 dest_scale_prefill_lines; 637 u32 macrotile_prefill_lines; 638 u32 yuv_nv12_prefill_lines; 639 u32 linear_prefill_lines; 640 u32 downscaling_prefill_lines; 641 u32 amortizable_threshold; 642 u32 min_prefill_lines; 643 u32 safe_lut_tbl[DPU_QOS_LUT_USAGE_MAX]; 644 u32 danger_lut_tbl[DPU_QOS_LUT_USAGE_MAX]; 645 struct dpu_qos_lut_tbl qos_lut_tbl[DPU_QOS_LUT_USAGE_MAX]; 646 struct dpu_perf_cdp_cfg cdp_cfg[DPU_PERF_CDP_USAGE_MAX]; 647 }; 648 649 /** 650 * struct dpu_mdss_cfg - information of MDSS HW 651 * This is the main catalog data structure representing 652 * this HW version. Contains number of instances, 653 * register offsets, capabilities of the all MDSS HW sub-blocks. 654 * 655 * @dma_formats Supported formats for dma pipe 656 * @cursor_formats Supported formats for cursor pipe 657 * @vig_formats Supported formats for vig pipe 658 */ 659 struct dpu_mdss_cfg { 660 u32 hwversion; 661 662 const struct dpu_caps *caps; 663 664 u32 mdp_count; 665 struct dpu_mdp_cfg *mdp; 666 667 u32 ctl_count; 668 struct dpu_ctl_cfg *ctl; 669 670 u32 sspp_count; 671 struct dpu_sspp_cfg *sspp; 672 673 u32 mixer_count; 674 struct dpu_lm_cfg *mixer; 675 676 u32 pingpong_count; 677 struct dpu_pingpong_cfg *pingpong; 678 679 u32 intf_count; 680 struct dpu_intf_cfg *intf; 681 682 u32 vbif_count; 683 struct dpu_vbif_cfg *vbif; 684 685 u32 reg_dma_count; 686 struct dpu_reg_dma_cfg dma_cfg; 687 688 u32 ad_count; 689 690 /* Add additional block data structures here */ 691 692 struct dpu_perf_cfg perf; 693 struct dpu_format_extended *dma_formats; 694 struct dpu_format_extended *cursor_formats; 695 struct dpu_format_extended *vig_formats; 696 }; 697 698 struct dpu_mdss_hw_cfg_handler { 699 u32 hw_rev; 700 void (*cfg_init)(struct dpu_mdss_cfg *dpu_cfg); 701 }; 702 703 /* 704 * Access Macros 705 */ 706 #define BLK_MDP(s) ((s)->mdp) 707 #define BLK_CTL(s) ((s)->ctl) 708 #define BLK_VIG(s) ((s)->vig) 709 #define BLK_RGB(s) ((s)->rgb) 710 #define BLK_DMA(s) ((s)->dma) 711 #define BLK_CURSOR(s) ((s)->cursor) 712 #define BLK_MIXER(s) ((s)->mixer) 713 #define BLK_PINGPONG(s) ((s)->pingpong) 714 #define BLK_INTF(s) ((s)->intf) 715 #define BLK_AD(s) ((s)->ad) 716 717 /** 718 * dpu_hw_catalog_init - dpu hardware catalog init API retrieves 719 * hardcoded target specific catalog information in config structure 720 * @hw_rev: caller needs provide the hardware revision. 721 * 722 * Return: dpu config structure 723 */ 724 struct dpu_mdss_cfg *dpu_hw_catalog_init(u32 hw_rev); 725 726 /** 727 * dpu_hw_catalog_deinit - dpu hardware catalog cleanup 728 * @dpu_cfg: pointer returned from init function 729 */ 730 void dpu_hw_catalog_deinit(struct dpu_mdss_cfg *dpu_cfg); 731 732 #endif /* _DPU_HW_CATALOG_H */ 733